| Nirav Dave | 4e363e3 | 2017-06-19 15:18:20 +0000 | [diff] [blame] | 1 | ; RUN: llc -o - %s | FileCheck %s |
| 2 | |
| 3 | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" |
| 4 | target triple = "arm64-apple-ios10.0.0" |
| 5 | |
| 6 | ; PR33475 - Expect 64-bit operations as 128-operations are not legal |
| Sirish Pande | cabe50a3 | 2018-05-16 15:36:52 +0000 | [diff] [blame] | 7 | ; However, we can generate a paired 64-bit loads and stores, without using |
| 8 | ; floating point registers. |
| Nirav Dave | 4e363e3 | 2017-06-19 15:18:20 +0000 | [diff] [blame] | 9 | |
| 10 | ; CHECK-LABEL: pr33475 |
| Sirish Pande | cabe50a3 | 2018-05-16 15:36:52 +0000 | [diff] [blame] | 11 | ; CHECK-DAG: ldp [[R0:x[0-9]+]], [[R0:x[0-9]+]], [x1, #16] |
| 12 | ; CHECK-DAG: ldp [[R0:x[0-9]+]], [[R0:x[0-9]+]], [x1] |
| 13 | ; CHECK-DAG: stp [[R0:x[0-9]+]], [[R0:x[0-9]+]], [x0, #16] |
| 14 | ; CHECK-DAG: stp [[R0:x[0-9]+]], [[R0:x[0-9]+]], [x0] |
| Nirav Dave | 4e363e3 | 2017-06-19 15:18:20 +0000 | [diff] [blame] | 15 | |
| 16 | define void @pr33475(i8* %p0, i8* %p1) noimplicitfloat { |
| Daniel Neilson | 1e68724 | 2018-01-19 17:13:12 +0000 | [diff] [blame] | 17 | call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %p0, i8* align 4 %p1, i64 32, i1 false) |
| Nirav Dave | 4e363e3 | 2017-06-19 15:18:20 +0000 | [diff] [blame] | 18 | ret void |
| 19 | } |
| 20 | |
| Daniel Neilson | 1e68724 | 2018-01-19 17:13:12 +0000 | [diff] [blame] | 21 | declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i1) |