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gerrit-public.fairphone.software / toolchain / llvm-project / 91be65be656072a68b51a8c4e7bb751ea475d896 / . / llvm / test / CodeGen / SPARC / rem.ll
blob: 0dbd853c7d90e2beb9baaf3bd2346143df955bbe [file] [log] [blame]
Simon Pilgrimcbf5af12018-07-20 13:14:29 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s
Roman Divacky2262cfa2013-10-31 19:22:33 +0000[diff] [blame]3
4define i64 @test1(i64 %X, i64 %Y) {
Simon Pilgrimcbf5af12018-07-20 13:14:29 +0000[diff] [blame]5; CHECK-LABEL: test1:
6; CHECK: .cfi_startproc
7; CHECK-NEXT: ! %bb.0:
8; CHECK-NEXT: sdivx %o0, %o1, %o2
9; CHECK-NEXT: mulx %o2, %o1, %o1
10; CHECK-NEXT: retl
11; CHECK-NEXT: sub %o0, %o1, %o0
12 %tmp1 = srem i64 %X, %Y
13 ret i64 %tmp1
Roman Divacky2262cfa2013-10-31 19:22:33 +0000[diff] [blame]14}
15
Roman Divacky2262cfa2013-10-31 19:22:33 +0000[diff] [blame]16define i64 @test2(i64 %X, i64 %Y) {
Simon Pilgrimcbf5af12018-07-20 13:14:29 +0000[diff] [blame]17; CHECK-LABEL: test2:
18; CHECK: .cfi_startproc
19; CHECK-NEXT: ! %bb.0:
20; CHECK-NEXT: udivx %o0, %o1, %o2
21; CHECK-NEXT: mulx %o2, %o1, %o1
22; CHECK-NEXT: retl
23; CHECK-NEXT: sub %o0, %o1, %o0
24 %tmp1 = urem i64 %X, %Y
25 ret i64 %tmp1
Roman Divacky2262cfa2013-10-31 19:22:33 +0000[diff] [blame]26}
Venkatraman Govindaraju72cc2482013-12-08 22:06:07 +0000[diff] [blame]27
28; PR18150
Venkatraman Govindaraju72cc2482013-12-08 22:06:07 +0000[diff] [blame]29define i64 @test3(i64 %b) {
Simon Pilgrimcbf5af12018-07-20 13:14:29 +0000[diff] [blame]30; CHECK-LABEL: test3:
31; CHECK: .cfi_startproc
32; CHECK-NEXT: ! %bb.0: ! %entry
33; CHECK-NEXT: sethi 2545, %o1
34; CHECK-NEXT: or %o1, 379, %o1
35; CHECK-NEXT: mulx %o0, %o1, %o0
36; CHECK-NEXT: udivx %o0, 1021, %o1
37; CHECK-NEXT: mulx %o1, 1021, %o1
38; CHECK-NEXT: retl
39; CHECK-NEXT: sub %o0, %o1, %o0
Venkatraman Govindaraju72cc2482013-12-08 22:06:07 +0000[diff] [blame]40entry:
41 %mul = mul i64 %b, 2606459
42 %rem = urem i64 %mul, 1021
43 ret i64 %rem
44}