Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 1 | ; Test 64-bit compare and swap. |
| 2 | ; |
| 3 | ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s |
| 4 | |
| 5 | ; Check CSG without a displacement. |
| 6 | define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 7 | ; CHECK-LABEL: f1: |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 8 | ; CHECK: csg %r2, %r3, 0(%r4) |
| 9 | ; CHECK: br %r14 |
Tim Northover | 420a216 | 2014-06-13 14:24:07 +0000 | [diff] [blame] | 10 | %pairval = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst seq_cst |
| 11 | %val = extractvalue { i64, i1 } %pairval, 0 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 12 | ret i64 %val |
| 13 | } |
| 14 | |
| 15 | ; Check the high end of the aligned CSG range. |
| 16 | define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 17 | ; CHECK-LABEL: f2: |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 18 | ; CHECK: csg %r2, %r3, 524280(%r4) |
| 19 | ; CHECK: br %r14 |
David Blaikie | 79e6c74 | 2015-02-27 19:29:02 +0000 | [diff] [blame] | 20 | %ptr = getelementptr i64, i64 *%src, i64 65535 |
Tim Northover | 420a216 | 2014-06-13 14:24:07 +0000 | [diff] [blame] | 21 | %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst |
| 22 | %val = extractvalue { i64, i1 } %pairval, 0 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 23 | ret i64 %val |
| 24 | } |
| 25 | |
| 26 | ; Check the next doubleword up, which needs separate address logic. |
| 27 | ; Other sequences besides this one would be OK. |
| 28 | define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 29 | ; CHECK-LABEL: f3: |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 30 | ; CHECK: agfi %r4, 524288 |
| 31 | ; CHECK: csg %r2, %r3, 0(%r4) |
| 32 | ; CHECK: br %r14 |
David Blaikie | 79e6c74 | 2015-02-27 19:29:02 +0000 | [diff] [blame] | 33 | %ptr = getelementptr i64, i64 *%src, i64 65536 |
Tim Northover | 420a216 | 2014-06-13 14:24:07 +0000 | [diff] [blame] | 34 | %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst |
| 35 | %val = extractvalue { i64, i1 } %pairval, 0 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 36 | ret i64 %val |
| 37 | } |
| 38 | |
| 39 | ; Check the high end of the negative aligned CSG range. |
| 40 | define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 41 | ; CHECK-LABEL: f4: |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 42 | ; CHECK: csg %r2, %r3, -8(%r4) |
| 43 | ; CHECK: br %r14 |
David Blaikie | 79e6c74 | 2015-02-27 19:29:02 +0000 | [diff] [blame] | 44 | %ptr = getelementptr i64, i64 *%src, i64 -1 |
Tim Northover | 420a216 | 2014-06-13 14:24:07 +0000 | [diff] [blame] | 45 | %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst |
| 46 | %val = extractvalue { i64, i1 } %pairval, 0 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 47 | ret i64 %val |
| 48 | } |
| 49 | |
| 50 | ; Check the low end of the CSG range. |
| 51 | define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 52 | ; CHECK-LABEL: f5: |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 53 | ; CHECK: csg %r2, %r3, -524288(%r4) |
| 54 | ; CHECK: br %r14 |
David Blaikie | 79e6c74 | 2015-02-27 19:29:02 +0000 | [diff] [blame] | 55 | %ptr = getelementptr i64, i64 *%src, i64 -65536 |
Tim Northover | 420a216 | 2014-06-13 14:24:07 +0000 | [diff] [blame] | 56 | %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst |
| 57 | %val = extractvalue { i64, i1 } %pairval, 0 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 58 | ret i64 %val |
| 59 | } |
| 60 | |
| 61 | ; Check the next doubleword down, which needs separate address logic. |
| 62 | ; Other sequences besides this one would be OK. |
| 63 | define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 64 | ; CHECK-LABEL: f6: |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 65 | ; CHECK: agfi %r4, -524296 |
| 66 | ; CHECK: csg %r2, %r3, 0(%r4) |
| 67 | ; CHECK: br %r14 |
David Blaikie | 79e6c74 | 2015-02-27 19:29:02 +0000 | [diff] [blame] | 68 | %ptr = getelementptr i64, i64 *%src, i64 -65537 |
Tim Northover | 420a216 | 2014-06-13 14:24:07 +0000 | [diff] [blame] | 69 | %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst |
| 70 | %val = extractvalue { i64, i1 } %pairval, 0 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 71 | ret i64 %val |
| 72 | } |
| 73 | |
| 74 | ; Check that CSG does not allow an index. |
| 75 | define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 76 | ; CHECK-LABEL: f7: |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 77 | ; CHECK: agr %r4, %r5 |
| 78 | ; CHECK: csg %r2, %r3, 0(%r4) |
| 79 | ; CHECK: br %r14 |
| 80 | %add1 = add i64 %src, %index |
| 81 | %ptr = inttoptr i64 %add1 to i64 * |
Tim Northover | 420a216 | 2014-06-13 14:24:07 +0000 | [diff] [blame] | 82 | %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst |
| 83 | %val = extractvalue { i64, i1 } %pairval, 0 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 84 | ret i64 %val |
| 85 | } |
| 86 | |
| 87 | ; Check that a constant %cmp value is loaded into a register first. |
| 88 | define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 89 | ; CHECK-LABEL: f8: |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 90 | ; CHECK: lghi %r2, 1001 |
| 91 | ; CHECK: csg %r2, %r3, 0(%r4) |
| 92 | ; CHECK: br %r14 |
Tim Northover | 420a216 | 2014-06-13 14:24:07 +0000 | [diff] [blame] | 93 | %pairval = cmpxchg i64 *%ptr, i64 1001, i64 %swap seq_cst seq_cst |
| 94 | %val = extractvalue { i64, i1 } %pairval, 0 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 95 | ret i64 %val |
| 96 | } |
| 97 | |
| 98 | ; Check that a constant %swap value is loaded into a register first. |
| 99 | define i64 @f9(i64 %cmp, i64 *%ptr) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 100 | ; CHECK-LABEL: f9: |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 101 | ; CHECK: lghi [[SWAP:%r[0-9]+]], 1002 |
| 102 | ; CHECK: csg %r2, [[SWAP]], 0(%r3) |
| 103 | ; CHECK: br %r14 |
Tim Northover | 420a216 | 2014-06-13 14:24:07 +0000 | [diff] [blame] | 104 | %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 1002 seq_cst seq_cst |
| 105 | %val = extractvalue { i64, i1 } %pairval, 0 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 106 | ret i64 %val |
| 107 | } |
Ulrich Weigand | 0f1de04 | 2017-09-28 16:22:54 +0000 | [diff] [blame] | 108 | |
| 109 | ; Check generating the comparison result. |
| 110 | ; CHECK-LABEL: f10 |
| 111 | ; CHECK: csg %r2, %r3, 0(%r4) |
| 112 | ; CHECK-NEXT: ipm %r2 |
| 113 | ; CHECK-NEXT: afi %r2, -268435456 |
| 114 | ; CHECK-NEXT: srl %r2, 31 |
| 115 | ; CHECK: br %r14 |
| 116 | define i32 @f10(i64 %cmp, i64 %swap, i64 *%src) { |
| 117 | %pairval = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst seq_cst |
| 118 | %val = extractvalue { i64, i1 } %pairval, 1 |
| 119 | %res = zext i1 %val to i32 |
| 120 | ret i32 %res |
| 121 | } |
| 122 | |
Ulrich Weigand | 3111289 | 2018-01-19 20:54:18 +0000 | [diff] [blame] | 123 | declare void @g() |
| 124 | |
| 125 | ; Check using the comparison result for a branch. |
| 126 | ; CHECK-LABEL: f11 |
| 127 | ; CHECK: csg %r2, %r3, 0(%r4) |
| 128 | ; CHECK-NEXT: jge g |
| 129 | ; CHECK: br %r14 |
| 130 | define void @f11(i64 %cmp, i64 %swap, i64 *%src) { |
| 131 | %pairval = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst seq_cst |
| 132 | %cond = extractvalue { i64, i1 } %pairval, 1 |
| 133 | br i1 %cond, label %call, label %exit |
| 134 | |
| 135 | call: |
| 136 | tail call void @g() |
| 137 | br label %exit |
| 138 | |
| 139 | exit: |
| 140 | ret void |
| 141 | } |
| 142 | |
| 143 | ; ... and the same with the inverted direction. |
| 144 | ; CHECK-LABEL: f12 |
| 145 | ; CHECK: csg %r2, %r3, 0(%r4) |
| 146 | ; CHECK-NEXT: jgl g |
| 147 | ; CHECK: br %r14 |
| 148 | define void @f12(i64 %cmp, i64 %swap, i64 *%src) { |
| 149 | %pairval = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst seq_cst |
| 150 | %cond = extractvalue { i64, i1 } %pairval, 1 |
| 151 | br i1 %cond, label %exit, label %call |
| 152 | |
| 153 | call: |
| 154 | tail call void @g() |
| 155 | br label %exit |
| 156 | |
| 157 | exit: |
| 158 | ret void |
| 159 | } |
| 160 | |