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Ulrich Weigand33435c42017-07-17 17:42:48 +00001; Test vector addition on z14.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
4
5; Test a v4f32 addition.
6define <4 x float> @f1(<4 x float> %dummy, <4 x float> %val1,
7 <4 x float> %val2) {
8; CHECK-LABEL: f1:
9; CHECK: vfasb %v24, %v26, %v28
10; CHECK: br %r14
11 %ret = fadd <4 x float> %val1, %val2
12 ret <4 x float> %ret
13}
14
15; Test an f32 addition that uses vector registers.
16define float @f2(<4 x float> %val1, <4 x float> %val2) {
17; CHECK-LABEL: f2:
18; CHECK: wfasb %f0, %v24, %v26
19; CHECK: br %r14
20 %scalar1 = extractelement <4 x float> %val1, i32 0
21 %scalar2 = extractelement <4 x float> %val2, i32 0
22 %ret = fadd float %scalar1, %scalar2
23 ret float %ret
24}