blob: 9d87797c8f9240c243852c2cc450f230b7324a75 [file] [log] [blame]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +00001; Test moves between FPRs and GPRs.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
4
5; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high
6; 32 bits of the FPR.
7define float @f1(i32 %a) {
8; CHECK: f1:
9; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 32
10; CHECK: ldgr %f0, [[REGISTER]]
11 %res = bitcast i32 %a to float
12 ret float %res
13}
14
15; Like f1, but create a situation where the shift can be folded with
16; surrounding code.
17define float @f2(i64 %big) {
18; CHECK: f2:
19; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 31
20; CHECK: ldgr %f0, [[REGISTER]]
21 %shift = lshr i64 %big, 1
22 %a = trunc i64 %shift to i32
23 %res = bitcast i32 %a to float
24 ret float %res
25}
26
27; Another example of the same thing.
28define float @f3(i64 %big) {
29; CHECK: f3:
30; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 2
31; CHECK: ldgr %f0, [[REGISTER]]
32 %shift = ashr i64 %big, 30
33 %a = trunc i64 %shift to i32
34 %res = bitcast i32 %a to float
35 ret float %res
36}
37
38; Like f1, but the value to transfer is already in the high 32 bits.
39define float @f4(i64 %big) {
40; CHECK: f4:
41; CHECK-NOT: %r2
42; CHECK: nilf %r2, 0
43; CHECK-NOT: %r2
44; CHECK: ldgr %f0, %r2
45 %shift = ashr i64 %big, 32
46 %a = trunc i64 %shift to i32
47 %res = bitcast i32 %a to float
48 ret float %res
49}
50
51; Test 64-bit moves from GPRs to FPRs.
52define double @f5(i64 %a) {
53; CHECK: f5:
54; CHECK: ldgr %f0, %r2
55 %res = bitcast i64 %a to double
56 ret double %res
57}
58
59; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type,
60; so this goes through memory.
61define void @f6(fp128 *%a, i128 *%b) {
62; CHECK: f6:
63; CHECK: lg
64; CHECK: lg
65; CHECK: stg
66; CHECK: stg
67 %val = load i128 *%b
68 %res = bitcast i128 %val to fp128
69 store fp128 %res, fp128 *%a
70 ret void
71}
72
73; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
74; be moved into the low 32 bits of the GPR.
75define i32 @f7(float %a) {
76; CHECK: f7:
77; CHECK: lgdr [[REGISTER:%r[0-5]]], %f0
78; CHECK: srlg %r2, [[REGISTER]], 32
79 %res = bitcast float %a to i32
80 ret i32 %res
81}
82
83; Test 64-bit moves from FPRs to GPRs.
84define i64 @f8(double %a) {
85; CHECK: f8:
86; CHECK: lgdr %r2, %f0
87 %res = bitcast double %a to i64
88 ret i64 %res
89}
90
91; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
92define void @f9(fp128 *%a, i128 *%b) {
93; CHECK: f9:
94; CHECK: ld
95; CHECK: ld
96; CHECK: std
97; CHECK: std
98 %val = load fp128 *%a
99 %res = bitcast fp128 %val to i128
100 store i128 %res, i128 *%b
101 ret void
102}
103