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gerrit-public.fairphone.software / toolchain / llvm-project / 871d3247999c4c8495e3d39831b88f37d33072b4 / . / llvm / test / CodeGen / ARM / fast-isel-pic.ll
blob: 75b82e8b0d64d140aac19bdcdf5326c610c4e3be [file] [log] [blame]
Mehdi Amini945a6602015-02-27 18:32:11 +0000[diff] [blame]1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
Mehdi Amini945a6602015-02-27 18:32:11 +0000[diff] [blame]2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
3; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
4; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
Jush Lue87e5592012-08-29 02:41:21 +0000[diff] [blame]5
6@g = global i32 0, align 4
7
8define i32 @LoadGV() {
9entry:
10; THUMB: LoadGV
11; THUMB: movw [[reg0:r[0-9]+]],
12; THUMB: movt [[reg0]],
13; THUMB: add [[reg0]], pc
Jush Lu47172a02012-09-27 05:21:41 +0000[diff] [blame]14; THUMB-ELF: LoadGV
Mihai Popa8a9da5b2013-07-22 15:49:36 +0000[diff] [blame]15; THUMB-ELF: ldr r[[reg0:[0-9]+]],
16; THUMB-ELF: ldr r[[reg1:[0-9]+]],
Andrew Tricke2431c62013-05-25 03:08:10 +0000[diff] [blame]17; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]]
Jush Lue87e5592012-08-29 02:41:21 +0000[diff] [blame]18; ARM: LoadGV
19; ARM: ldr [[reg1:r[0-9]+]],
20; ARM: add [[reg1]], pc, [[reg1]]
21; ARMv7: LoadGV
22; ARMv7: movw [[reg2:r[0-9]+]],
23; ARMv7: movt [[reg2]],
24; ARMv7: add [[reg2]], pc, [[reg2]]
Jush Lu47172a02012-09-27 05:21:41 +0000[diff] [blame]25; ARMv7-ELF: LoadGV
26; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
Benjamin Kramer30920662013-08-16 12:52:08 +0000[diff] [blame]27; ARMv7-ELF: .LPC
28; ARMv7-ELF-NEXT: add r[[reg2]], pc
Jush Lu47172a02012-09-27 05:21:41 +0000[diff] [blame]29; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
JF Bastien18db1f22013-06-14 02:49:43 +0000[diff] [blame]30; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]31 %tmp = load i32, i32* @g
Jush Lue87e5592012-08-29 02:41:21 +0000[diff] [blame]32 ret i32 %tmp
33}
34
35@i = external global i32
36
37define i32 @LoadIndirectSymbol() {
38entry:
39; THUMB: LoadIndirectSymbol
40; THUMB: movw r[[reg3:[0-9]+]],
41; THUMB: movt r[[reg3]],
42; THUMB: add r[[reg3]], pc
43; THUMB: ldr r[[reg3]], [r[[reg3]]]
Jush Lu47172a02012-09-27 05:21:41 +0000[diff] [blame]44; THUMB-ELF: LoadIndirectSymbol
Mihai Popa8a9da5b2013-07-22 15:49:36 +0000[diff] [blame]45; THUMB-ELF: ldr r[[reg3:[0-9]+]],
46; THUMB-ELF: ldr r[[reg4:[0-9]+]],
Andrew Tricke2431c62013-05-25 03:08:10 +0000[diff] [blame]47; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
Jush Lue87e5592012-08-29 02:41:21 +0000[diff] [blame]48; ARM: LoadIndirectSymbol
49; ARM: ldr [[reg4:r[0-9]+]],
50; ARM: ldr [[reg4]], [pc, [[reg4]]]
51; ARMv7: LoadIndirectSymbol
52; ARMv7: movw r[[reg5:[0-9]+]],
53; ARMv7: movt r[[reg5]],
54; ARMv7: add r[[reg5]], pc, r[[reg5]]
55; ARMv7: ldr r[[reg5]], [r[[reg5]]]
Jush Lu47172a02012-09-27 05:21:41 +0000[diff] [blame]56; ARMv7-ELF: LoadIndirectSymbol
57; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
Benjamin Kramer30920662013-08-16 12:52:08 +0000[diff] [blame]58; ARMv7-ELF: .LPC
59; ARMv7-ELF-NEXT: add r[[reg5]], pc
Jush Lu47172a02012-09-27 05:21:41 +0000[diff] [blame]60; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
JF Bastien18db1f22013-06-14 02:49:43 +0000[diff] [blame]61; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]62 %tmp = load i32, i32* @i
Jush Lue87e5592012-08-29 02:41:21 +0000[diff] [blame]63 ret i32 %tmp
64}