Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 98432956087f564dd39fe8d76aa6bc5fc09e079b / . / llvm / lib / Target / WebAssembly / MCTargetDesc / WebAssemblyMCTargetDesc.h
blob: a111eb51c56dbeb944a8cc9aa5baac66aa6326e8 [file] [log] [blame]
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]1//==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000[diff] [blame]11/// This file provides WebAssembly-specific target descriptions.
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
16#define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
17
Zachary Turner264b5d92017-06-07 03:48:56 +0000[diff] [blame]18#include "llvm/BinaryFormat/Wasm.h"
Dan Gohmana11fb232016-01-12 03:09:16 +0000[diff] [blame]19#include "llvm/MC/MCInstrDesc.h"
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]20#include "llvm/Support/DataTypes.h"
Derek Schuff669300d2017-10-10 17:31:43 +0000[diff] [blame]21#include <memory>
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]22
23namespace llvm {
24
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]25class MCAsmBackend;
26class MCCodeEmitter;
27class MCContext;
28class MCInstrInfo;
Peter Collingbournedcd7d6c2018-05-21 19:20:29 +0000[diff] [blame]29class MCObjectTargetWriter;
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]30class MCSubtargetInfo;
Dan Gohman3acb1872016-10-24 23:27:49 +0000[diff] [blame]31class MVT;
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]32class Target;
33class Triple;
Dan Gohman53828fd2015-11-23 16:50:18 +0000[diff] [blame]34class raw_pwrite_stream;
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]35
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]36Target &getTheWebAssemblyTarget32();
37Target &getTheWebAssemblyTarget64();
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]38
Sam Clegg9d24fb72017-06-16 23:59:10 +0000[diff] [blame]39MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
Dan Gohman53828fd2015-11-23 16:50:18 +0000[diff] [blame]40
Dan Gohmancceedf72016-01-08 00:43:54 +0000[diff] [blame]41MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]42
Peter Collingbournedcd7d6c2018-05-21 19:20:29 +0000[diff] [blame]43std::unique_ptr<MCObjectTargetWriter>
Peter Collingbournedcd7d6c2018-05-21 19:20:29 +0000[diff] [blame]44createWebAssemblyWasmObjectWriter(bool Is64Bit);
Dan Gohman18eafb62017-02-22 01:23:18 +0000[diff] [blame]45
Dan Gohmana11fb232016-01-12 03:09:16 +0000[diff] [blame]46namespace WebAssembly {
47enum OperandType {
48 /// Basic block label in a branch construct.
49 OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
Dan Gohman4fc4e422016-10-24 19:49:43 +0000[diff] [blame]50 /// Local index.
51 OPERAND_LOCAL,
Dan Gohmanb89f2d32017-02-02 19:29:44 +0000[diff] [blame]52 /// Global index.
53 OPERAND_GLOBAL,
Dan Gohman5a68ec72016-10-05 21:24:08 +0000[diff] [blame]54 /// 32-bit integer immediates.
55 OPERAND_I32IMM,
56 /// 64-bit integer immediates.
57 OPERAND_I64IMM,
Dan Gohmanaa742912016-02-16 15:14:23 +0000[diff] [blame]58 /// 32-bit floating-point immediates.
Dan Gohman4b8e8be2016-10-03 21:31:31 +0000[diff] [blame]59 OPERAND_F32IMM,
Dan Gohmanaa742912016-02-16 15:14:23 +0000[diff] [blame]60 /// 64-bit floating-point immediates.
Dan Gohman4b8e8be2016-10-03 21:31:31 +0000[diff] [blame]61 OPERAND_F64IMM,
Thomas Lively22442922018-08-21 21:03:18 +0000[diff] [blame]62 /// 8-bit vector lane immediate
63 OPERAND_VEC_I8IMM,
64 /// 16-bit vector lane immediate
65 OPERAND_VEC_I16IMM,
66 /// 32-bit vector lane immediate
67 OPERAND_VEC_I32IMM,
68 /// 64-bit vector lane immediate
69 OPERAND_VEC_I64IMM,
Dan Gohman00d734d2016-12-23 03:23:52 +0000[diff] [blame]70 /// 32-bit unsigned function indices.
71 OPERAND_FUNCTION32,
72 /// 32-bit unsigned memory offsets.
73 OPERAND_OFFSET32,
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]74 /// p2align immediate for load and store address alignment.
Dan Gohman2726b882016-10-06 22:29:32 +0000[diff] [blame]75 OPERAND_P2ALIGN,
76 /// signature immediate for block/loop.
Dan Gohmand934cb82017-02-24 23:18:00 +0000[diff] [blame]77 OPERAND_SIGNATURE,
78 /// type signature immediate for call_indirect.
79 OPERAND_TYPEINDEX,
Heejin Ahnda419bd2018-11-14 02:46:21 +0000[diff] [blame]80 /// Event index.
81 OPERAND_EVENT,
Dan Gohmana11fb232016-01-12 03:09:16 +0000[diff] [blame]82};
83} // end namespace WebAssembly
84
85namespace WebAssemblyII {
Nicholas Wilsone408a892018-08-03 14:33:37 +0000[diff] [blame]86
87/// Target Operand Flag enum.
88enum TOF {
89 MO_NO_FLAG = 0,
90
91 // Flags to indicate the type of the symbol being referenced
92 MO_SYMBOL_FUNCTION = 0x1,
Heejin Ahnf208f632018-09-05 01:27:38 +0000[diff] [blame]93 MO_SYMBOL_GLOBAL = 0x2,
Heejin Ahnda419bd2018-11-14 02:46:21 +0000[diff] [blame]94 MO_SYMBOL_EVENT = 0x4,
95 MO_SYMBOL_MASK = 0x7,
Nicholas Wilsone408a892018-08-03 14:33:37 +0000[diff] [blame]96};
Dan Gohmana11fb232016-01-12 03:09:16 +0000[diff] [blame]97} // end namespace WebAssemblyII
98
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]99} // end namespace llvm
100
101// Defines symbolic names for WebAssembly registers. This defines a mapping from
102// register name to register number.
103//
JF Bastien5ca0bac2015-07-10 18:23:10 +0000[diff] [blame]104#define GET_REGINFO_ENUM
105#include "WebAssemblyGenRegisterInfo.inc"
106
JF Bastienb9073fb2015-07-22 21:28:15 +0000[diff] [blame]107// Defines symbolic names for the WebAssembly instructions.
108//
109#define GET_INSTRINFO_ENUM
110#include "WebAssemblyGenInstrInfo.inc"
111
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]112#define GET_SUBTARGETINFO_ENUM
113#include "WebAssemblyGenSubtargetInfo.inc"
114
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]115namespace llvm {
116namespace WebAssembly {
117
118/// Return the default p2align value for a load or store with the given opcode.
119inline unsigned GetDefaultP2Align(unsigned Opcode) {
120 switch (Opcode) {
121 case WebAssembly::LOAD8_S_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]122 case WebAssembly::LOAD8_S_I32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]123 case WebAssembly::LOAD8_U_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]124 case WebAssembly::LOAD8_U_I32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]125 case WebAssembly::LOAD8_S_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]126 case WebAssembly::LOAD8_S_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]127 case WebAssembly::LOAD8_U_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]128 case WebAssembly::LOAD8_U_I64_S:
Derek Schuff885dc592017-10-05 21:18:42 +0000[diff] [blame]129 case WebAssembly::ATOMIC_LOAD8_U_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]130 case WebAssembly::ATOMIC_LOAD8_U_I32_S:
Derek Schuff885dc592017-10-05 21:18:42 +0000[diff] [blame]131 case WebAssembly::ATOMIC_LOAD8_U_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]132 case WebAssembly::ATOMIC_LOAD8_U_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]133 case WebAssembly::STORE8_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]134 case WebAssembly::STORE8_I32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]135 case WebAssembly::STORE8_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]136 case WebAssembly::STORE8_I64_S:
Heejin Ahn402b4902018-07-02 21:22:59 +0000[diff] [blame]137 case WebAssembly::ATOMIC_STORE8_I32:
Heejin Ahn80d9f172018-07-05 21:27:09 +0000[diff] [blame]138 case WebAssembly::ATOMIC_STORE8_I32_S:
Heejin Ahn402b4902018-07-02 21:22:59 +0000[diff] [blame]139 case WebAssembly::ATOMIC_STORE8_I64:
Heejin Ahn80d9f172018-07-05 21:27:09 +0000[diff] [blame]140 case WebAssembly::ATOMIC_STORE8_I64_S:
Heejin Ahnfed73822018-07-09 22:30:51 +0000[diff] [blame]141 case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
142 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
143 case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
144 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
145 case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
146 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
147 case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
148 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
149 case WebAssembly::ATOMIC_RMW8_U_AND_I32:
150 case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
151 case WebAssembly::ATOMIC_RMW8_U_AND_I64:
152 case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
153 case WebAssembly::ATOMIC_RMW8_U_OR_I32:
154 case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
155 case WebAssembly::ATOMIC_RMW8_U_OR_I64:
156 case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
157 case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
158 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
159 case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
160 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
161 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
162 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
163 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
164 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
Heejin Ahnb3724b72018-08-01 19:40:28 +0000[diff] [blame]165 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
166 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
167 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
168 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]169 return 0;
170 case WebAssembly::LOAD16_S_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]171 case WebAssembly::LOAD16_S_I32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]172 case WebAssembly::LOAD16_U_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]173 case WebAssembly::LOAD16_U_I32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]174 case WebAssembly::LOAD16_S_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]175 case WebAssembly::LOAD16_S_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]176 case WebAssembly::LOAD16_U_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]177 case WebAssembly::LOAD16_U_I64_S:
Derek Schuff885dc592017-10-05 21:18:42 +0000[diff] [blame]178 case WebAssembly::ATOMIC_LOAD16_U_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]179 case WebAssembly::ATOMIC_LOAD16_U_I32_S:
Derek Schuff885dc592017-10-05 21:18:42 +0000[diff] [blame]180 case WebAssembly::ATOMIC_LOAD16_U_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]181 case WebAssembly::ATOMIC_LOAD16_U_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]182 case WebAssembly::STORE16_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]183 case WebAssembly::STORE16_I32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]184 case WebAssembly::STORE16_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]185 case WebAssembly::STORE16_I64_S:
Heejin Ahn402b4902018-07-02 21:22:59 +0000[diff] [blame]186 case WebAssembly::ATOMIC_STORE16_I32:
Heejin Ahn80d9f172018-07-05 21:27:09 +0000[diff] [blame]187 case WebAssembly::ATOMIC_STORE16_I32_S:
Heejin Ahn402b4902018-07-02 21:22:59 +0000[diff] [blame]188 case WebAssembly::ATOMIC_STORE16_I64:
Heejin Ahn80d9f172018-07-05 21:27:09 +0000[diff] [blame]189 case WebAssembly::ATOMIC_STORE16_I64_S:
Heejin Ahnfed73822018-07-09 22:30:51 +0000[diff] [blame]190 case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
191 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
192 case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
193 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
194 case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
195 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
196 case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
197 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
198 case WebAssembly::ATOMIC_RMW16_U_AND_I32:
199 case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
200 case WebAssembly::ATOMIC_RMW16_U_AND_I64:
201 case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
202 case WebAssembly::ATOMIC_RMW16_U_OR_I32:
203 case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
204 case WebAssembly::ATOMIC_RMW16_U_OR_I64:
205 case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
206 case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
207 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
208 case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
209 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
210 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
211 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
212 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
213 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
Heejin Ahnb3724b72018-08-01 19:40:28 +0000[diff] [blame]214 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
215 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
216 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
217 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]218 return 1;
219 case WebAssembly::LOAD_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]220 case WebAssembly::LOAD_I32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]221 case WebAssembly::LOAD_F32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]222 case WebAssembly::LOAD_F32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]223 case WebAssembly::STORE_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]224 case WebAssembly::STORE_I32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]225 case WebAssembly::STORE_F32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]226 case WebAssembly::STORE_F32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]227 case WebAssembly::LOAD32_S_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]228 case WebAssembly::LOAD32_S_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]229 case WebAssembly::LOAD32_U_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]230 case WebAssembly::LOAD32_U_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]231 case WebAssembly::STORE32_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]232 case WebAssembly::STORE32_I64_S:
Derek Schuff18ba1922017-08-30 18:07:45 +0000[diff] [blame]233 case WebAssembly::ATOMIC_LOAD_I32:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]234 case WebAssembly::ATOMIC_LOAD_I32_S:
Derek Schuff885dc592017-10-05 21:18:42 +0000[diff] [blame]235 case WebAssembly::ATOMIC_LOAD32_U_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]236 case WebAssembly::ATOMIC_LOAD32_U_I64_S:
Heejin Ahn402b4902018-07-02 21:22:59 +0000[diff] [blame]237 case WebAssembly::ATOMIC_STORE_I32:
Heejin Ahn80d9f172018-07-05 21:27:09 +0000[diff] [blame]238 case WebAssembly::ATOMIC_STORE_I32_S:
Heejin Ahn402b4902018-07-02 21:22:59 +0000[diff] [blame]239 case WebAssembly::ATOMIC_STORE32_I64:
Heejin Ahn80d9f172018-07-05 21:27:09 +0000[diff] [blame]240 case WebAssembly::ATOMIC_STORE32_I64_S:
Heejin Ahnfed73822018-07-09 22:30:51 +0000[diff] [blame]241 case WebAssembly::ATOMIC_RMW_ADD_I32:
242 case WebAssembly::ATOMIC_RMW_ADD_I32_S:
243 case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
244 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
245 case WebAssembly::ATOMIC_RMW_SUB_I32:
246 case WebAssembly::ATOMIC_RMW_SUB_I32_S:
247 case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
248 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
249 case WebAssembly::ATOMIC_RMW_AND_I32:
250 case WebAssembly::ATOMIC_RMW_AND_I32_S:
251 case WebAssembly::ATOMIC_RMW32_U_AND_I64:
252 case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
253 case WebAssembly::ATOMIC_RMW_OR_I32:
254 case WebAssembly::ATOMIC_RMW_OR_I32_S:
255 case WebAssembly::ATOMIC_RMW32_U_OR_I64:
256 case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
257 case WebAssembly::ATOMIC_RMW_XOR_I32:
258 case WebAssembly::ATOMIC_RMW_XOR_I32_S:
259 case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
260 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
261 case WebAssembly::ATOMIC_RMW_XCHG_I32:
262 case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
263 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
264 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
Heejin Ahnb3724b72018-08-01 19:40:28 +0000[diff] [blame]265 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
266 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
267 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
268 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
Heejin Ahn4128cb02018-08-02 21:44:24 +0000[diff] [blame]269 case WebAssembly::ATOMIC_NOTIFY:
270 case WebAssembly::ATOMIC_NOTIFY_S:
271 case WebAssembly::ATOMIC_WAIT_I32:
272 case WebAssembly::ATOMIC_WAIT_I32_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]273 return 2;
274 case WebAssembly::LOAD_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]275 case WebAssembly::LOAD_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]276 case WebAssembly::LOAD_F64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]277 case WebAssembly::LOAD_F64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]278 case WebAssembly::STORE_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]279 case WebAssembly::STORE_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]280 case WebAssembly::STORE_F64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]281 case WebAssembly::STORE_F64_S:
Derek Schuff885dc592017-10-05 21:18:42 +0000[diff] [blame]282 case WebAssembly::ATOMIC_LOAD_I64:
Wouter van Oortmerssen48dac312018-06-18 21:22:44 +0000[diff] [blame]283 case WebAssembly::ATOMIC_LOAD_I64_S:
Heejin Ahn402b4902018-07-02 21:22:59 +0000[diff] [blame]284 case WebAssembly::ATOMIC_STORE_I64:
Heejin Ahn80d9f172018-07-05 21:27:09 +0000[diff] [blame]285 case WebAssembly::ATOMIC_STORE_I64_S:
Heejin Ahnfed73822018-07-09 22:30:51 +0000[diff] [blame]286 case WebAssembly::ATOMIC_RMW_ADD_I64:
287 case WebAssembly::ATOMIC_RMW_ADD_I64_S:
288 case WebAssembly::ATOMIC_RMW_SUB_I64:
289 case WebAssembly::ATOMIC_RMW_SUB_I64_S:
290 case WebAssembly::ATOMIC_RMW_AND_I64:
291 case WebAssembly::ATOMIC_RMW_AND_I64_S:
292 case WebAssembly::ATOMIC_RMW_OR_I64:
293 case WebAssembly::ATOMIC_RMW_OR_I64_S:
294 case WebAssembly::ATOMIC_RMW_XOR_I64:
295 case WebAssembly::ATOMIC_RMW_XOR_I64_S:
296 case WebAssembly::ATOMIC_RMW_XCHG_I64:
297 case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
Heejin Ahnb3724b72018-08-01 19:40:28 +0000[diff] [blame]298 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
299 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
Heejin Ahn4128cb02018-08-02 21:44:24 +0000[diff] [blame]300 case WebAssembly::ATOMIC_WAIT_I64:
301 case WebAssembly::ATOMIC_WAIT_I64_S:
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]302 return 3;
Thomas Livelyd183d8c2018-08-30 21:36:48 +0000[diff] [blame]303 case WebAssembly::LOAD_v16i8:
304 case WebAssembly::LOAD_v16i8_S:
305 case WebAssembly::LOAD_v8i16:
306 case WebAssembly::LOAD_v8i16_S:
307 case WebAssembly::LOAD_v4i32:
308 case WebAssembly::LOAD_v4i32_S:
309 case WebAssembly::LOAD_v2i64:
310 case WebAssembly::LOAD_v2i64_S:
311 case WebAssembly::LOAD_v4f32:
312 case WebAssembly::LOAD_v4f32_S:
313 case WebAssembly::LOAD_v2f64:
314 case WebAssembly::LOAD_v2f64_S:
315 case WebAssembly::STORE_v16i8:
316 case WebAssembly::STORE_v16i8_S:
317 case WebAssembly::STORE_v8i16:
318 case WebAssembly::STORE_v8i16_S:
319 case WebAssembly::STORE_v4i32:
320 case WebAssembly::STORE_v4i32_S:
321 case WebAssembly::STORE_v2i64:
322 case WebAssembly::STORE_v2i64_S:
323 case WebAssembly::STORE_v4f32:
324 case WebAssembly::STORE_v4f32_S:
325 case WebAssembly::STORE_v2f64:
326 case WebAssembly::STORE_v2f64_S:
327 return 4;
Derek Schuffc64d7652016-08-01 22:25:02 +0000[diff] [blame]328 default:
329 llvm_unreachable("Only loads and stores have p2align values");
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]330 }
331}
332
Derek Schuffc97ba932016-01-30 21:43:08 +0000[diff] [blame]333/// The operand number of the load or store address in load/store instructions.
Dan Gohman48abaa92016-10-25 00:17:11 +0000[diff] [blame]334static const unsigned LoadAddressOperandNo = 3;
335static const unsigned StoreAddressOperandNo = 2;
Dan Gohman7f1bdb22016-10-06 22:08:28 +0000[diff] [blame]336
337/// The operand number of the load or store p2align in load/store instructions.
Dan Gohman48abaa92016-10-25 00:17:11 +0000[diff] [blame]338static const unsigned LoadP2AlignOperandNo = 1;
339static const unsigned StoreP2AlignOperandNo = 0;
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]340
Dan Gohman2726b882016-10-06 22:29:32 +0000[diff] [blame]341/// This is used to indicate block signatures.
Heejin Ahn0c69a3e2018-03-02 20:52:59 +0000[diff] [blame]342enum class ExprType : unsigned {
Derek Schuff2c783852018-08-06 23:16:50 +0000[diff] [blame]343 Void = 0x40,
344 I32 = 0x7F,
345 I64 = 0x7E,
346 F32 = 0x7D,
347 F64 = 0x7C,
348 V128 = 0x7B,
Wouter van Oortmerssenad72f682019-01-02 23:23:51 +0000[diff] [blame]349 ExceptRef = 0x68,
350 Invalid = 0x00
Dan Gohman4fc4e422016-10-24 19:49:43 +0000[diff] [blame]351};
352
Dan Gohman3acb1872016-10-24 23:27:49 +0000[diff] [blame]353/// Instruction opcodes emitted via means other than CodeGen.
354static const unsigned Nop = 0x01;
355static const unsigned End = 0x0b;
356
Derek Schuffe2688c42017-03-14 20:23:22 +0000[diff] [blame]357wasm::ValType toValType(const MVT &Ty);
Dan Gohman3acb1872016-10-24 23:27:49 +0000[diff] [blame]358
Dan Gohmanbb372242016-01-26 03:39:31 +0000[diff] [blame]359} // end namespace WebAssembly
360} // end namespace llvm
361
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]362#endif