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Chris Lattnera76eab42010-11-14 19:40:38 +00001//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an PPC MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
Chris Lattnera76eab42010-11-14 19:40:38 +000014#include "PPCInstPrinter.h"
Hal Finkelfeea6532013-03-26 20:08:20 +000015#include "MCTargetDesc/PPCMCTargetDesc.h"
Evan Cheng11424442011-07-26 00:24:13 +000016#include "MCTargetDesc/PPCPredicates.h"
Chris Lattner7a5c57e2010-11-14 20:02:39 +000017#include "llvm/MC/MCExpr.h"
Chris Lattnera76eab42010-11-14 19:40:38 +000018#include "llvm/MC/MCInst.h"
Craig Topperdab9e352012-04-02 07:01:04 +000019#include "llvm/MC/MCInstrInfo.h"
Hal Finkel7c8ae532014-07-25 17:47:22 +000020#include "llvm/MC/MCSymbol.h"
Hal Finkelc6a24392013-11-11 14:58:40 +000021#include "llvm/Support/CommandLine.h"
Chris Lattnera76eab42010-11-14 19:40:38 +000022#include "llvm/Support/raw_ostream.h"
Bill Schmidt8d86fe72013-08-30 15:18:11 +000023#include "llvm/Target/TargetOpcodes.h"
Chris Lattnera76eab42010-11-14 19:40:38 +000024using namespace llvm;
25
Chandler Carruth84e68b22014-04-22 02:41:26 +000026#define DEBUG_TYPE "asm-printer"
27
Hal Finkelc6a24392013-11-11 14:58:40 +000028// FIXME: Once the integrated assembler supports full register names, tie this
29// to the verbose-asm setting.
30static cl::opt<bool>
31FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
32 cl::desc("Use full register names when printing assembly"));
33
Chris Lattnera76eab42010-11-14 19:40:38 +000034#include "PPCGenAsmWriter.inc"
35
Rafael Espindolad6860522011-06-02 02:34:55 +000036void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
37 OS << getRegisterName(RegNo);
Rafael Espindola08600bc2011-05-30 20:20:15 +000038}
Chris Lattnera76eab42010-11-14 19:40:38 +000039
Owen Andersona0c3b972011-09-15 23:38:46 +000040void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
41 StringRef Annot) {
Chris Lattner219cc3d2010-11-14 21:39:51 +000042 // Check for slwi/srwi mnemonics.
43 if (MI->getOpcode() == PPC::RLWINM) {
44 unsigned char SH = MI->getOperand(2).getImm();
45 unsigned char MB = MI->getOperand(3).getImm();
46 unsigned char ME = MI->getOperand(4).getImm();
47 bool useSubstituteMnemonic = false;
48 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
49 O << "\tslwi "; useSubstituteMnemonic = true;
50 }
51 if (SH <= 31 && MB == (32-SH) && ME == 31) {
52 O << "\tsrwi "; useSubstituteMnemonic = true;
53 SH = 32-SH;
54 }
55 if (useSubstituteMnemonic) {
56 printOperand(MI, 0, O);
57 O << ", ";
58 printOperand(MI, 1, O);
59 O << ", " << (unsigned int)SH;
Owen Andersona0c3b972011-09-15 23:38:46 +000060
Owen Andersonbcc3fad2011-09-21 17:58:45 +000061 printAnnotation(O, Annot);
Chris Lattner219cc3d2010-11-14 21:39:51 +000062 return;
63 }
64 }
65
66 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
67 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
68 O << "\tmr ";
69 printOperand(MI, 0, O);
70 O << ", ";
71 printOperand(MI, 1, O);
Owen Andersonbcc3fad2011-09-21 17:58:45 +000072 printAnnotation(O, Annot);
Chris Lattner219cc3d2010-11-14 21:39:51 +000073 return;
74 }
75
76 if (MI->getOpcode() == PPC::RLDICR) {
77 unsigned char SH = MI->getOperand(2).getImm();
78 unsigned char ME = MI->getOperand(3).getImm();
79 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
80 if (63-SH == ME) {
81 O << "\tsldi ";
82 printOperand(MI, 0, O);
83 O << ", ";
84 printOperand(MI, 1, O);
85 O << ", " << (unsigned int)SH;
Owen Andersonbcc3fad2011-09-21 17:58:45 +000086 printAnnotation(O, Annot);
Chris Lattner219cc3d2010-11-14 21:39:51 +000087 return;
88 }
89 }
90
Bill Schmidt8d86fe72013-08-30 15:18:11 +000091 // For fast-isel, a COPY_TO_REGCLASS may survive this long. This is
92 // used when converting a 32-bit float to a 64-bit float as part of
93 // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
94 // as otherwise we have problems with incorrect register classes
95 // in machine instruction verification. For now, just avoid trying
96 // to print it as such an instruction has no effect (a 32-bit float
97 // in a register is already in 64-bit form, just with lower
98 // precision). FIXME: Is there a better solution?
99 if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
100 return;
101
Chris Lattnera76eab42010-11-14 19:40:38 +0000102 printInstruction(MI, O);
Owen Andersonbcc3fad2011-09-21 17:58:45 +0000103 printAnnotation(O, Annot);
Chris Lattnera76eab42010-11-14 19:40:38 +0000104}
105
Chris Lattnerf2cb69c2010-11-14 21:51:37 +0000106
107void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
108 raw_ostream &O,
109 const char *Modifier) {
Chris Lattnerf2cb69c2010-11-14 21:51:37 +0000110 unsigned Code = MI->getOperand(OpNo).getImm();
Hal Finkel460e94d2012-06-22 23:10:08 +0000111
Chris Lattnerf2cb69c2010-11-14 21:51:37 +0000112 if (StringRef(Modifier) == "cc") {
113 switch ((PPC::Predicate)Code) {
Ulrich Weigand86247b62013-06-24 16:52:04 +0000114 case PPC::PRED_LT_MINUS:
115 case PPC::PRED_LT_PLUS:
116 case PPC::PRED_LT:
117 O << "lt";
118 return;
119 case PPC::PRED_LE_MINUS:
120 case PPC::PRED_LE_PLUS:
121 case PPC::PRED_LE:
122 O << "le";
123 return;
124 case PPC::PRED_EQ_MINUS:
125 case PPC::PRED_EQ_PLUS:
126 case PPC::PRED_EQ:
127 O << "eq";
128 return;
129 case PPC::PRED_GE_MINUS:
130 case PPC::PRED_GE_PLUS:
131 case PPC::PRED_GE:
132 O << "ge";
133 return;
134 case PPC::PRED_GT_MINUS:
135 case PPC::PRED_GT_PLUS:
136 case PPC::PRED_GT:
137 O << "gt";
138 return;
139 case PPC::PRED_NE_MINUS:
140 case PPC::PRED_NE_PLUS:
141 case PPC::PRED_NE:
142 O << "ne";
143 return;
144 case PPC::PRED_UN_MINUS:
145 case PPC::PRED_UN_PLUS:
146 case PPC::PRED_UN:
147 O << "un";
148 return;
149 case PPC::PRED_NU_MINUS:
150 case PPC::PRED_NU_PLUS:
151 case PPC::PRED_NU:
152 O << "nu";
153 return;
Hal Finkel940ab932014-02-28 00:27:01 +0000154 case PPC::PRED_BIT_SET:
155 case PPC::PRED_BIT_UNSET:
156 llvm_unreachable("Invalid use of bit predicate code");
Ulrich Weigand86247b62013-06-24 16:52:04 +0000157 }
Benjamin Kramer3912d782013-06-24 17:03:25 +0000158 llvm_unreachable("Invalid predicate code");
Ulrich Weigand86247b62013-06-24 16:52:04 +0000159 }
160
161 if (StringRef(Modifier) == "pm") {
162 switch ((PPC::Predicate)Code) {
163 case PPC::PRED_LT:
164 case PPC::PRED_LE:
165 case PPC::PRED_EQ:
166 case PPC::PRED_GE:
167 case PPC::PRED_GT:
168 case PPC::PRED_NE:
169 case PPC::PRED_UN:
170 case PPC::PRED_NU:
171 return;
172 case PPC::PRED_LT_MINUS:
173 case PPC::PRED_LE_MINUS:
174 case PPC::PRED_EQ_MINUS:
175 case PPC::PRED_GE_MINUS:
176 case PPC::PRED_GT_MINUS:
177 case PPC::PRED_NE_MINUS:
178 case PPC::PRED_UN_MINUS:
179 case PPC::PRED_NU_MINUS:
180 O << "-";
181 return;
182 case PPC::PRED_LT_PLUS:
183 case PPC::PRED_LE_PLUS:
184 case PPC::PRED_EQ_PLUS:
185 case PPC::PRED_GE_PLUS:
186 case PPC::PRED_GT_PLUS:
187 case PPC::PRED_NE_PLUS:
188 case PPC::PRED_UN_PLUS:
189 case PPC::PRED_NU_PLUS:
190 O << "+";
191 return;
Hal Finkel940ab932014-02-28 00:27:01 +0000192 case PPC::PRED_BIT_SET:
193 case PPC::PRED_BIT_UNSET:
194 llvm_unreachable("Invalid use of bit predicate code");
Chris Lattnerf2cb69c2010-11-14 21:51:37 +0000195 }
Benjamin Kramer3912d782013-06-24 17:03:25 +0000196 llvm_unreachable("Invalid predicate code");
Chris Lattnerf2cb69c2010-11-14 21:51:37 +0000197 }
198
199 assert(StringRef(Modifier) == "reg" &&
Ulrich Weigand86247b62013-06-24 16:52:04 +0000200 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
Chris Lattnerf2cb69c2010-11-14 21:51:37 +0000201 printOperand(MI, OpNo+1, O);
202}
203
Hal Finkel27774d92014-03-13 07:58:58 +0000204void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
205 raw_ostream &O) {
206 unsigned int Value = MI->getOperand(OpNo).getImm();
207 assert(Value <= 3 && "Invalid u2imm argument!");
208 O << (unsigned int)Value;
209}
210
Joerg Sonnenberger9e9623c2014-07-29 22:21:57 +0000211void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
212 raw_ostream &O) {
213 unsigned int Value = MI->getOperand(OpNo).getImm();
214 assert(Value <= 15 && "Invalid u4imm argument!");
215 O << (unsigned int)Value;
216}
217
Chris Lattner94881432010-11-14 20:11:21 +0000218void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
219 raw_ostream &O) {
Adhemerval Zanellafe3f7932012-10-08 18:59:53 +0000220 int Value = MI->getOperand(OpNo).getImm();
Richard Smith228e6d42012-08-24 23:29:28 +0000221 Value = SignExtend32<5>(Value);
Chris Lattner94881432010-11-14 20:11:21 +0000222 O << (int)Value;
223}
224
225void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
226 raw_ostream &O) {
Adhemerval Zanellafe3f7932012-10-08 18:59:53 +0000227 unsigned int Value = MI->getOperand(OpNo).getImm();
Chris Lattner94881432010-11-14 20:11:21 +0000228 assert(Value <= 31 && "Invalid u5imm argument!");
229 O << (unsigned int)Value;
230}
231
232void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
233 raw_ostream &O) {
Adhemerval Zanellafe3f7932012-10-08 18:59:53 +0000234 unsigned int Value = MI->getOperand(OpNo).getImm();
Chris Lattner94881432010-11-14 20:11:21 +0000235 assert(Value <= 63 && "Invalid u6imm argument!");
236 O << (unsigned int)Value;
237}
238
239void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
240 raw_ostream &O) {
Ulrich Weigand41789de2013-05-23 22:26:41 +0000241 if (MI->getOperand(OpNo).isImm())
242 O << (short)MI->getOperand(OpNo).getImm();
243 else
244 printOperand(MI, OpNo, O);
Chris Lattner94881432010-11-14 20:11:21 +0000245}
246
247void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
248 raw_ostream &O) {
Ulrich Weigandfd3ad692013-06-26 13:49:15 +0000249 if (MI->getOperand(OpNo).isImm())
250 O << (unsigned short)MI->getOperand(OpNo).getImm();
251 else
252 printOperand(MI, OpNo, O);
Chris Lattner94881432010-11-14 20:11:21 +0000253}
254
Chris Lattner3dc9bb22010-11-14 21:20:46 +0000255void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
256 raw_ostream &O) {
257 if (!MI->getOperand(OpNo).isImm())
258 return printOperand(MI, OpNo, O);
259
260 // Branches can take an immediate operand. This is used by the branch
Ulrich Weigandb9d5d072013-05-03 19:53:04 +0000261 // selection pass to print .+8, an eight byte displacement from the PC.
262 O << ".+";
Ulrich Weigandb6a30d12013-06-24 11:03:33 +0000263 printAbsBranchOperand(MI, OpNo, O);
Chris Lattner3dc9bb22010-11-14 21:20:46 +0000264}
265
Ulrich Weigandb6a30d12013-06-24 11:03:33 +0000266void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
267 raw_ostream &O) {
268 if (!MI->getOperand(OpNo).isImm())
269 return printOperand(MI, OpNo, O);
270
Alexey Samsonov9ca48702014-09-02 17:38:34 +0000271 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
Chris Lattnerf2cb69c2010-11-14 21:51:37 +0000272}
Chris Lattner3dc9bb22010-11-14 21:20:46 +0000273
274
Chris Lattner0dcd8002010-11-14 20:22:56 +0000275void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
276 raw_ostream &O) {
277 unsigned CCReg = MI->getOperand(OpNo).getReg();
278 unsigned RegNo;
279 switch (CCReg) {
Craig Toppere55c5562012-02-07 02:50:20 +0000280 default: llvm_unreachable("Unknown CR register");
Chris Lattner0dcd8002010-11-14 20:22:56 +0000281 case PPC::CR0: RegNo = 0; break;
282 case PPC::CR1: RegNo = 1; break;
283 case PPC::CR2: RegNo = 2; break;
284 case PPC::CR3: RegNo = 3; break;
285 case PPC::CR4: RegNo = 4; break;
286 case PPC::CR5: RegNo = 5; break;
287 case PPC::CR6: RegNo = 6; break;
288 case PPC::CR7: RegNo = 7; break;
289 }
290 O << (0x80 >> RegNo);
291}
292
293void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
294 raw_ostream &O) {
Ulrich Weigand41789de2013-05-23 22:26:41 +0000295 printS16ImmOperand(MI, OpNo, O);
Chris Lattner0dcd8002010-11-14 20:22:56 +0000296 O << '(';
Chris Lattnerfd56ee22010-11-15 03:51:13 +0000297 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
Chris Lattner0dcd8002010-11-14 20:22:56 +0000298 O << "0";
299 else
300 printOperand(MI, OpNo+1, O);
301 O << ')';
302}
303
Chris Lattner0dcd8002010-11-14 20:22:56 +0000304void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
305 raw_ostream &O) {
306 // When used as the base register, r0 reads constant zero rather than
307 // the value contained in the register. For this reason, the darwin
308 // assembler requires that we print r0 as 0 (no r) when used as the base.
309 if (MI->getOperand(OpNo).getReg() == PPC::R0)
310 O << "0";
311 else
312 printOperand(MI, OpNo, O);
313 O << ", ";
314 printOperand(MI, OpNo+1, O);
315}
316
Ulrich Weigand5143bab2013-07-02 21:31:04 +0000317void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
318 raw_ostream &O) {
Hal Finkel7c8ae532014-07-25 17:47:22 +0000319 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
320 // come at the _end_ of the expression.
321 const MCOperand &Op = MI->getOperand(OpNo);
322 const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
323 O << refExp.getSymbol().getName();
Ulrich Weigand5143bab2013-07-02 21:31:04 +0000324 O << '(';
325 printOperand(MI, OpNo+1, O);
326 O << ')';
Hal Finkel7c8ae532014-07-25 17:47:22 +0000327 if (refExp.getKind() != MCSymbolRefExpr::VK_None)
328 O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
Ulrich Weigand5143bab2013-07-02 21:31:04 +0000329}
Chris Lattner0dcd8002010-11-14 20:22:56 +0000330
Chris Lattner94881432010-11-14 20:11:21 +0000331
Chris Lattner7a5c57e2010-11-14 20:02:39 +0000332/// stripRegisterPrefix - This method strips the character prefix from a
333/// register name so that only the number is left. Used by for linux asm.
Benjamin Krameraef5bd02010-11-25 16:42:51 +0000334static const char *stripRegisterPrefix(const char *RegName) {
Hal Finkelc6a24392013-11-11 14:58:40 +0000335 if (FullRegNames)
336 return RegName;
337
Chris Lattner7a5c57e2010-11-14 20:02:39 +0000338 switch (RegName[0]) {
339 case 'r':
340 case 'f':
Hal Finkel27774d92014-03-13 07:58:58 +0000341 case 'v':
342 if (RegName[1] == 's')
343 return RegName + 2;
344 return RegName + 1;
Chris Lattner7a5c57e2010-11-14 20:02:39 +0000345 case 'c': if (RegName[1] == 'r') return RegName + 2;
346 }
347
348 return RegName;
349}
350
351void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
352 raw_ostream &O) {
353 const MCOperand &Op = MI->getOperand(OpNo);
354 if (Op.isReg()) {
355 const char *RegName = getRegisterName(Op.getReg());
356 // The linux and AIX assembler does not take register prefixes.
357 if (!isDarwinSyntax())
358 RegName = stripRegisterPrefix(RegName);
359
360 O << RegName;
361 return;
362 }
363
364 if (Op.isImm()) {
365 O << Op.getImm();
366 return;
367 }
368
369 assert(Op.isExpr() && "unknown operand kind in printOperand");
370 O << *Op.getExpr();
371}
Chris Lattnercfb62872010-11-14 21:54:34 +0000372