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gerrit-public.fairphone.software / toolchain / llvm-project / 9d010fffe139750b71427e5d7921c8c7fcd68e1e / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: cc4445fc4c021956ff5467a036df606b9fc3dd71 [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]17#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]22#include "llvm/CodeGen/MachineJumpTableInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]23#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]24#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/DerivedTypes.h"
26#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]27#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]28#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]29#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]30#include "llvm/MC/MCExpr.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Target/TargetLoweringObjectFile.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetRegisterInfo.h"
37#include <cctype>
38using namespace llvm;
39
40/// InitLibcallNames - Set default libcall names.
41///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]42static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]43 Names[RTLIB::SHL_I16] = "__ashlhi3";
44 Names[RTLIB::SHL_I32] = "__ashlsi3";
45 Names[RTLIB::SHL_I64] = "__ashldi3";
46 Names[RTLIB::SHL_I128] = "__ashlti3";
47 Names[RTLIB::SRL_I16] = "__lshrhi3";
48 Names[RTLIB::SRL_I32] = "__lshrsi3";
49 Names[RTLIB::SRL_I64] = "__lshrdi3";
50 Names[RTLIB::SRL_I128] = "__lshrti3";
51 Names[RTLIB::SRA_I16] = "__ashrhi3";
52 Names[RTLIB::SRA_I32] = "__ashrsi3";
53 Names[RTLIB::SRA_I64] = "__ashrdi3";
54 Names[RTLIB::SRA_I128] = "__ashrti3";
55 Names[RTLIB::MUL_I8] = "__mulqi3";
56 Names[RTLIB::MUL_I16] = "__mulhi3";
57 Names[RTLIB::MUL_I32] = "__mulsi3";
58 Names[RTLIB::MUL_I64] = "__muldi3";
59 Names[RTLIB::MUL_I128] = "__multi3";
60 Names[RTLIB::MULO_I32] = "__mulosi4";
61 Names[RTLIB::MULO_I64] = "__mulodi4";
62 Names[RTLIB::MULO_I128] = "__muloti4";
63 Names[RTLIB::SDIV_I8] = "__divqi3";
64 Names[RTLIB::SDIV_I16] = "__divhi3";
65 Names[RTLIB::SDIV_I32] = "__divsi3";
66 Names[RTLIB::SDIV_I64] = "__divdi3";
67 Names[RTLIB::SDIV_I128] = "__divti3";
68 Names[RTLIB::UDIV_I8] = "__udivqi3";
69 Names[RTLIB::UDIV_I16] = "__udivhi3";
70 Names[RTLIB::UDIV_I32] = "__udivsi3";
71 Names[RTLIB::UDIV_I64] = "__udivdi3";
72 Names[RTLIB::UDIV_I128] = "__udivti3";
73 Names[RTLIB::SREM_I8] = "__modqi3";
74 Names[RTLIB::SREM_I16] = "__modhi3";
75 Names[RTLIB::SREM_I32] = "__modsi3";
76 Names[RTLIB::SREM_I64] = "__moddi3";
77 Names[RTLIB::SREM_I128] = "__modti3";
78 Names[RTLIB::UREM_I8] = "__umodqi3";
79 Names[RTLIB::UREM_I16] = "__umodhi3";
80 Names[RTLIB::UREM_I32] = "__umodsi3";
81 Names[RTLIB::UREM_I64] = "__umoddi3";
82 Names[RTLIB::UREM_I128] = "__umodti3";
83
84 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]85 Names[RTLIB::SDIVREM_I8] = nullptr;
86 Names[RTLIB::SDIVREM_I16] = nullptr;
87 Names[RTLIB::SDIVREM_I32] = nullptr;
88 Names[RTLIB::SDIVREM_I64] = nullptr;
89 Names[RTLIB::SDIVREM_I128] = nullptr;
90 Names[RTLIB::UDIVREM_I8] = nullptr;
91 Names[RTLIB::UDIVREM_I16] = nullptr;
92 Names[RTLIB::UDIVREM_I32] = nullptr;
93 Names[RTLIB::UDIVREM_I64] = nullptr;
94 Names[RTLIB::UDIVREM_I128] = nullptr;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]95
96 Names[RTLIB::NEG_I32] = "__negsi2";
97 Names[RTLIB::NEG_I64] = "__negdi2";
98 Names[RTLIB::ADD_F32] = "__addsf3";
99 Names[RTLIB::ADD_F64] = "__adddf3";
100 Names[RTLIB::ADD_F80] = "__addxf3";
101 Names[RTLIB::ADD_F128] = "__addtf3";
102 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
103 Names[RTLIB::SUB_F32] = "__subsf3";
104 Names[RTLIB::SUB_F64] = "__subdf3";
105 Names[RTLIB::SUB_F80] = "__subxf3";
106 Names[RTLIB::SUB_F128] = "__subtf3";
107 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
108 Names[RTLIB::MUL_F32] = "__mulsf3";
109 Names[RTLIB::MUL_F64] = "__muldf3";
110 Names[RTLIB::MUL_F80] = "__mulxf3";
111 Names[RTLIB::MUL_F128] = "__multf3";
112 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
113 Names[RTLIB::DIV_F32] = "__divsf3";
114 Names[RTLIB::DIV_F64] = "__divdf3";
115 Names[RTLIB::DIV_F80] = "__divxf3";
116 Names[RTLIB::DIV_F128] = "__divtf3";
117 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
118 Names[RTLIB::REM_F32] = "fmodf";
119 Names[RTLIB::REM_F64] = "fmod";
120 Names[RTLIB::REM_F80] = "fmodl";
121 Names[RTLIB::REM_F128] = "fmodl";
122 Names[RTLIB::REM_PPCF128] = "fmodl";
123 Names[RTLIB::FMA_F32] = "fmaf";
124 Names[RTLIB::FMA_F64] = "fma";
125 Names[RTLIB::FMA_F80] = "fmal";
126 Names[RTLIB::FMA_F128] = "fmal";
127 Names[RTLIB::FMA_PPCF128] = "fmal";
128 Names[RTLIB::POWI_F32] = "__powisf2";
129 Names[RTLIB::POWI_F64] = "__powidf2";
130 Names[RTLIB::POWI_F80] = "__powixf2";
131 Names[RTLIB::POWI_F128] = "__powitf2";
132 Names[RTLIB::POWI_PPCF128] = "__powitf2";
133 Names[RTLIB::SQRT_F32] = "sqrtf";
134 Names[RTLIB::SQRT_F64] = "sqrt";
135 Names[RTLIB::SQRT_F80] = "sqrtl";
136 Names[RTLIB::SQRT_F128] = "sqrtl";
137 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
138 Names[RTLIB::LOG_F32] = "logf";
139 Names[RTLIB::LOG_F64] = "log";
140 Names[RTLIB::LOG_F80] = "logl";
141 Names[RTLIB::LOG_F128] = "logl";
142 Names[RTLIB::LOG_PPCF128] = "logl";
143 Names[RTLIB::LOG2_F32] = "log2f";
144 Names[RTLIB::LOG2_F64] = "log2";
145 Names[RTLIB::LOG2_F80] = "log2l";
146 Names[RTLIB::LOG2_F128] = "log2l";
147 Names[RTLIB::LOG2_PPCF128] = "log2l";
148 Names[RTLIB::LOG10_F32] = "log10f";
149 Names[RTLIB::LOG10_F64] = "log10";
150 Names[RTLIB::LOG10_F80] = "log10l";
151 Names[RTLIB::LOG10_F128] = "log10l";
152 Names[RTLIB::LOG10_PPCF128] = "log10l";
153 Names[RTLIB::EXP_F32] = "expf";
154 Names[RTLIB::EXP_F64] = "exp";
155 Names[RTLIB::EXP_F80] = "expl";
156 Names[RTLIB::EXP_F128] = "expl";
157 Names[RTLIB::EXP_PPCF128] = "expl";
158 Names[RTLIB::EXP2_F32] = "exp2f";
159 Names[RTLIB::EXP2_F64] = "exp2";
160 Names[RTLIB::EXP2_F80] = "exp2l";
161 Names[RTLIB::EXP2_F128] = "exp2l";
162 Names[RTLIB::EXP2_PPCF128] = "exp2l";
163 Names[RTLIB::SIN_F32] = "sinf";
164 Names[RTLIB::SIN_F64] = "sin";
165 Names[RTLIB::SIN_F80] = "sinl";
166 Names[RTLIB::SIN_F128] = "sinl";
167 Names[RTLIB::SIN_PPCF128] = "sinl";
168 Names[RTLIB::COS_F32] = "cosf";
169 Names[RTLIB::COS_F64] = "cos";
170 Names[RTLIB::COS_F80] = "cosl";
171 Names[RTLIB::COS_F128] = "cosl";
172 Names[RTLIB::COS_PPCF128] = "cosl";
173 Names[RTLIB::POW_F32] = "powf";
174 Names[RTLIB::POW_F64] = "pow";
175 Names[RTLIB::POW_F80] = "powl";
176 Names[RTLIB::POW_F128] = "powl";
177 Names[RTLIB::POW_PPCF128] = "powl";
178 Names[RTLIB::CEIL_F32] = "ceilf";
179 Names[RTLIB::CEIL_F64] = "ceil";
180 Names[RTLIB::CEIL_F80] = "ceill";
181 Names[RTLIB::CEIL_F128] = "ceill";
182 Names[RTLIB::CEIL_PPCF128] = "ceill";
183 Names[RTLIB::TRUNC_F32] = "truncf";
184 Names[RTLIB::TRUNC_F64] = "trunc";
185 Names[RTLIB::TRUNC_F80] = "truncl";
186 Names[RTLIB::TRUNC_F128] = "truncl";
187 Names[RTLIB::TRUNC_PPCF128] = "truncl";
188 Names[RTLIB::RINT_F32] = "rintf";
189 Names[RTLIB::RINT_F64] = "rint";
190 Names[RTLIB::RINT_F80] = "rintl";
191 Names[RTLIB::RINT_F128] = "rintl";
192 Names[RTLIB::RINT_PPCF128] = "rintl";
193 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
194 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
195 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
196 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
197 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]198 Names[RTLIB::ROUND_F32] = "roundf";
199 Names[RTLIB::ROUND_F64] = "round";
200 Names[RTLIB::ROUND_F80] = "roundl";
201 Names[RTLIB::ROUND_F128] = "roundl";
202 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]203 Names[RTLIB::FLOOR_F32] = "floorf";
204 Names[RTLIB::FLOOR_F64] = "floor";
205 Names[RTLIB::FLOOR_F80] = "floorl";
206 Names[RTLIB::FLOOR_F128] = "floorl";
207 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]208 Names[RTLIB::ROUND_F32] = "roundf";
209 Names[RTLIB::ROUND_F64] = "round";
210 Names[RTLIB::ROUND_F80] = "roundl";
211 Names[RTLIB::ROUND_F128] = "roundl";
212 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]213 Names[RTLIB::COPYSIGN_F32] = "copysignf";
214 Names[RTLIB::COPYSIGN_F64] = "copysign";
215 Names[RTLIB::COPYSIGN_F80] = "copysignl";
216 Names[RTLIB::COPYSIGN_F128] = "copysignl";
217 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
218 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
219 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
220 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
221 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
222 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
223 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
224 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
225 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
226 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
227 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
228 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
229 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
230 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
231 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
232 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
233 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
234 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
235 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
236 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
237 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
238 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
239 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
240 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
241 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
242 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
243 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
244 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
245 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
246 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
247 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
248 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
249 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
250 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
251 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
252 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
253 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
254 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
255 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
256 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
257 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
258 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
259 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
260 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
261 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
262 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
263 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
264 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
265 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
266 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
267 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
268 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
269 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
270 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
271 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
272 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
273 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
274 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
275 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
276 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
277 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
278 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
279 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
280 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
281 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
282 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
283 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
284 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
285 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
286 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
287 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
288 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
289 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
290 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
291 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
292 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
293 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
294 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
295 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
296 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
297 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
298 Names[RTLIB::OEQ_F32] = "__eqsf2";
299 Names[RTLIB::OEQ_F64] = "__eqdf2";
300 Names[RTLIB::OEQ_F128] = "__eqtf2";
301 Names[RTLIB::UNE_F32] = "__nesf2";
302 Names[RTLIB::UNE_F64] = "__nedf2";
303 Names[RTLIB::UNE_F128] = "__netf2";
304 Names[RTLIB::OGE_F32] = "__gesf2";
305 Names[RTLIB::OGE_F64] = "__gedf2";
306 Names[RTLIB::OGE_F128] = "__getf2";
307 Names[RTLIB::OLT_F32] = "__ltsf2";
308 Names[RTLIB::OLT_F64] = "__ltdf2";
309 Names[RTLIB::OLT_F128] = "__lttf2";
310 Names[RTLIB::OLE_F32] = "__lesf2";
311 Names[RTLIB::OLE_F64] = "__ledf2";
312 Names[RTLIB::OLE_F128] = "__letf2";
313 Names[RTLIB::OGT_F32] = "__gtsf2";
314 Names[RTLIB::OGT_F64] = "__gtdf2";
315 Names[RTLIB::OGT_F128] = "__gttf2";
316 Names[RTLIB::UO_F32] = "__unordsf2";
317 Names[RTLIB::UO_F64] = "__unorddf2";
318 Names[RTLIB::UO_F128] = "__unordtf2";
319 Names[RTLIB::O_F32] = "__unordsf2";
320 Names[RTLIB::O_F64] = "__unorddf2";
321 Names[RTLIB::O_F128] = "__unordtf2";
322 Names[RTLIB::MEMCPY] = "memcpy";
323 Names[RTLIB::MEMMOVE] = "memmove";
324 Names[RTLIB::MEMSET] = "memset";
325 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
326 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
327 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
328 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
329 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]330 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]331 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
332 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
333 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
334 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]335 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]336 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
337 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
338 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
339 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]340 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]341 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
342 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
343 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
344 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]345 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]346 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
347 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
348 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
349 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]350 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]351 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
352 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
353 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
354 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]355 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]356 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
357 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
358 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
359 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]360 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]361 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
362 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
363 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
364 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]365 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]366 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
367 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
368 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
369 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
370 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
371 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
372 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
373 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
374 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
375 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
376 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
377 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
378 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
379 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
380 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
381 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
382 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
383 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
384 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
385 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
Evan Cheng0e88c7d2013-01-29 02:32:37 +0000[diff] [blame]386
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]387 if (TT.getEnvironment() == Triple::GNU) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]388 Names[RTLIB::SINCOS_F32] = "sincosf";
389 Names[RTLIB::SINCOS_F64] = "sincos";
390 Names[RTLIB::SINCOS_F80] = "sincosl";
391 Names[RTLIB::SINCOS_F128] = "sincosl";
392 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
393 } else {
394 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]395 Names[RTLIB::SINCOS_F32] = nullptr;
396 Names[RTLIB::SINCOS_F64] = nullptr;
397 Names[RTLIB::SINCOS_F80] = nullptr;
398 Names[RTLIB::SINCOS_F128] = nullptr;
399 Names[RTLIB::SINCOS_PPCF128] = nullptr;
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]400 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]401
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]402 if (TT.getOS() != Triple::OpenBSD) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]403 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
404 } else {
405 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]406 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr;
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]407 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]408}
409
410/// InitLibcallCallingConvs - Set default libcall CallingConvs.
411///
412static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
413 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
414 CCs[i] = CallingConv::C;
415 }
416}
417
418/// getFPEXT - Return the FPEXT_*_* value for the given types, or
419/// UNKNOWN_LIBCALL if there is none.
420RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
421 if (OpVT == MVT::f32) {
422 if (RetVT == MVT::f64)
423 return FPEXT_F32_F64;
424 if (RetVT == MVT::f128)
425 return FPEXT_F32_F128;
426 } else if (OpVT == MVT::f64) {
427 if (RetVT == MVT::f128)
428 return FPEXT_F64_F128;
429 }
430
431 return UNKNOWN_LIBCALL;
432}
433
434/// getFPROUND - Return the FPROUND_*_* value for the given types, or
435/// UNKNOWN_LIBCALL if there is none.
436RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
437 if (RetVT == MVT::f32) {
438 if (OpVT == MVT::f64)
439 return FPROUND_F64_F32;
440 if (OpVT == MVT::f80)
441 return FPROUND_F80_F32;
442 if (OpVT == MVT::f128)
443 return FPROUND_F128_F32;
444 if (OpVT == MVT::ppcf128)
445 return FPROUND_PPCF128_F32;
446 } else if (RetVT == MVT::f64) {
447 if (OpVT == MVT::f80)
448 return FPROUND_F80_F64;
449 if (OpVT == MVT::f128)
450 return FPROUND_F128_F64;
451 if (OpVT == MVT::ppcf128)
452 return FPROUND_PPCF128_F64;
453 }
454
455 return UNKNOWN_LIBCALL;
456}
457
458/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
459/// UNKNOWN_LIBCALL if there is none.
460RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
461 if (OpVT == MVT::f32) {
462 if (RetVT == MVT::i8)
463 return FPTOSINT_F32_I8;
464 if (RetVT == MVT::i16)
465 return FPTOSINT_F32_I16;
466 if (RetVT == MVT::i32)
467 return FPTOSINT_F32_I32;
468 if (RetVT == MVT::i64)
469 return FPTOSINT_F32_I64;
470 if (RetVT == MVT::i128)
471 return FPTOSINT_F32_I128;
472 } else if (OpVT == MVT::f64) {
473 if (RetVT == MVT::i8)
474 return FPTOSINT_F64_I8;
475 if (RetVT == MVT::i16)
476 return FPTOSINT_F64_I16;
477 if (RetVT == MVT::i32)
478 return FPTOSINT_F64_I32;
479 if (RetVT == MVT::i64)
480 return FPTOSINT_F64_I64;
481 if (RetVT == MVT::i128)
482 return FPTOSINT_F64_I128;
483 } else if (OpVT == MVT::f80) {
484 if (RetVT == MVT::i32)
485 return FPTOSINT_F80_I32;
486 if (RetVT == MVT::i64)
487 return FPTOSINT_F80_I64;
488 if (RetVT == MVT::i128)
489 return FPTOSINT_F80_I128;
490 } else if (OpVT == MVT::f128) {
491 if (RetVT == MVT::i32)
492 return FPTOSINT_F128_I32;
493 if (RetVT == MVT::i64)
494 return FPTOSINT_F128_I64;
495 if (RetVT == MVT::i128)
496 return FPTOSINT_F128_I128;
497 } else if (OpVT == MVT::ppcf128) {
498 if (RetVT == MVT::i32)
499 return FPTOSINT_PPCF128_I32;
500 if (RetVT == MVT::i64)
501 return FPTOSINT_PPCF128_I64;
502 if (RetVT == MVT::i128)
503 return FPTOSINT_PPCF128_I128;
504 }
505 return UNKNOWN_LIBCALL;
506}
507
508/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
509/// UNKNOWN_LIBCALL if there is none.
510RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
511 if (OpVT == MVT::f32) {
512 if (RetVT == MVT::i8)
513 return FPTOUINT_F32_I8;
514 if (RetVT == MVT::i16)
515 return FPTOUINT_F32_I16;
516 if (RetVT == MVT::i32)
517 return FPTOUINT_F32_I32;
518 if (RetVT == MVT::i64)
519 return FPTOUINT_F32_I64;
520 if (RetVT == MVT::i128)
521 return FPTOUINT_F32_I128;
522 } else if (OpVT == MVT::f64) {
523 if (RetVT == MVT::i8)
524 return FPTOUINT_F64_I8;
525 if (RetVT == MVT::i16)
526 return FPTOUINT_F64_I16;
527 if (RetVT == MVT::i32)
528 return FPTOUINT_F64_I32;
529 if (RetVT == MVT::i64)
530 return FPTOUINT_F64_I64;
531 if (RetVT == MVT::i128)
532 return FPTOUINT_F64_I128;
533 } else if (OpVT == MVT::f80) {
534 if (RetVT == MVT::i32)
535 return FPTOUINT_F80_I32;
536 if (RetVT == MVT::i64)
537 return FPTOUINT_F80_I64;
538 if (RetVT == MVT::i128)
539 return FPTOUINT_F80_I128;
540 } else if (OpVT == MVT::f128) {
541 if (RetVT == MVT::i32)
542 return FPTOUINT_F128_I32;
543 if (RetVT == MVT::i64)
544 return FPTOUINT_F128_I64;
545 if (RetVT == MVT::i128)
546 return FPTOUINT_F128_I128;
547 } else if (OpVT == MVT::ppcf128) {
548 if (RetVT == MVT::i32)
549 return FPTOUINT_PPCF128_I32;
550 if (RetVT == MVT::i64)
551 return FPTOUINT_PPCF128_I64;
552 if (RetVT == MVT::i128)
553 return FPTOUINT_PPCF128_I128;
554 }
555 return UNKNOWN_LIBCALL;
556}
557
558/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
559/// UNKNOWN_LIBCALL if there is none.
560RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
561 if (OpVT == MVT::i32) {
562 if (RetVT == MVT::f32)
563 return SINTTOFP_I32_F32;
564 if (RetVT == MVT::f64)
565 return SINTTOFP_I32_F64;
566 if (RetVT == MVT::f80)
567 return SINTTOFP_I32_F80;
568 if (RetVT == MVT::f128)
569 return SINTTOFP_I32_F128;
570 if (RetVT == MVT::ppcf128)
571 return SINTTOFP_I32_PPCF128;
572 } else if (OpVT == MVT::i64) {
573 if (RetVT == MVT::f32)
574 return SINTTOFP_I64_F32;
575 if (RetVT == MVT::f64)
576 return SINTTOFP_I64_F64;
577 if (RetVT == MVT::f80)
578 return SINTTOFP_I64_F80;
579 if (RetVT == MVT::f128)
580 return SINTTOFP_I64_F128;
581 if (RetVT == MVT::ppcf128)
582 return SINTTOFP_I64_PPCF128;
583 } else if (OpVT == MVT::i128) {
584 if (RetVT == MVT::f32)
585 return SINTTOFP_I128_F32;
586 if (RetVT == MVT::f64)
587 return SINTTOFP_I128_F64;
588 if (RetVT == MVT::f80)
589 return SINTTOFP_I128_F80;
590 if (RetVT == MVT::f128)
591 return SINTTOFP_I128_F128;
592 if (RetVT == MVT::ppcf128)
593 return SINTTOFP_I128_PPCF128;
594 }
595 return UNKNOWN_LIBCALL;
596}
597
598/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
599/// UNKNOWN_LIBCALL if there is none.
600RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
601 if (OpVT == MVT::i32) {
602 if (RetVT == MVT::f32)
603 return UINTTOFP_I32_F32;
604 if (RetVT == MVT::f64)
605 return UINTTOFP_I32_F64;
606 if (RetVT == MVT::f80)
607 return UINTTOFP_I32_F80;
608 if (RetVT == MVT::f128)
609 return UINTTOFP_I32_F128;
610 if (RetVT == MVT::ppcf128)
611 return UINTTOFP_I32_PPCF128;
612 } else if (OpVT == MVT::i64) {
613 if (RetVT == MVT::f32)
614 return UINTTOFP_I64_F32;
615 if (RetVT == MVT::f64)
616 return UINTTOFP_I64_F64;
617 if (RetVT == MVT::f80)
618 return UINTTOFP_I64_F80;
619 if (RetVT == MVT::f128)
620 return UINTTOFP_I64_F128;
621 if (RetVT == MVT::ppcf128)
622 return UINTTOFP_I64_PPCF128;
623 } else if (OpVT == MVT::i128) {
624 if (RetVT == MVT::f32)
625 return UINTTOFP_I128_F32;
626 if (RetVT == MVT::f64)
627 return UINTTOFP_I128_F64;
628 if (RetVT == MVT::f80)
629 return UINTTOFP_I128_F80;
630 if (RetVT == MVT::f128)
631 return UINTTOFP_I128_F128;
632 if (RetVT == MVT::ppcf128)
633 return UINTTOFP_I128_PPCF128;
634 }
635 return UNKNOWN_LIBCALL;
636}
637
638/// InitCmpLibcallCCs - Set default comparison libcall CC.
639///
640static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
641 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
642 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
643 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
644 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
645 CCs[RTLIB::UNE_F32] = ISD::SETNE;
646 CCs[RTLIB::UNE_F64] = ISD::SETNE;
647 CCs[RTLIB::UNE_F128] = ISD::SETNE;
648 CCs[RTLIB::OGE_F32] = ISD::SETGE;
649 CCs[RTLIB::OGE_F64] = ISD::SETGE;
650 CCs[RTLIB::OGE_F128] = ISD::SETGE;
651 CCs[RTLIB::OLT_F32] = ISD::SETLT;
652 CCs[RTLIB::OLT_F64] = ISD::SETLT;
653 CCs[RTLIB::OLT_F128] = ISD::SETLT;
654 CCs[RTLIB::OLE_F32] = ISD::SETLE;
655 CCs[RTLIB::OLE_F64] = ISD::SETLE;
656 CCs[RTLIB::OLE_F128] = ISD::SETLE;
657 CCs[RTLIB::OGT_F32] = ISD::SETGT;
658 CCs[RTLIB::OGT_F64] = ISD::SETGT;
659 CCs[RTLIB::OGT_F128] = ISD::SETGT;
660 CCs[RTLIB::UO_F32] = ISD::SETNE;
661 CCs[RTLIB::UO_F64] = ISD::SETNE;
662 CCs[RTLIB::UO_F128] = ISD::SETNE;
663 CCs[RTLIB::O_F32] = ISD::SETEQ;
664 CCs[RTLIB::O_F64] = ISD::SETEQ;
665 CCs[RTLIB::O_F128] = ISD::SETEQ;
666}
667
668/// NOTE: The constructor takes ownership of TLOF.
669TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
670 const TargetLoweringObjectFile *tlof)
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]671 : TM(tm), DL(TM.getDataLayout()), TLOF(*tlof) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]672 initActions();
673
674 // Perform these initializations only once.
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]675 IsLittleEndian = DL->isLittleEndian();
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]676 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
677 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
678 = MaxStoresPerMemmoveOptSize = 4;
679 UseUnderscoreSetJmp = false;
680 UseUnderscoreLongJmp = false;
681 SelectIsExpensive = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]682 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]683 HasExtractBitsInsn = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]684 IntDivIsCheap = false;
685 Pow2DivIsCheap = false;
686 JumpIsExpensive = false;
687 PredictableSelectIsExpensive = false;
Tim Northovercea0abb2014-03-29 08:22:29 +0000[diff] [blame]688 MaskAndBranchFoldingIsLegal = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]689 StackPointerRegisterToSaveRestore = 0;
690 ExceptionPointerRegister = 0;
691 ExceptionSelectorRegister = 0;
692 BooleanContents = UndefinedBooleanContent;
693 BooleanVectorContents = UndefinedBooleanContent;
694 SchedPreferenceInfo = Sched::ILP;
695 JumpBufSize = 0;
696 JumpBufAlignment = 0;
697 MinFunctionAlignment = 0;
698 PrefFunctionAlignment = 0;
699 PrefLoopAlignment = 0;
700 MinStackArgumentAlignment = 1;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]701 InsertFencesForAtomic = false;
702 SupportJumpTables = true;
703 MinimumJumpTableEntries = 4;
704
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]705 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple()));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]706 InitCmpLibcallCCs(CmpLibcallCCs);
707 InitLibcallCallingConvs(LibcallCallingConvs);
708}
709
710TargetLoweringBase::~TargetLoweringBase() {
711 delete &TLOF;
712}
713
714void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]715 // All operations default to being supported.
716 memset(OpActions, 0, sizeof(OpActions));
717 memset(LoadExtActions, 0, sizeof(LoadExtActions));
718 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
719 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
720 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]721 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
722 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]723
724 // Set default actions for various operations.
725 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
726 // Default all indexed load / store to expand.
727 for (unsigned IM = (unsigned)ISD::PRE_INC;
728 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
729 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
730 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
731 }
732
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]733 // Most backends expect to see the node which just returns the value loaded.
734 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
735 (MVT::SimpleValueType)VT, Expand);
736
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]737 // These operations default to expand.
738 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]740
741 // These library functions default to expand.
742 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]743
744 // These operations default to expand for vector types.
745 if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
746 VT <= MVT::LAST_VECTOR_VALUETYPE)
747 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]748 }
749
750 // Most targets ignore the @llvm.prefetch intrinsic.
751 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
752
753 // ConstantFP nodes default to expand. Targets can either change this to
754 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
755 // to optimize expansions for certain constants.
756 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
757 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
758 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
759 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
760 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
761
762 // These library functions default to expand.
763 setOperationAction(ISD::FLOG , MVT::f16, Expand);
764 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
765 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
766 setOperationAction(ISD::FEXP , MVT::f16, Expand);
767 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
768 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
769 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
770 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
771 setOperationAction(ISD::FRINT, MVT::f16, Expand);
772 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]773 setOperationAction(ISD::FROUND, MVT::f16, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]774 setOperationAction(ISD::FLOG , MVT::f32, Expand);
775 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
776 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
777 setOperationAction(ISD::FEXP , MVT::f32, Expand);
778 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
779 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
780 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
781 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
782 setOperationAction(ISD::FRINT, MVT::f32, Expand);
783 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]784 setOperationAction(ISD::FROUND, MVT::f32, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]785 setOperationAction(ISD::FLOG , MVT::f64, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
788 setOperationAction(ISD::FEXP , MVT::f64, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
790 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
791 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
792 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
793 setOperationAction(ISD::FRINT, MVT::f64, Expand);
794 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]795 setOperationAction(ISD::FROUND, MVT::f64, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]796 setOperationAction(ISD::FLOG , MVT::f128, Expand);
797 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
798 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
799 setOperationAction(ISD::FEXP , MVT::f128, Expand);
800 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
801 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
802 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
803 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
804 setOperationAction(ISD::FRINT, MVT::f128, Expand);
805 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]806 setOperationAction(ISD::FROUND, MVT::f128, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]807
808 // Default ISD::TRAP to expand (which turns it into abort).
809 setOperationAction(ISD::TRAP, MVT::Other, Expand);
810
811 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
812 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
813 //
814 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]815}
816
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]817MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
818 return MVT::getIntegerVT(getPointerSizeInBits(AS));
819}
820
821unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]822 return DL->getPointerSizeInBits(AS);
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]823}
824
825unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
826 assert(Ty->isPointerTy());
827 return getPointerSizeInBits(Ty->getPointerAddressSpace());
828}
829
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]830MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]831 return MVT::getIntegerVT(8*DL->getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]832}
833
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]834EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
835 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
836 if (LHSTy.isVector())
837 return LHSTy;
838 return getScalarShiftAmountTy(LHSTy);
839}
840
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]841/// canOpTrap - Returns true if the operation can trap for the value type.
842/// VT must be a legal type.
843bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
844 assert(isTypeLegal(VT));
845 switch (Op) {
846 default:
847 return false;
848 case ISD::FDIV:
849 case ISD::FREM:
850 case ISD::SDIV:
851 case ISD::UDIV:
852 case ISD::SREM:
853 case ISD::UREM:
854 return true;
855 }
856}
857
858
859static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
860 unsigned &NumIntermediates,
861 MVT &RegisterVT,
862 TargetLoweringBase *TLI) {
863 // Figure out the right, legal destination reg to copy into.
864 unsigned NumElts = VT.getVectorNumElements();
865 MVT EltTy = VT.getVectorElementType();
866
867 unsigned NumVectorRegs = 1;
868
869 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
870 // could break down into LHS/RHS like LegalizeDAG does.
871 if (!isPowerOf2_32(NumElts)) {
872 NumVectorRegs = NumElts;
873 NumElts = 1;
874 }
875
876 // Divide the input until we get to a supported size. This will always
877 // end with a scalar if the target doesn't support vectors.
878 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
879 NumElts >>= 1;
880 NumVectorRegs <<= 1;
881 }
882
883 NumIntermediates = NumVectorRegs;
884
885 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
886 if (!TLI->isTypeLegal(NewVT))
887 NewVT = EltTy;
888 IntermediateVT = NewVT;
889
890 unsigned NewVTSize = NewVT.getSizeInBits();
891
892 // Convert sizes such as i33 to i64.
893 if (!isPowerOf2_32(NewVTSize))
894 NewVTSize = NextPowerOf2(NewVTSize);
895
896 MVT DestVT = TLI->getRegisterType(NewVT);
897 RegisterVT = DestVT;
898 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
899 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
900
901 // Otherwise, promotion or legal types use the same number of registers as
902 // the vector decimated to the appropriate level.
903 return NumVectorRegs;
904}
905
906/// isLegalRC - Return true if the value types that can be represented by the
907/// specified register class are all legal.
908bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
909 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
910 I != E; ++I) {
911 if (isTypeLegal(*I))
912 return true;
913 }
914 return false;
915}
916
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]917/// Replace/modify any TargetFrameIndex operands with a targte-dependent
918/// sequence of memory operands that is recognized by PrologEpilogInserter.
919MachineBasicBlock*
920TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
921 MachineBasicBlock *MBB) const {
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]922 MachineFunction &MF = *MI->getParent()->getParent();
923
924 // MI changes inside this loop as we grow operands.
925 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
926 MachineOperand &MO = MI->getOperand(OperIdx);
927 if (!MO.isFI())
928 continue;
929
930 // foldMemoryOperand builds a new MI after replacing a single FI operand
931 // with the canonical set of five x86 addressing-mode operands.
932 int FI = MO.getIndex();
933 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
934
935 // Copy operands before the frame-index.
936 for (unsigned i = 0; i < OperIdx; ++i)
937 MIB.addOperand(MI->getOperand(i));
938 // Add frame index operands: direct-mem-ref tag, #FI, offset.
939 MIB.addImm(StackMaps::DirectMemRefOp);
940 MIB.addOperand(MI->getOperand(OperIdx));
941 MIB.addImm(0);
942 // Copy the operands after the frame index.
943 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
944 MIB.addOperand(MI->getOperand(i));
945
946 // Inherit previous memory operands.
947 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
948 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
949
950 // Add a new memory operand for this FI.
951 const MachineFrameInfo &MFI = *MF.getFrameInfo();
952 assert(MFI.getObjectOffset(FI) != -1);
953 MachineMemOperand *MMO =
954 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
955 MachineMemOperand::MOLoad,
956 TM.getDataLayout()->getPointerSize(),
957 MFI.getObjectAlignment(FI));
958 MIB->addMemOperand(MF, MMO);
959
960 // Replace the instruction and update the operand index.
961 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
962 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
963 MI->eraseFromParent();
964 MI = MIB;
965 }
966 return MBB;
967}
968
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]969/// findRepresentativeClass - Return the largest legal super-reg register class
970/// of the register class for the specified type and its associated "cost".
971std::pair<const TargetRegisterClass*, uint8_t>
972TargetLoweringBase::findRepresentativeClass(MVT VT) const {
973 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
974 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
975 if (!RC)
976 return std::make_pair(RC, 0);
977
978 // Compute the set of all super-register classes.
979 BitVector SuperRegRC(TRI->getNumRegClasses());
980 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
981 SuperRegRC.setBitsInMask(RCI.getMask());
982
983 // Find the first legal register class with the largest spill size.
984 const TargetRegisterClass *BestRC = RC;
985 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
986 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
987 // We want the largest possible spill size.
988 if (SuperRC->getSize() <= BestRC->getSize())
989 continue;
990 if (!isLegalRC(SuperRC))
991 continue;
992 BestRC = SuperRC;
993 }
994 return std::make_pair(BestRC, 1);
995}
996
997/// computeRegisterProperties - Once all of the register classes are added,
998/// this allows us to compute derived properties we expose.
999void TargetLoweringBase::computeRegisterProperties() {
1000 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
1001 "Too many value types for ValueTypeActions to hold!");
1002
1003 // Everything defaults to needing one register.
1004 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1005 NumRegistersForVT[i] = 1;
1006 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1007 }
1008 // ...except isVoid, which doesn't need any registers.
1009 NumRegistersForVT[MVT::isVoid] = 0;
1010
1011 // Find the largest integer register class.
1012 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1013 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1014 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1015
1016 // Every integer value type larger than this largest register takes twice as
1017 // many registers to represent as the previous ValueType.
1018 for (unsigned ExpandedReg = LargestIntReg + 1;
1019 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1020 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1021 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1022 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1023 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1024 TypeExpandInteger);
1025 }
1026
1027 // Inspect all of the ValueType's smaller than the largest integer
1028 // register to see which ones need promotion.
1029 unsigned LegalIntReg = LargestIntReg;
1030 for (unsigned IntReg = LargestIntReg - 1;
1031 IntReg >= (unsigned)MVT::i1; --IntReg) {
1032 MVT IVT = (MVT::SimpleValueType)IntReg;
1033 if (isTypeLegal(IVT)) {
1034 LegalIntReg = IntReg;
1035 } else {
1036 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1037 (const MVT::SimpleValueType)LegalIntReg;
1038 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1039 }
1040 }
1041
1042 // ppcf128 type is really two f64's.
1043 if (!isTypeLegal(MVT::ppcf128)) {
1044 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1045 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1046 TransformToType[MVT::ppcf128] = MVT::f64;
1047 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1048 }
1049
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1050 // Decide how to handle f128. If the target does not have native f128 support,
1051 // expand it to i128 and we will be generating soft float library calls.
1052 if (!isTypeLegal(MVT::f128)) {
1053 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1054 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1055 TransformToType[MVT::f128] = MVT::i128;
1056 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1057 }
1058
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1059 // Decide how to handle f64. If the target does not have native f64 support,
1060 // expand it to i64 and we will be generating soft float library calls.
1061 if (!isTypeLegal(MVT::f64)) {
1062 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1063 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1064 TransformToType[MVT::f64] = MVT::i64;
1065 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1066 }
1067
1068 // Decide how to handle f32. If the target does not have native support for
1069 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1070 if (!isTypeLegal(MVT::f32)) {
1071 if (isTypeLegal(MVT::f64)) {
1072 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
1073 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
1074 TransformToType[MVT::f32] = MVT::f64;
1075 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
1076 } else {
1077 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1078 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1079 TransformToType[MVT::f32] = MVT::i32;
1080 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1081 }
1082 }
1083
1084 // Loop over all of the vector value types to see which need transformations.
1085 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1086 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame^]1087 MVT VT = (MVT::SimpleValueType) i;
1088 if (isTypeLegal(VT))
1089 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1090
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1091 MVT EltVT = VT.getVectorElementType();
1092 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame^]1093 bool IsLegalWiderType = false;
1094 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1095 switch (PreferredAction) {
1096 case TypePromoteInteger: {
1097 // Try to promote the elements of integer vectors. If no legal
1098 // promotion was found, fall through to the widen-vector method.
1099 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1100 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1101 // Promote vectors of integers to vectors with the same number
1102 // of elements, with a wider element type.
1103 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame^]1104 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1105 && SVT.getScalarType().isInteger()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1106 TransformToType[i] = SVT;
1107 RegisterTypeForVT[i] = SVT;
1108 NumRegistersForVT[i] = 1;
1109 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1110 IsLegalWiderType = true;
1111 break;
1112 }
1113 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame^]1114 if (IsLegalWiderType)
1115 break;
1116 }
1117 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1118 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame^]1119 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1120 MVT SVT = (MVT::SimpleValueType) nVT;
1121 if (SVT.getVectorElementType() == EltVT
1122 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1123 TransformToType[i] = SVT;
1124 RegisterTypeForVT[i] = SVT;
1125 NumRegistersForVT[i] = 1;
1126 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1127 IsLegalWiderType = true;
1128 break;
1129 }
1130 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame^]1131 if (IsLegalWiderType)
1132 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1133 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame^]1134 case TypeSplitVector:
1135 case TypeScalarizeVector: {
1136 MVT IntermediateVT;
1137 MVT RegisterVT;
1138 unsigned NumIntermediates;
1139 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1140 NumIntermediates, RegisterVT, this);
1141 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1142
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame^]1143 MVT NVT = VT.getPow2VectorType();
1144 if (NVT == VT) {
1145 // Type is already a power of 2. The default action is to split.
1146 TransformToType[i] = MVT::Other;
1147 if (PreferredAction == TypeScalarizeVector)
1148 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1149 else
1150 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1151 } else {
1152 TransformToType[i] = NVT;
1153 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1154 }
1155 break;
1156 }
1157 default:
1158 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1159 }
1160 }
1161
1162 // Determine the 'representative' register class for each value type.
1163 // An representative register class is the largest (meaning one which is
1164 // not a sub-register class / subreg register class) legal register class for
1165 // a group of value types. For example, on i386, i8, i16, and i32
1166 // representative would be GR32; while on x86_64 it's GR64.
1167 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1168 const TargetRegisterClass* RRC;
1169 uint8_t Cost;
Benjamin Kramerd6f1f842014-03-02 13:30:33 +0000[diff] [blame]1170 std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1171 RepRegClassForVT[i] = RRC;
1172 RepRegClassCostForVT[i] = Cost;
1173 }
1174}
1175
Matt Arsenault758659232013-05-18 00:21:46 +0000[diff] [blame]1176EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1177 assert(!VT.isVector() && "No default SetCC type for vectors!");
1178 return getPointerTy(0).SimpleTy;
1179}
1180
1181MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1182 return MVT::i32; // return the default value
1183}
1184
1185/// getVectorTypeBreakdown - Vector types are broken down into some number of
1186/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1187/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1188/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1189///
1190/// This method returns the number of registers needed, and the VT for each
1191/// register. It also returns the VT and quantity of the intermediate values
1192/// before they are promoted/expanded.
1193///
1194unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1195 EVT &IntermediateVT,
1196 unsigned &NumIntermediates,
1197 MVT &RegisterVT) const {
1198 unsigned NumElts = VT.getVectorNumElements();
1199
1200 // If there is a wider vector type with the same element type as this one,
1201 // or a promoted vector type that has the same number of elements which
1202 // are wider, then we should convert to that legal vector type.
1203 // This handles things like <2 x float> -> <4 x float> and
1204 // <4 x i1> -> <4 x i32>.
1205 LegalizeTypeAction TA = getTypeAction(Context, VT);
1206 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1207 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1208 if (isTypeLegal(RegisterEVT)) {
1209 IntermediateVT = RegisterEVT;
1210 RegisterVT = RegisterEVT.getSimpleVT();
1211 NumIntermediates = 1;
1212 return 1;
1213 }
1214 }
1215
1216 // Figure out the right, legal destination reg to copy into.
1217 EVT EltTy = VT.getVectorElementType();
1218
1219 unsigned NumVectorRegs = 1;
1220
1221 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1222 // could break down into LHS/RHS like LegalizeDAG does.
1223 if (!isPowerOf2_32(NumElts)) {
1224 NumVectorRegs = NumElts;
1225 NumElts = 1;
1226 }
1227
1228 // Divide the input until we get to a supported size. This will always
1229 // end with a scalar if the target doesn't support vectors.
1230 while (NumElts > 1 && !isTypeLegal(
1231 EVT::getVectorVT(Context, EltTy, NumElts))) {
1232 NumElts >>= 1;
1233 NumVectorRegs <<= 1;
1234 }
1235
1236 NumIntermediates = NumVectorRegs;
1237
1238 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1239 if (!isTypeLegal(NewVT))
1240 NewVT = EltTy;
1241 IntermediateVT = NewVT;
1242
1243 MVT DestVT = getRegisterType(Context, NewVT);
1244 RegisterVT = DestVT;
1245 unsigned NewVTSize = NewVT.getSizeInBits();
1246
1247 // Convert sizes such as i33 to i64.
1248 if (!isPowerOf2_32(NewVTSize))
1249 NewVTSize = NextPowerOf2(NewVTSize);
1250
1251 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1252 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1253
1254 // Otherwise, promotion or legal types use the same number of registers as
1255 // the vector decimated to the appropriate level.
1256 return NumVectorRegs;
1257}
1258
1259/// Get the EVTs and ArgFlags collections that represent the legalized return
1260/// type of the given function. This does not require a DAG or a return value,
1261/// and is suitable for use before any DAGs for the function are constructed.
1262/// TODO: Move this out of TargetLowering.cpp.
1263void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1264 SmallVectorImpl<ISD::OutputArg> &Outs,
1265 const TargetLowering &TLI) {
1266 SmallVector<EVT, 4> ValueVTs;
1267 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1268 unsigned NumValues = ValueVTs.size();
1269 if (NumValues == 0) return;
1270
1271 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1272 EVT VT = ValueVTs[j];
1273 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1274
1275 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1276 ExtendKind = ISD::SIGN_EXTEND;
1277 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1278 ExtendKind = ISD::ZERO_EXTEND;
1279
1280 // FIXME: C calling convention requires the return type to be promoted to
1281 // at least 32-bit. But this is not necessary for non-C calling
1282 // conventions. The frontend should mark functions whose return values
1283 // require promoting with signext or zeroext attributes.
1284 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1285 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1286 if (VT.bitsLT(MinVT))
1287 VT = MinVT;
1288 }
1289
1290 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1291 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1292
1293 // 'inreg' on function refers to return value
1294 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1295 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1296 Flags.setInReg();
1297
1298 // Propagate extension type if any
1299 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1300 Flags.setSExt();
1301 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1302 Flags.setZExt();
1303
1304 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1305 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1306 }
1307}
1308
1309/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1310/// function arguments in the caller parameter area. This is the actual
1311/// alignment, not its logarithm.
1312unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]1313 return DL->getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1314}
1315
1316//===----------------------------------------------------------------------===//
1317// TargetTransformInfo Helpers
1318//===----------------------------------------------------------------------===//
1319
1320int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1321 enum InstructionOpcodes {
1322#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1323#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1324#include "llvm/IR/Instruction.def"
1325 };
1326 switch (static_cast<InstructionOpcodes>(Opcode)) {
1327 case Ret: return 0;
1328 case Br: return 0;
1329 case Switch: return 0;
1330 case IndirectBr: return 0;
1331 case Invoke: return 0;
1332 case Resume: return 0;
1333 case Unreachable: return 0;
1334 case Add: return ISD::ADD;
1335 case FAdd: return ISD::FADD;
1336 case Sub: return ISD::SUB;
1337 case FSub: return ISD::FSUB;
1338 case Mul: return ISD::MUL;
1339 case FMul: return ISD::FMUL;
1340 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1341 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1342 case FDiv: return ISD::FDIV;
1343 case URem: return ISD::UREM;
1344 case SRem: return ISD::SREM;
1345 case FRem: return ISD::FREM;
1346 case Shl: return ISD::SHL;
1347 case LShr: return ISD::SRL;
1348 case AShr: return ISD::SRA;
1349 case And: return ISD::AND;
1350 case Or: return ISD::OR;
1351 case Xor: return ISD::XOR;
1352 case Alloca: return 0;
1353 case Load: return ISD::LOAD;
1354 case Store: return ISD::STORE;
1355 case GetElementPtr: return 0;
1356 case Fence: return 0;
1357 case AtomicCmpXchg: return 0;
1358 case AtomicRMW: return 0;
1359 case Trunc: return ISD::TRUNCATE;
1360 case ZExt: return ISD::ZERO_EXTEND;
1361 case SExt: return ISD::SIGN_EXTEND;
1362 case FPToUI: return ISD::FP_TO_UINT;
1363 case FPToSI: return ISD::FP_TO_SINT;
1364 case UIToFP: return ISD::UINT_TO_FP;
1365 case SIToFP: return ISD::SINT_TO_FP;
1366 case FPTrunc: return ISD::FP_ROUND;
1367 case FPExt: return ISD::FP_EXTEND;
1368 case PtrToInt: return ISD::BITCAST;
1369 case IntToPtr: return ISD::BITCAST;
1370 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1371 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1372 case ICmp: return ISD::SETCC;
1373 case FCmp: return ISD::SETCC;
1374 case PHI: return 0;
1375 case Call: return 0;
1376 case Select: return ISD::SELECT;
1377 case UserOp1: return 0;
1378 case UserOp2: return 0;
1379 case VAArg: return 0;
1380 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1381 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1382 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1383 case ExtractValue: return ISD::MERGE_VALUES;
1384 case InsertValue: return ISD::MERGE_VALUES;
1385 case LandingPad: return 0;
1386 }
1387
1388 llvm_unreachable("Unknown instruction type encountered!");
1389}
1390
1391std::pair<unsigned, MVT>
1392TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1393 LLVMContext &C = Ty->getContext();
1394 EVT MTy = getValueType(Ty);
1395
1396 unsigned Cost = 1;
1397 // We keep legalizing the type until we find a legal kind. We assume that
1398 // the only operation that costs anything is the split. After splitting
1399 // we need to handle two types.
1400 while (true) {
1401 LegalizeKind LK = getTypeConversion(C, MTy);
1402
1403 if (LK.first == TypeLegal)
1404 return std::make_pair(Cost, MTy.getSimpleVT());
1405
1406 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1407 Cost *= 2;
1408
1409 // Keep legalizing the type.
1410 MTy = LK.second;
1411 }
1412}
1413
1414//===----------------------------------------------------------------------===//
1415// Loop Strength Reduction hooks
1416//===----------------------------------------------------------------------===//
1417
1418/// isLegalAddressingMode - Return true if the addressing mode represented
1419/// by AM is legal for this target, for a load/store of the specified type.
1420bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
1421 Type *Ty) const {
1422 // The default implementation of this implements a conservative RISCy, r+r and
1423 // r+i addr mode.
1424
1425 // Allows a sign-extended 16-bit immediate field.
1426 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1427 return false;
1428
1429 // No global is ever allowed as a base.
1430 if (AM.BaseGV)
1431 return false;
1432
1433 // Only support r+r,
1434 switch (AM.Scale) {
1435 case 0: // "r+i" or just "i", depending on HasBaseReg.
1436 break;
1437 case 1:
1438 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1439 return false;
1440 // Otherwise we have r+r or r+i.
1441 break;
1442 case 2:
1443 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1444 return false;
1445 // Allow 2*r as r+r.
1446 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1447 default: // Don't allow n * r
1448 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1449 }
1450
1451 return true;
1452}