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gerrit-public.fairphone.software / toolchain / llvm-project / a032374ea0d069bff44045eee72ebdaa100ccc7a / . / llvm / test / Transforms / LoopUnswitch / 2011-11-18-TwoSwitches-Threshold.ll
blob: c3bf5966ad05f306882469add9e33ae6d6052b20 [file] [log] [blame]
Stepan Dyatkovskiy82165692012-01-11 08:40:51 +0000[diff] [blame]1; RUN: opt -loop-unswitch -loop-unswitch-threshold 13 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s
Dmitri Gribenkob137c9e2012-12-30 01:28:40 +0000[diff] [blame]2; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 13 -verify-loop-info -verify-dom-info < %s | FileCheck %s
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]3
4; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted
5; STATS: 1 loop-unswitch - Number of switches unswitched
6
7; ModuleID = '../llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll'
8
9; CHECK: %1 = icmp eq i32 %c, 1
10; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge
11
12; CHECK: ..split_crit_edge: ; preds = %0
13; CHECK-NEXT: br label %.split
14
15; CHECK: .split.us: ; preds = %0
16; CHECK-NEXT: br label %loop_begin.us
17
18; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us
19; CHECK: switch i32 1, label %second_switch.us [
20; CHECK-NEXT: i32 1, label %inc.us
21
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]22; CHECK: second_switch.us: ; preds = %loop_begin.us
23; CHECK-NEXT: switch i32 %d, label %default.us [
24; CHECK-NEXT: i32 1, label %inc.us
25; CHECK-NEXT: ]
26
Andrew Trickfb2ba3e2012-06-26 04:11:38 +0000[diff] [blame]27; CHECK: inc.us: ; preds = %second_switch.us, %loop_begin.us
Bill Wendlinga0323742013-02-22 09:09:42 +0000[diff] [blame^]28; CHECK-NEXT: call void @incf() [[NOR_NUW:#[0-9]+]]
Andrew Trickfb2ba3e2012-06-26 04:11:38 +0000[diff] [blame]29; CHECK-NEXT: br label %loop_begin.backedge.us
30
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]31; CHECK: .split: ; preds = %..split_crit_edge
32; CHECK-NEXT: br label %loop_begin
33
34; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split
35; CHECK: switch i32 %c, label %second_switch [
36; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge
37; CHECK-NEXT: ]
38
39; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin
40; CHECK-NEXT: br i1 true, label %us-unreachable, label %inc
41
42; CHECK: second_switch: ; preds = %loop_begin
43; CHECK-NEXT: switch i32 %d, label %default [
44; CHECK-NEXT: i32 1, label %inc
45; CHECK-NEXT: ]
46
47; CHECK: inc: ; preds = %loop_begin.inc_crit_edge, %second_switch
Bill Wendlinga0323742013-02-22 09:09:42 +0000[diff] [blame^]48; CHECK-NEXT: call void @incf() [[NOR_NUW]]
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]49; CHECK-NEXT: br label %loop_begin.backedge
50
51define i32 @test(i32* %var) {
52 %mem = alloca i32
53 store i32 2, i32* %mem
54 %c = load i32* %mem
55 %d = load i32* %mem
56
57 br label %loop_begin
58
59loop_begin:
60
61 %var_val = load i32* %var
62
63 switch i32 %c, label %second_switch [
64 i32 1, label %inc
65 ]
66
67second_switch:
68 switch i32 %d, label %default [
69 i32 1, label %inc
70 ]
71
72inc:
73 call void @incf() noreturn nounwind
74 br label %loop_begin
75
Andrew Trickfb2ba3e2012-06-26 04:11:38 +0000[diff] [blame]76default:
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]77 br label %loop_begin
78
79loop_exit:
80 ret i32 0
81}
82
83declare void @incf() noreturn
84declare void @decf() noreturn
Bill Wendlinga0323742013-02-22 09:09:42 +0000[diff] [blame^]85
86; CHECK: attributes #0 = { noreturn }
87; CHECK: attributes [[NOR_NUW]] = { noreturn nounwind }