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Ulrich Weigandce4c1092015-05-05 19:25:42 +00001; Test v16i8 absolute.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test with slt.
6define <16 x i8> @f1(<16 x i8> %val) {
7; CHECK-LABEL: f1:
8; CHECK: vlpb %v24, %v24
9; CHECK: br %r14
10 %cmp = icmp slt <16 x i8> %val, zeroinitializer
11 %neg = sub <16 x i8> zeroinitializer, %val
12 %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
13 ret <16 x i8> %ret
14}
15
16; Test with sle.
17define <16 x i8> @f2(<16 x i8> %val) {
18; CHECK-LABEL: f2:
19; CHECK: vlpb %v24, %v24
20; CHECK: br %r14
21 %cmp = icmp sle <16 x i8> %val, zeroinitializer
22 %neg = sub <16 x i8> zeroinitializer, %val
23 %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
24 ret <16 x i8> %ret
25}
26
27; Test with sgt.
28define <16 x i8> @f3(<16 x i8> %val) {
29; CHECK-LABEL: f3:
30; CHECK: vlpb %v24, %v24
31; CHECK: br %r14
32 %cmp = icmp sgt <16 x i8> %val, zeroinitializer
33 %neg = sub <16 x i8> zeroinitializer, %val
34 %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
35 ret <16 x i8> %ret
36}
37
38; Test with sge.
39define <16 x i8> @f4(<16 x i8> %val) {
40; CHECK-LABEL: f4:
41; CHECK: vlpb %v24, %v24
42; CHECK: br %r14
43 %cmp = icmp sge <16 x i8> %val, zeroinitializer
44 %neg = sub <16 x i8> zeroinitializer, %val
45 %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
46 ret <16 x i8> %ret
47}
48
49; Test that negative absolute uses VLPB too. There is no vector equivalent
50; of LOAD NEGATIVE.
51define <16 x i8> @f5(<16 x i8> %val) {
52; CHECK-LABEL: f5:
53; CHECK: vlpb [[REG:%v[0-9]+]], %v24
54; CHECK: vlcb %v24, [[REG]]
55; CHECK: br %r14
56 %cmp = icmp slt <16 x i8> %val, zeroinitializer
57 %neg = sub <16 x i8> zeroinitializer, %val
58 %abs = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
59 %ret = sub <16 x i8> zeroinitializer, %abs
60 ret <16 x i8> %ret
61}
62
63; Try another form of negative absolute (slt version).
64define <16 x i8> @f6(<16 x i8> %val) {
65; CHECK-LABEL: f6:
66; CHECK: vlpb [[REG:%v[0-9]+]], %v24
67; CHECK: vlcb %v24, [[REG]]
68; CHECK: br %r14
69 %cmp = icmp slt <16 x i8> %val, zeroinitializer
70 %neg = sub <16 x i8> zeroinitializer, %val
71 %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
72 ret <16 x i8> %ret
73}
74
75; Test with sle.
76define <16 x i8> @f7(<16 x i8> %val) {
77; CHECK-LABEL: f7:
78; CHECK: vlpb [[REG:%v[0-9]+]], %v24
79; CHECK: vlcb %v24, [[REG]]
80; CHECK: br %r14
81 %cmp = icmp sle <16 x i8> %val, zeroinitializer
82 %neg = sub <16 x i8> zeroinitializer, %val
83 %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
84 ret <16 x i8> %ret
85}
86
87; Test with sgt.
88define <16 x i8> @f8(<16 x i8> %val) {
89; CHECK-LABEL: f8:
90; CHECK: vlpb [[REG:%v[0-9]+]], %v24
91; CHECK: vlcb %v24, [[REG]]
92; CHECK: br %r14
93 %cmp = icmp sgt <16 x i8> %val, zeroinitializer
94 %neg = sub <16 x i8> zeroinitializer, %val
95 %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
96 ret <16 x i8> %ret
97}
98
99; Test with sge.
100define <16 x i8> @f9(<16 x i8> %val) {
101; CHECK-LABEL: f9:
102; CHECK: vlpb [[REG:%v[0-9]+]], %v24
103; CHECK: vlcb %v24, [[REG]]
104; CHECK: br %r14
105 %cmp = icmp sge <16 x i8> %val, zeroinitializer
106 %neg = sub <16 x i8> zeroinitializer, %val
107 %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
108 ret <16 x i8> %ret
109}
110
111; Test with an SRA-based boolean vector.
112define <16 x i8> @f10(<16 x i8> %val) {
113; CHECK-LABEL: f10:
114; CHECK: vlpb %v24, %v24
115; CHECK: br %r14
116 %shr = ashr <16 x i8> %val,
117 <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,
118 i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
119 %neg = sub <16 x i8> zeroinitializer, %val
120 %and1 = and <16 x i8> %shr, %neg
121 %not = xor <16 x i8> %shr,
122 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
123 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
124 %and2 = and <16 x i8> %not, %val
125 %ret = or <16 x i8> %and1, %and2
126 ret <16 x i8> %ret
127}
128
129; ...and again in reverse
130define <16 x i8> @f11(<16 x i8> %val) {
131; CHECK-LABEL: f11:
132; CHECK: vlpb [[REG:%v[0-9]+]], %v24
133; CHECK: vlcb %v24, [[REG]]
134; CHECK: br %r14
135 %shr = ashr <16 x i8> %val,
136 <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,
137 i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
138 %and1 = and <16 x i8> %shr, %val
139 %not = xor <16 x i8> %shr,
140 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
141 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
142 %neg = sub <16 x i8> zeroinitializer, %val
143 %and2 = and <16 x i8> %not, %neg
144 %ret = or <16 x i8> %and1, %and2
145 ret <16 x i8> %ret
146}