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Chris Lattnercab0b442003-01-13 20:01:16 +00001//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
Misha Brukman835702a2005-04-21 22:36:52 +00002//
John Criswell482202a2003-10-20 19:43:21 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukman835702a2005-04-21 22:36:52 +00007//
John Criswell482202a2003-10-20 19:43:21 +00008//===----------------------------------------------------------------------===//
Misha Brukman835702a2005-04-21 22:36:52 +00009//
Chris Lattner5ab42e52003-05-07 20:08:36 +000010// This file implements the LiveVariable analysis pass. For each machine
11// instruction in the function, this pass calculates the set of registers that
12// are immediately dead after the instruction (i.e., the instruction calculates
13// the value, but it is never used) and the set of registers that are used by
14// the instruction, but are never used after the instruction (i.e., they are
15// killed).
16//
Lang Hames652f2122012-04-01 19:27:25 +000017// This class computes live variables using a sparse implementation based on
Chris Lattner5ab42e52003-05-07 20:08:36 +000018// the machine code SSA form. This class computes live variable information for
19// each virtual and _register allocatable_ physical register in a function. It
20// uses the dominance properties of SSA form to efficiently compute live
21// variables for virtual registers, and assumes that physical registers are only
22// live within a single basic block (allowing it to do a single local analysis
23// to resolve physical register lifetimes in each basic block). If a physical
24// register is not register allocatable, it is not tracked. This is useful for
25// things like the stack pointer and condition codes.
26//
Chris Lattnercab0b442003-01-13 20:01:16 +000027//===----------------------------------------------------------------------===//
28
29#include "llvm/CodeGen/LiveVariables.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000030#include "llvm/ADT/DepthFirstIterator.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallPtrSet.h"
33#include "llvm/ADT/SmallSet.h"
Chris Lattnercab0b442003-01-13 20:01:16 +000034#include "llvm/CodeGen/MachineInstr.h"
Chris Lattnera10fff52007-12-31 04:13:23 +000035#include "llvm/CodeGen/MachineRegisterInfo.h"
Owen Andersona1022902008-08-04 23:54:43 +000036#include "llvm/CodeGen/Passes.h"
David Greened599dcd2010-01-04 23:02:10 +000037#include "llvm/Support/Debug.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000038#include "llvm/Support/ErrorHandling.h"
Chris Lattnerb4d58d72003-01-14 22:00:31 +000039#include "llvm/Target/TargetInstrInfo.h"
Chris Lattnereeacce52005-08-24 00:09:33 +000040#include <algorithm>
Chris Lattner07708622004-01-30 22:08:53 +000041using namespace llvm;
Brian Gaeke960707c2003-11-11 22:41:34 +000042
Devang Patel8c78a0b2007-05-03 01:11:54 +000043char LiveVariables::ID = 0;
Andrew Trickd3f8fe82012-02-10 04:10:36 +000044char &llvm::LiveVariablesID = LiveVariables::ID;
Owen Anderson8ac477f2010-10-12 19:48:12 +000045INITIALIZE_PASS_BEGIN(LiveVariables, "livevars",
46 "Live Variable Analysis", false, false)
47INITIALIZE_PASS_DEPENDENCY(UnreachableMachineBlockElim)
48INITIALIZE_PASS_END(LiveVariables, "livevars",
Owen Andersondf7a4f22010-10-07 22:25:06 +000049 "Live Variable Analysis", false, false)
Chris Lattnercab0b442003-01-13 20:01:16 +000050
Owen Andersona1022902008-08-04 23:54:43 +000051
52void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
53 AU.addRequiredID(UnreachableMachineBlockElimID);
54 AU.setPreservesAll();
Dan Gohman5ea74d52009-07-31 18:16:33 +000055 MachineFunctionPass::getAnalysisUsage(AU);
Owen Andersona1022902008-08-04 23:54:43 +000056}
57
Jakob Stoklund Olesen4453dc92009-11-10 22:01:05 +000058MachineInstr *
59LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
60 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
61 if (Kills[i]->getParent() == MBB)
62 return Kills[i];
Craig Topperc0196b12014-04-14 00:51:57 +000063 return nullptr;
Jakob Stoklund Olesen4453dc92009-11-10 22:01:05 +000064}
65
Chris Lattnerbe45b5e2006-01-04 05:40:30 +000066void LiveVariables::VarInfo::dump() const {
Manman Ren19f49ac2012-09-11 22:23:19 +000067#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
David Greened599dcd2010-01-04 23:02:10 +000068 dbgs() << " Alive in blocks: ";
Jeffrey Yasskin7d287cb2009-05-26 18:27:15 +000069 for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
70 E = AliveBlocks.end(); I != E; ++I)
David Greened599dcd2010-01-04 23:02:10 +000071 dbgs() << *I << ", ";
72 dbgs() << "\n Killed by:";
Chris Lattnerbe45b5e2006-01-04 05:40:30 +000073 if (Kills.empty())
David Greened599dcd2010-01-04 23:02:10 +000074 dbgs() << " No instructions.\n";
Chris Lattnerbe45b5e2006-01-04 05:40:30 +000075 else {
76 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
David Greened599dcd2010-01-04 23:02:10 +000077 dbgs() << "\n #" << i << ": " << *Kills[i];
78 dbgs() << "\n";
Chris Lattnerbe45b5e2006-01-04 05:40:30 +000079 }
Manman Ren742534c2012-09-06 19:06:06 +000080#endif
Chris Lattnerbe45b5e2006-01-04 05:40:30 +000081}
82
Bill Wendling59cc1592008-02-20 06:10:21 +000083/// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
Chris Lattner584bae42003-05-12 14:24:00 +000084LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
Dan Gohman3a4be0f2008-02-10 18:45:23 +000085 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
Chris Lattner584bae42003-05-12 14:24:00 +000086 "getVarInfo: not a virtual register!");
Jakob Stoklund Olesen28d76692011-01-08 23:10:57 +000087 VirtRegInfo.grow(RegIdx);
Jeffrey Yasskin7d287cb2009-05-26 18:27:15 +000088 return VirtRegInfo[RegIdx];
Chris Lattner584bae42003-05-12 14:24:00 +000089}
90
Owen Anderson897aed92008-01-15 22:58:11 +000091void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
92 MachineBasicBlock *DefBlock,
Evan Cheng9e178722007-05-08 19:00:00 +000093 MachineBasicBlock *MBB,
94 std::vector<MachineBasicBlock*> &WorkList) {
Chris Lattner6c375e42004-07-01 04:29:47 +000095 unsigned BBNum = MBB->getNumber();
Andrew Trick808a7a62012-02-03 05:12:30 +000096
Chris Lattnercab0b442003-01-13 20:01:16 +000097 // Check to see if this basic block is one of the killing blocks. If so,
Bill Wendling59cc1592008-02-20 06:10:21 +000098 // remove it.
Chris Lattnercab0b442003-01-13 20:01:16 +000099 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
Chris Lattneraef6c2a2004-07-19 07:04:55 +0000100 if (VRInfo.Kills[i]->getParent() == MBB) {
Chris Lattnercab0b442003-01-13 20:01:16 +0000101 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
102 break;
103 }
Andrew Trick808a7a62012-02-03 05:12:30 +0000104
Owen Anderson897aed92008-01-15 22:58:11 +0000105 if (MBB == DefBlock) return; // Terminate recursion
Chris Lattnercab0b442003-01-13 20:01:16 +0000106
Jeffrey Yasskin7d287cb2009-05-26 18:27:15 +0000107 if (VRInfo.AliveBlocks.test(BBNum))
Chris Lattnercab0b442003-01-13 20:01:16 +0000108 return; // We already know the block is live
109
110 // Mark the variable known alive in this bb
Jeffrey Yasskin7d287cb2009-05-26 18:27:15 +0000111 VRInfo.AliveBlocks.set(BBNum);
Chris Lattnercab0b442003-01-13 20:01:16 +0000112
Jakob Stoklund Olesen7d544f92012-03-09 23:41:44 +0000113 assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
Benjamin Kramerb8ca01f2011-03-08 17:28:36 +0000114 WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
Chris Lattnercab0b442003-01-13 20:01:16 +0000115}
116
Bill Wendling406fdbd2008-02-20 07:36:31 +0000117void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
Owen Anderson897aed92008-01-15 22:58:11 +0000118 MachineBasicBlock *DefBlock,
Evan Cheng9e178722007-05-08 19:00:00 +0000119 MachineBasicBlock *MBB) {
120 std::vector<MachineBasicBlock*> WorkList;
Owen Anderson897aed92008-01-15 22:58:11 +0000121 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
Bill Wendling406fdbd2008-02-20 07:36:31 +0000122
Evan Cheng9e178722007-05-08 19:00:00 +0000123 while (!WorkList.empty()) {
124 MachineBasicBlock *Pred = WorkList.back();
125 WorkList.pop_back();
Owen Anderson897aed92008-01-15 22:58:11 +0000126 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
Evan Cheng9e178722007-05-08 19:00:00 +0000127 }
128}
129
Owen Anderson1ba66e02008-01-15 22:02:46 +0000130void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
Misha Brukman7d11fbf2004-06-24 21:31:16 +0000131 MachineInstr *MI) {
Evan Chengd8616062008-04-02 18:04:08 +0000132 assert(MRI->getVRegDef(reg) && "Register use before def!");
Alkis Evlogimenos6a099d42004-09-01 22:34:52 +0000133
Owen Anderson9d86ef12007-11-08 01:20:48 +0000134 unsigned BBNum = MBB->getNumber();
135
Owen Anderson1ba66e02008-01-15 22:02:46 +0000136 VarInfo& VRInfo = getVarInfo(reg);
Evan Chengf6f04332007-03-17 09:29:54 +0000137
Bill Wendling59cc1592008-02-20 06:10:21 +0000138 // Check to see if this basic block is already a kill block.
Chris Lattneraef6c2a2004-07-19 07:04:55 +0000139 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
Bill Wendling59cc1592008-02-20 06:10:21 +0000140 // Yes, this register is killed in this basic block already. Increase the
Chris Lattnercab0b442003-01-13 20:01:16 +0000141 // live range by updating the kill instruction.
Chris Lattneraef6c2a2004-07-19 07:04:55 +0000142 VRInfo.Kills.back() = MI;
Chris Lattnercab0b442003-01-13 20:01:16 +0000143 return;
144 }
145
146#ifndef NDEBUG
147 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
Chris Lattneraef6c2a2004-07-19 07:04:55 +0000148 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
Chris Lattnercab0b442003-01-13 20:01:16 +0000149#endif
150
Bill Wendlingc44659b2008-06-23 23:41:14 +0000151 // This situation can occur:
152 //
153 // ,------.
154 // | |
155 // | v
156 // | t2 = phi ... t1 ...
157 // | |
158 // | v
159 // | t1 = ...
160 // | ... = ... t1 ...
161 // | |
162 // `------'
163 //
164 // where there is a use in a PHI node that's a predecessor to the defining
165 // block. We don't want to mark all predecessors as having the value "alive"
166 // in this case.
167 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
Chris Lattnercab0b442003-01-13 20:01:16 +0000168
Bill Wendling59cc1592008-02-20 06:10:21 +0000169 // Add a new kill entry for this basic block. If this virtual register is
170 // already marked as alive in this basic block, that means it is alive in at
171 // least one of the successor blocks, it's not a kill.
Jeffrey Yasskin7d287cb2009-05-26 18:27:15 +0000172 if (!VRInfo.AliveBlocks.test(BBNum))
Evan Chengdf7949a2007-03-09 09:48:56 +0000173 VRInfo.Kills.push_back(MI);
Chris Lattnercab0b442003-01-13 20:01:16 +0000174
Bill Wendling406fdbd2008-02-20 07:36:31 +0000175 // Update all dominating blocks to mark them as "known live".
Chris Lattnerc49a9a52004-05-01 21:24:24 +0000176 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
177 E = MBB->pred_end(); PI != E; ++PI)
Evan Chengd8616062008-04-02 18:04:08 +0000178 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
Chris Lattnercab0b442003-01-13 20:01:16 +0000179}
180
Dan Gohmanae9d9f42008-09-21 21:11:41 +0000181void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
182 VarInfo &VRInfo = getVarInfo(Reg);
183
Jeffrey Yasskin7d287cb2009-05-26 18:27:15 +0000184 if (VRInfo.AliveBlocks.empty())
Dan Gohmanae9d9f42008-09-21 21:11:41 +0000185 // If vr is not alive in any block, then defaults to dead.
186 VRInfo.Kills.push_back(MI);
187}
188
Evan Chenge45b8f82008-04-16 09:46:40 +0000189/// FindLastPartialDef - Return the last partial def of the specified register.
Evan Cheng08d1e412009-09-22 08:34:46 +0000190/// Also returns the sub-registers that're defined by the instruction.
Evan Chenge45b8f82008-04-16 09:46:40 +0000191MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
Evan Cheng08d1e412009-09-22 08:34:46 +0000192 SmallSet<unsigned,4> &PartDefRegs) {
Evan Chenge45b8f82008-04-16 09:46:40 +0000193 unsigned LastDefReg = 0;
194 unsigned LastDefDist = 0;
Craig Topperc0196b12014-04-14 00:51:57 +0000195 MachineInstr *LastDef = nullptr;
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000196 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
197 unsigned SubReg = *SubRegs;
Evan Chenge45b8f82008-04-16 09:46:40 +0000198 MachineInstr *Def = PhysRegDef[SubReg];
199 if (!Def)
200 continue;
201 unsigned Dist = DistanceMap[Def];
202 if (Dist > LastDefDist) {
203 LastDefReg = SubReg;
204 LastDef = Def;
205 LastDefDist = Dist;
206 }
207 }
Evan Cheng08d1e412009-09-22 08:34:46 +0000208
209 if (!LastDef)
Craig Topperc0196b12014-04-14 00:51:57 +0000210 return nullptr;
Evan Cheng08d1e412009-09-22 08:34:46 +0000211
212 PartDefRegs.insert(LastDefReg);
213 for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
214 MachineOperand &MO = LastDef->getOperand(i);
215 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
216 continue;
217 unsigned DefReg = MO.getReg();
218 if (TRI->isSubRegister(Reg, DefReg)) {
Chad Rosierc7505ef2013-05-22 22:26:05 +0000219 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
220 SubRegs.isValid(); ++SubRegs)
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000221 PartDefRegs.insert(*SubRegs);
Evan Cheng08d1e412009-09-22 08:34:46 +0000222 }
223 }
Evan Chenge45b8f82008-04-16 09:46:40 +0000224 return LastDef;
225}
226
Bill Wendlingb9123512008-02-20 09:15:16 +0000227/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
228/// implicit defs to a machine instruction if there was an earlier def of its
229/// super-register.
Chris Lattnercab0b442003-01-13 20:01:16 +0000230void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
Evan Chengd190b822009-11-13 20:36:40 +0000231 MachineInstr *LastDef = PhysRegDef[Reg];
Evan Chenge45b8f82008-04-16 09:46:40 +0000232 // If there was a previous use or a "full" def all is well.
Evan Chengd190b822009-11-13 20:36:40 +0000233 if (!LastDef && !PhysRegUse[Reg]) {
Evan Chenge45b8f82008-04-16 09:46:40 +0000234 // Otherwise, the last sub-register def implicitly defines this register.
235 // e.g.
236 // AH =
237 // AL = ... <imp-def EAX>, <imp-kill AH>
238 // = AH
239 // ...
240 // = EAX
241 // All of the sub-registers must have been defined before the use of Reg!
Evan Cheng08d1e412009-09-22 08:34:46 +0000242 SmallSet<unsigned, 4> PartDefRegs;
243 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
Evan Chenge45b8f82008-04-16 09:46:40 +0000244 // If LastPartialDef is NULL, it must be using a livein register.
245 if (LastPartialDef) {
246 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
247 true/*IsImp*/));
248 PhysRegDef[Reg] = LastPartialDef;
Owen Anderson14738122008-08-14 23:41:38 +0000249 SmallSet<unsigned, 8> Processed;
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000250 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
251 unsigned SubReg = *SubRegs;
Evan Chenge45b8f82008-04-16 09:46:40 +0000252 if (Processed.count(SubReg))
253 continue;
Evan Cheng08d1e412009-09-22 08:34:46 +0000254 if (PartDefRegs.count(SubReg))
Evan Chenge45b8f82008-04-16 09:46:40 +0000255 continue;
256 // This part of Reg was defined before the last partial def. It's killed
257 // here.
258 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
259 false/*IsDef*/,
260 true/*IsImp*/));
261 PhysRegDef[SubReg] = LastPartialDef;
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000262 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
Evan Chenge45b8f82008-04-16 09:46:40 +0000263 Processed.insert(*SS);
264 }
265 }
Evan Cheng6bb95252012-01-14 01:53:46 +0000266 } else if (LastDef && !PhysRegUse[Reg] &&
267 !LastDef->findRegisterDefOperand(Reg))
Evan Chengd190b822009-11-13 20:36:40 +0000268 // Last def defines the super register, add an implicit def of reg.
Evan Cheng6bb95252012-01-14 01:53:46 +0000269 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
270 true/*IsImp*/));
Bill Wendling59cc1592008-02-20 06:10:21 +0000271
Evan Chenge45b8f82008-04-16 09:46:40 +0000272 // Remember this use.
Chad Rosierc7505ef2013-05-22 22:26:05 +0000273 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
274 SubRegs.isValid(); ++SubRegs)
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000275 PhysRegUse[*SubRegs] = MI;
Evan Chengd8417d92007-06-26 21:03:35 +0000276}
277
Evan Cheng1d31fc92009-12-01 00:44:45 +0000278/// FindLastRefOrPartRef - Return the last reference or partial reference of
279/// the specified register.
280MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
281 MachineInstr *LastDef = PhysRegDef[Reg];
282 MachineInstr *LastUse = PhysRegUse[Reg];
283 if (!LastDef && !LastUse)
Craig Topperc0196b12014-04-14 00:51:57 +0000284 return nullptr;
Evan Cheng1d31fc92009-12-01 00:44:45 +0000285
286 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
287 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
Evan Cheng1d31fc92009-12-01 00:44:45 +0000288 unsigned LastPartDefDist = 0;
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000289 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
290 unsigned SubReg = *SubRegs;
Evan Cheng1d31fc92009-12-01 00:44:45 +0000291 MachineInstr *Def = PhysRegDef[SubReg];
292 if (Def && Def != LastDef) {
293 // There was a def of this sub-register in between. This is a partial
294 // def, keep track of the last one.
295 unsigned Dist = DistanceMap[Def];
Benjamin Kramerd64b9522010-01-07 17:29:08 +0000296 if (Dist > LastPartDefDist)
Evan Cheng1d31fc92009-12-01 00:44:45 +0000297 LastPartDefDist = Dist;
Benjamin Kramerd64b9522010-01-07 17:29:08 +0000298 } else if (MachineInstr *Use = PhysRegUse[SubReg]) {
Evan Cheng1d31fc92009-12-01 00:44:45 +0000299 unsigned Dist = DistanceMap[Use];
300 if (Dist > LastRefOrPartRefDist) {
301 LastRefOrPartRefDist = Dist;
302 LastRefOrPartRef = Use;
303 }
304 }
305 }
306
307 return LastRefOrPartRef;
308}
309
Evan Chengf1e873a2009-01-20 21:25:12 +0000310bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
Evan Chenga21aac32009-09-24 02:15:22 +0000311 MachineInstr *LastDef = PhysRegDef[Reg];
312 MachineInstr *LastUse = PhysRegUse[Reg];
313 if (!LastDef && !LastUse)
Evan Chenge45b8f82008-04-16 09:46:40 +0000314 return false;
315
Evan Chenga21aac32009-09-24 02:15:22 +0000316 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
Evan Chenge45b8f82008-04-16 09:46:40 +0000317 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
318 // The whole register is used.
319 // AL =
320 // AH =
321 //
322 // = AX
323 // = AL, AX<imp-use, kill>
324 // AX =
325 //
326 // Or whole register is defined, but not used at all.
327 // AX<dead> =
328 // ...
329 // AX =
330 //
331 // Or whole register is defined, but only partly used.
332 // AX<dead> = AL<imp-def>
333 // = AL<kill>
Andrew Trick808a7a62012-02-03 05:12:30 +0000334 // AX =
Craig Topperc0196b12014-04-14 00:51:57 +0000335 MachineInstr *LastPartDef = nullptr;
Evan Chenga21aac32009-09-24 02:15:22 +0000336 unsigned LastPartDefDist = 0;
Owen Anderson14738122008-08-14 23:41:38 +0000337 SmallSet<unsigned, 8> PartUses;
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000338 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
339 unsigned SubReg = *SubRegs;
Evan Chenga21aac32009-09-24 02:15:22 +0000340 MachineInstr *Def = PhysRegDef[SubReg];
341 if (Def && Def != LastDef) {
342 // There was a def of this sub-register in between. This is a partial
343 // def, keep track of the last one.
344 unsigned Dist = DistanceMap[Def];
345 if (Dist > LastPartDefDist) {
346 LastPartDefDist = Dist;
347 LastPartDef = Def;
348 }
349 continue;
350 }
Evan Chenge45b8f82008-04-16 09:46:40 +0000351 if (MachineInstr *Use = PhysRegUse[SubReg]) {
Chad Rosierc7505ef2013-05-22 22:26:05 +0000352 for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true); SS.isValid();
353 ++SS)
Evan Chenge45b8f82008-04-16 09:46:40 +0000354 PartUses.insert(*SS);
355 unsigned Dist = DistanceMap[Use];
356 if (Dist > LastRefOrPartRefDist) {
357 LastRefOrPartRefDist = Dist;
358 LastRefOrPartRef = Use;
Evan Chengd8417d92007-06-26 21:03:35 +0000359 }
Evan Chenge45b8f82008-04-16 09:46:40 +0000360 }
361 }
Evan Chengf1e873a2009-01-20 21:25:12 +0000362
Jakob Stoklund Olesen2664d292010-03-05 21:49:17 +0000363 if (!PhysRegUse[Reg]) {
Evan Chenga21aac32009-09-24 02:15:22 +0000364 // Partial uses. Mark register def dead and add implicit def of
365 // sub-registers which are used.
366 // EAX<dead> = op AL<imp-def>
367 // That is, EAX def is dead but AL def extends pass it.
Evan Chenge45b8f82008-04-16 09:46:40 +0000368 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000369 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
370 unsigned SubReg = *SubRegs;
Evan Chenga21aac32009-09-24 02:15:22 +0000371 if (!PartUses.count(SubReg))
372 continue;
373 bool NeedDef = true;
374 if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
375 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
376 if (MO) {
377 NeedDef = false;
378 assert(!MO->isDead());
Evan Chengba2410b2009-07-06 21:34:05 +0000379 }
Evan Chenge45b8f82008-04-16 09:46:40 +0000380 }
Evan Chenga21aac32009-09-24 02:15:22 +0000381 if (NeedDef)
382 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
383 true/*IsDef*/, true/*IsImp*/));
Evan Cheng1d31fc92009-12-01 00:44:45 +0000384 MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
385 if (LastSubRef)
386 LastSubRef->addRegisterKilled(SubReg, TRI, true);
387 else {
388 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
Chad Rosierc7505ef2013-05-22 22:26:05 +0000389 for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true);
390 SS.isValid(); ++SS)
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000391 PhysRegUse[*SS] = LastRefOrPartRef;
Evan Cheng1d31fc92009-12-01 00:44:45 +0000392 }
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000393 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
Evan Chenga21aac32009-09-24 02:15:22 +0000394 PartUses.erase(*SS);
Evan Chenge45b8f82008-04-16 09:46:40 +0000395 }
Jakob Stoklund Olesen2664d292010-03-05 21:49:17 +0000396 } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
397 if (LastPartDef)
398 // The last partial def kills the register.
399 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
400 true/*IsImp*/, true/*IsKill*/));
401 else {
402 MachineOperand *MO =
403 LastRefOrPartRef->findRegisterDefOperand(Reg, false, TRI);
404 bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
405 // If the last reference is the last def, then it's not used at all.
406 // That is, unless we are currently processing the last reference itself.
407 LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
408 if (NeedEC) {
409 // If we are adding a subreg def and the superreg def is marked early
410 // clobber, add an early clobber marker to the subreg def.
411 MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
412 if (MO)
413 MO->setIsEarlyClobber();
414 }
415 }
Evan Chenga21aac32009-09-24 02:15:22 +0000416 } else
Evan Chenge45b8f82008-04-16 09:46:40 +0000417 LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
418 return true;
419}
420
Jakob Stoklund Olesen8e3bb312012-01-21 00:58:53 +0000421void LiveVariables::HandleRegMask(const MachineOperand &MO) {
422 // Call HandlePhysRegKill() for all live registers clobbered by Mask.
423 // Clobbered registers are always dead, sp there is no need to use
424 // HandlePhysRegDef().
425 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
426 // Skip dead regs.
427 if (!PhysRegDef[Reg] && !PhysRegUse[Reg])
428 continue;
429 // Skip mask-preserved regs.
Evan Cheng64a2bec2012-01-21 03:31:03 +0000430 if (!MO.clobbersPhysReg(Reg))
Jakob Stoklund Olesen8e3bb312012-01-21 00:58:53 +0000431 continue;
432 // Kill the largest clobbered super-register.
433 // This avoids needless implicit operands.
434 unsigned Super = Reg;
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000435 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
Jakob Stoklund Olesen8e3bb312012-01-21 00:58:53 +0000436 if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
437 Super = *SR;
Craig Topperc0196b12014-04-14 00:51:57 +0000438 HandlePhysRegKill(Super, nullptr);
Jakob Stoklund Olesen8e3bb312012-01-21 00:58:53 +0000439 }
440}
441
Evan Cheng262f86e2009-09-23 06:28:31 +0000442void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
Craig Topper2cd5ff82013-07-11 16:22:38 +0000443 SmallVectorImpl<unsigned> &Defs) {
Evan Chenge45b8f82008-04-16 09:46:40 +0000444 // What parts of the register are previously defined?
Owen Anderson413f7d92008-06-27 07:05:59 +0000445 SmallSet<unsigned, 32> Live;
Evan Chenge45b8f82008-04-16 09:46:40 +0000446 if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
Chad Rosierc7505ef2013-05-22 22:26:05 +0000447 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
448 SubRegs.isValid(); ++SubRegs)
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000449 Live.insert(*SubRegs);
Evan Chenge45b8f82008-04-16 09:46:40 +0000450 } else {
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000451 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
452 unsigned SubReg = *SubRegs;
Evan Chenge45b8f82008-04-16 09:46:40 +0000453 // If a register isn't itself defined, but all parts that make up of it
454 // are defined, then consider it also defined.
455 // e.g.
456 // AL =
457 // AH =
458 // = AX
Evan Chenga21aac32009-09-24 02:15:22 +0000459 if (Live.count(SubReg))
460 continue;
Evan Chenge45b8f82008-04-16 09:46:40 +0000461 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
Chad Rosierc7505ef2013-05-22 22:26:05 +0000462 for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true);
463 SS.isValid(); ++SS)
Evan Chenge45b8f82008-04-16 09:46:40 +0000464 Live.insert(*SS);
465 }
Bill Wendling406fdbd2008-02-20 07:36:31 +0000466 }
Chris Lattnercab0b442003-01-13 20:01:16 +0000467 }
Alkis Evlogimenosebbd66c2004-01-13 06:24:30 +0000468
Evan Chenge45b8f82008-04-16 09:46:40 +0000469 // Start from the largest piece, find the last time any part of the register
470 // is referenced.
Evan Chenga21aac32009-09-24 02:15:22 +0000471 HandlePhysRegKill(Reg, MI);
472 // Only some of the sub-registers are used.
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000473 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
474 unsigned SubReg = *SubRegs;
Evan Chenga21aac32009-09-24 02:15:22 +0000475 if (!Live.count(SubReg))
476 // Skip if this sub-register isn't defined.
477 continue;
478 HandlePhysRegKill(SubReg, MI);
Evan Cheng7818c032007-04-25 07:30:23 +0000479 }
480
Evan Chenga21aac32009-09-24 02:15:22 +0000481 if (MI)
482 Defs.push_back(Reg); // Remember this def.
Evan Cheng262f86e2009-09-23 06:28:31 +0000483}
484
485void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
Craig Topper2cd5ff82013-07-11 16:22:38 +0000486 SmallVectorImpl<unsigned> &Defs) {
Evan Cheng262f86e2009-09-23 06:28:31 +0000487 while (!Defs.empty()) {
488 unsigned Reg = Defs.back();
489 Defs.pop_back();
Chad Rosierc7505ef2013-05-22 22:26:05 +0000490 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
491 SubRegs.isValid(); ++SubRegs) {
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000492 unsigned SubReg = *SubRegs;
Evan Chenge45b8f82008-04-16 09:46:40 +0000493 PhysRegDef[SubReg] = MI;
Craig Topperc0196b12014-04-14 00:51:57 +0000494 PhysRegUse[SubReg] = nullptr;
Evan Chengd8417d92007-06-26 21:03:35 +0000495 }
Alkis Evlogimenosebbd66c2004-01-13 06:24:30 +0000496 }
Chris Lattnercab0b442003-01-13 20:01:16 +0000497}
498
Dylan Noblesmith6e699272014-08-25 01:59:49 +0000499void LiveVariables::runOnInstr(MachineInstr *MI,
500 SmallVectorImpl<unsigned> &Defs) {
501 assert(!MI->isDebugValue());
502 // Process all of the operands of the instruction...
503 unsigned NumOperandsToProcess = MI->getNumOperands();
504
505 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
506 // of the uses. They will be handled in other basic blocks.
507 if (MI->isPHI())
508 NumOperandsToProcess = 1;
509
510 // Clear kill and dead markers. LV will recompute them.
511 SmallVector<unsigned, 4> UseRegs;
512 SmallVector<unsigned, 4> DefRegs;
513 SmallVector<unsigned, 1> RegMasks;
514 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
515 MachineOperand &MO = MI->getOperand(i);
516 if (MO.isRegMask()) {
517 RegMasks.push_back(i);
518 continue;
519 }
520 if (!MO.isReg() || MO.getReg() == 0)
521 continue;
522 unsigned MOReg = MO.getReg();
523 if (MO.isUse()) {
524 MO.setIsKill(false);
525 if (MO.readsReg())
526 UseRegs.push_back(MOReg);
527 } else /*MO.isDef()*/ {
528 MO.setIsDead(false);
529 DefRegs.push_back(MOReg);
530 }
531 }
532
533 MachineBasicBlock *MBB = MI->getParent();
534 // Process all uses.
535 for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
536 unsigned MOReg = UseRegs[i];
537 if (TargetRegisterInfo::isVirtualRegister(MOReg))
538 HandleVirtRegUse(MOReg, MBB, MI);
539 else if (!MRI->isReserved(MOReg))
540 HandlePhysRegUse(MOReg, MI);
541 }
542
543 // Process all masked registers. (Call clobbers).
544 for (unsigned i = 0, e = RegMasks.size(); i != e; ++i)
545 HandleRegMask(MI->getOperand(RegMasks[i]));
546
547 // Process all defs.
548 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
549 unsigned MOReg = DefRegs[i];
550 if (TargetRegisterInfo::isVirtualRegister(MOReg))
551 HandleVirtRegDef(MOReg, MI);
552 else if (!MRI->isReserved(MOReg))
553 HandlePhysRegDef(MOReg, MI, Defs);
554 }
555 UpdatePhysRegDefs(MI, Defs);
556}
557
558void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
559 // Mark live-in registers as live-in.
560 SmallVector<unsigned, 4> Defs;
561 for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
562 EE = MBB->livein_end(); II != EE; ++II) {
563 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
564 "Cannot have a live-in virtual register!");
565 HandlePhysRegDef(*II, nullptr, Defs);
566 }
567
568 // Loop over all of the instructions, processing them.
569 DistanceMap.clear();
570 unsigned Dist = 0;
571 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
572 I != E; ++I) {
573 MachineInstr *MI = I;
574 if (MI->isDebugValue())
575 continue;
576 DistanceMap.insert(std::make_pair(MI, Dist++));
577
578 runOnInstr(MI, Defs);
579 }
580
581 // Handle any virtual assignments from PHI nodes which might be at the
582 // bottom of this basic block. We check all of our successor blocks to see
583 // if they have PHI nodes, and if so, we simulate an assignment at the end
584 // of the current block.
585 if (!PHIVarInfo[MBB->getNumber()].empty()) {
586 SmallVectorImpl<unsigned> &VarInfoVec = PHIVarInfo[MBB->getNumber()];
587
588 for (SmallVectorImpl<unsigned>::iterator I = VarInfoVec.begin(),
589 E = VarInfoVec.end(); I != E; ++I)
590 // Mark it alive only in the block we are representing.
591 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
592 MBB);
593 }
594
595 // MachineCSE may CSE instructions which write to non-allocatable physical
596 // registers across MBBs. Remember if any reserved register is liveout.
597 SmallSet<unsigned, 4> LiveOuts;
598 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
599 SE = MBB->succ_end(); SI != SE; ++SI) {
600 MachineBasicBlock *SuccMBB = *SI;
601 if (SuccMBB->isLandingPad())
602 continue;
603 for (MachineBasicBlock::livein_iterator LI = SuccMBB->livein_begin(),
604 LE = SuccMBB->livein_end(); LI != LE; ++LI) {
605 unsigned LReg = *LI;
606 if (!TRI->isInAllocatableClass(LReg))
607 // Ignore other live-ins, e.g. those that are live into landing pads.
608 LiveOuts.insert(LReg);
609 }
610 }
611
612 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
613 // available at the end of the basic block.
614 for (unsigned i = 0; i != NumRegs; ++i)
615 if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))
616 HandlePhysRegDef(i, nullptr, Defs);
617}
618
Evan Chengf6f04332007-03-17 09:29:54 +0000619bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
620 MF = &mf;
Evan Chengd8616062008-04-02 18:04:08 +0000621 MRI = &mf.getRegInfo();
Eric Christopherfc6de422014-08-05 02:39:49 +0000622 TRI = MF->getSubtarget().getRegisterInfo();
Chris Lattner26407382004-02-09 01:35:21 +0000623
Dylan Noblesmith46a922c2014-08-25 01:59:42 +0000624 const unsigned NumRegs = TRI->getNumRegs();
Dylan Noblesmith17f05a32014-08-26 02:03:25 +0000625 PhysRegDef.assign(NumRegs, nullptr);
626 PhysRegUse.assign(NumRegs, nullptr);
Dylan Noblesmith46a922c2014-08-25 01:59:42 +0000627 PHIVarInfo.resize(MF->getNumBlockIDs());
Jakob Stoklund Olesen38b76e22010-02-23 22:43:58 +0000628 PHIJoins.clear();
Chris Lattnercab0b442003-01-13 20:01:16 +0000629
Andrew Trickd3f8fe82012-02-10 04:10:36 +0000630 // FIXME: LiveIntervals will be updated to remove its dependence on
631 // LiveVariables to improve compilation time and eliminate bizarre pass
632 // dependencies. Until then, we can't change much in -O0.
633 if (!MRI->isSSA())
634 report_fatal_error("regalloc=... not currently supported with -O0");
635
Evan Chengf6f04332007-03-17 09:29:54 +0000636 analyzePHINodes(mf);
Bill Wendling984f0ce2006-10-03 07:20:20 +0000637
Chris Lattnercab0b442003-01-13 20:01:16 +0000638 // Calculate live variable information in depth first order on the CFG of the
639 // function. This guarantees that we will see the definition of a virtual
640 // register before its uses due to dominance properties of SSA (except for PHI
641 // nodes, which are treated as a special case).
Evan Chengf6f04332007-03-17 09:29:54 +0000642 MachineBasicBlock *Entry = MF->begin();
Evan Chenge66f8222007-06-27 05:23:00 +0000643 SmallPtrSet<MachineBasicBlock*,16> Visited;
Bill Wendlingb9123512008-02-20 09:15:16 +0000644
Craig Topper46276792014-08-24 23:23:06 +0000645 for (MachineBasicBlock *MBB : depth_first_ext(Entry, Visited)) {
Dylan Noblesmith6e699272014-08-25 01:59:49 +0000646 runOnBlock(MBB, NumRegs);
Evan Cheng7818c032007-04-25 07:30:23 +0000647
Dylan Noblesmith17f05a32014-08-26 02:03:25 +0000648 PhysRegDef.assign(NumRegs, nullptr);
649 PhysRegUse.assign(NumRegs, nullptr);
Chris Lattnercab0b442003-01-13 20:01:16 +0000650 }
651
Evan Cheng70ec5282006-11-15 20:51:59 +0000652 // Convert and transfer the dead / killed information we have gathered into
653 // VirtRegInfo onto MI's.
Jakob Stoklund Olesen28d76692011-01-08 23:10:57 +0000654 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
655 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
656 for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
657 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
658 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
Chris Lattnercab0b442003-01-13 20:01:16 +0000659 else
Jakob Stoklund Olesen28d76692011-01-08 23:10:57 +0000660 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
661 }
Chris Lattner7c77fd52004-07-01 04:24:29 +0000662
Chris Lattnerd47909e2004-07-09 16:44:37 +0000663 // Check to make sure there are no unreachable blocks in the MC CFG for the
664 // function. If so, it is due to a bug in the instruction selector or some
665 // other part of the code generator if this happens.
666#ifndef NDEBUG
Evan Chengf6f04332007-03-17 09:29:54 +0000667 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
Chris Lattnerd47909e2004-07-09 16:44:37 +0000668 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
669#endif
670
Dylan Noblesmith46a922c2014-08-25 01:59:42 +0000671 PhysRegDef.clear();
672 PhysRegUse.clear();
673 PHIVarInfo.clear();
Evan Cheng0fbe14a2007-04-25 19:34:00 +0000674
Chris Lattnercab0b442003-01-13 20:01:16 +0000675 return false;
676}
Chris Lattnerafa9d7e2004-02-19 18:28:02 +0000677
Evan Cheng7a265d82008-07-03 00:07:19 +0000678/// replaceKillInstruction - Update register kill info by replacing a kill
679/// instruction with a new one.
680void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
681 MachineInstr *NewMI) {
682 VarInfo &VI = getVarInfo(Reg);
Evan Cheng9f8b66f2008-07-03 00:28:27 +0000683 std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
Evan Cheng7a265d82008-07-03 00:07:19 +0000684}
685
Chris Lattnerf8f724a2006-09-03 00:05:09 +0000686/// removeVirtualRegistersKilled - Remove all killed info for the specified
687/// instruction.
688void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
Evan Cheng70ec5282006-11-15 20:51:59 +0000689 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
690 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000691 if (MO.isReg() && MO.isKill()) {
Chris Lattner60055892007-12-30 21:56:09 +0000692 MO.setIsKill(false);
Evan Cheng70ec5282006-11-15 20:51:59 +0000693 unsigned Reg = MO.getReg();
Dan Gohman3a4be0f2008-02-10 18:45:23 +0000694 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
Evan Cheng70ec5282006-11-15 20:51:59 +0000695 bool removed = getVarInfo(Reg).removeKill(MI);
696 assert(removed && "kill not in register's VarInfo?");
Duncan Sandsa41634e2011-08-12 14:54:45 +0000697 (void)removed;
Evan Cheng70ec5282006-11-15 20:51:59 +0000698 }
Chris Lattnerf8f724a2006-09-03 00:05:09 +0000699 }
700 }
Chris Lattnerf8f724a2006-09-03 00:05:09 +0000701}
702
Bill Wendling984f0ce2006-10-03 07:20:20 +0000703/// analyzePHINodes - Gather information about the PHI nodes in here. In
Bill Wendlingb9123512008-02-20 09:15:16 +0000704/// particular, we want to map the variable information of a virtual register
705/// which is used in a PHI node. We map that to the BB the vreg is coming from.
Bill Wendling984f0ce2006-10-03 07:20:20 +0000706///
707void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
Alexey Samsonov41b977d2014-04-30 18:29:51 +0000708 for (const auto &MBB : Fn)
Alexey Samsonovf74bde62014-04-30 22:17:38 +0000709 for (const auto &BBI : MBB) {
710 if (!BBI.isPHI())
711 break;
712 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
713 if (BBI.getOperand(i).readsReg())
714 PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()]
715 .push_back(BBI.getOperand(i).getReg());
716 }
Bill Wendling984f0ce2006-10-03 07:20:20 +0000717}
Jakob Stoklund Olesen4453dc92009-11-10 22:01:05 +0000718
Jakob Stoklund Olesenbc630ac2009-11-21 02:05:21 +0000719bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
720 unsigned Reg,
721 MachineRegisterInfo &MRI) {
722 unsigned Num = MBB.getNumber();
723
724 // Reg is live-through.
725 if (AliveBlocks.test(Num))
726 return true;
727
728 // Registers defined in MBB cannot be live in.
729 const MachineInstr *Def = MRI.getVRegDef(Reg);
730 if (Def && Def->getParent() == &MBB)
731 return false;
732
733 // Reg was not defined in MBB, was it killed here?
734 return findKill(&MBB);
735}
736
Jakob Stoklund Olesendefc4702009-12-01 17:13:31 +0000737bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) {
738 LiveVariables::VarInfo &VI = getVarInfo(Reg);
739
740 // Loop over all of the successors of the basic block, checking to see if
741 // the value is either live in the block, or if it is killed in the block.
Benjamin Kramerb8ca01f2011-03-08 17:28:36 +0000742 SmallVector<MachineBasicBlock*, 8> OpSuccBlocks;
Jakob Stoklund Olesendefc4702009-12-01 17:13:31 +0000743 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
744 E = MBB.succ_end(); SI != E; ++SI) {
745 MachineBasicBlock *SuccMBB = *SI;
746
747 // Is it alive in this successor?
748 unsigned SuccIdx = SuccMBB->getNumber();
749 if (VI.AliveBlocks.test(SuccIdx))
750 return true;
751 OpSuccBlocks.push_back(SuccMBB);
752 }
753
754 // Check to see if this value is live because there is a use in a successor
755 // that kills it.
756 switch (OpSuccBlocks.size()) {
757 case 1: {
758 MachineBasicBlock *SuccMBB = OpSuccBlocks[0];
759 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
760 if (VI.Kills[i]->getParent() == SuccMBB)
761 return true;
762 break;
763 }
764 case 2: {
765 MachineBasicBlock *SuccMBB1 = OpSuccBlocks[0], *SuccMBB2 = OpSuccBlocks[1];
766 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
767 if (VI.Kills[i]->getParent() == SuccMBB1 ||
768 VI.Kills[i]->getParent() == SuccMBB2)
769 return true;
770 break;
771 }
772 default:
773 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
774 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
775 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
776 VI.Kills[i]->getParent()))
777 return true;
778 }
779 return false;
780}
781
Jakob Stoklund Olesen4f7fd3b2009-11-11 19:31:31 +0000782/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
783/// variables that are live out of DomBB will be marked as passing live through
784/// BB.
785void LiveVariables::addNewBlock(MachineBasicBlock *BB,
Jakob Stoklund Olesenbc630ac2009-11-21 02:05:21 +0000786 MachineBasicBlock *DomBB,
787 MachineBasicBlock *SuccBB) {
Jakob Stoklund Olesen4f7fd3b2009-11-11 19:31:31 +0000788 const unsigned NumNew = BB->getNumber();
Jakob Stoklund Olesenbc630ac2009-11-21 02:05:21 +0000789
Benjamin Kramer851c9412012-09-09 11:56:14 +0000790 SmallSet<unsigned, 16> Defs, Kills;
791
792 MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end();
793 for (; BBI != BBE && BBI->isPHI(); ++BBI) {
794 // Record the def of the PHI node.
795 Defs.insert(BBI->getOperand(0).getReg());
796
797 // All registers used by PHI nodes in SuccBB must be live through BB.
Jakob Stoklund Olesenbc630ac2009-11-21 02:05:21 +0000798 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
799 if (BBI->getOperand(i+1).getMBB() == BB)
800 getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
Benjamin Kramer851c9412012-09-09 11:56:14 +0000801 }
802
803 // Record all vreg defs and kills of all instructions in SuccBB.
804 for (; BBI != BBE; ++BBI) {
805 for (MachineInstr::mop_iterator I = BBI->operands_begin(),
806 E = BBI->operands_end(); I != E; ++I) {
807 if (I->isReg() && TargetRegisterInfo::isVirtualRegister(I->getReg())) {
808 if (I->isDef())
809 Defs.insert(I->getReg());
810 else if (I->isKill())
811 Kills.insert(I->getReg());
812 }
813 }
814 }
Jakob Stoklund Olesen4453dc92009-11-10 22:01:05 +0000815
816 // Update info for all live variables
Jakob Stoklund Olesen28d76692011-01-08 23:10:57 +0000817 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
818 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
Benjamin Kramer851c9412012-09-09 11:56:14 +0000819
820 // If the Defs is defined in the successor it can't be live in BB.
821 if (Defs.count(Reg))
822 continue;
823
824 // If the register is either killed in or live through SuccBB it's also live
825 // through BB.
Jakob Stoklund Olesen4f7fd3b2009-11-11 19:31:31 +0000826 VarInfo &VI = getVarInfo(Reg);
Benjamin Kramer851c9412012-09-09 11:56:14 +0000827 if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))
Jakob Stoklund Olesen4f7fd3b2009-11-11 19:31:31 +0000828 VI.AliveBlocks.set(NumNew);
Jakob Stoklund Olesen4453dc92009-11-10 22:01:05 +0000829 }
830}