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gerrit-public.fairphone.software / toolchain / llvm-project / a8682554c6662ce01853d0069afb6c5b4ef8ab55 / . / llvm / lib / Support / X86TargetParser.cpp
blob: 1e8569bcd540a703ec9b77482622213ae8e40b2b [file] [log] [blame]
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/Support/X86TargetParser.h"
14#include "llvm/ADT/StringSwitch.h"
15#include "llvm/ADT/Triple.h"
16
17using namespace llvm;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]18using namespace llvm::X86;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]19
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]20namespace {
21
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]22/// Container class for CPU features.
23/// This is a constexpr reimplementation of a subset of std::bitset. It would be
24/// nice to use std::bitset directly, but it doesn't support constant
25/// initialization.
26class FeatureBitset {
27 static constexpr unsigned NUM_FEATURE_WORDS =
28 (X86::CPU_FEATURE_MAX + 31) / 32;
29
30 // This cannot be a std::array, operator[] is not constexpr until C++17.
31 uint32_t Bits[NUM_FEATURE_WORDS] = {};
32
33public:
34 constexpr FeatureBitset() = default;
35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36 for (auto I : Init)
37 set(I);
38 }
39
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]40 bool any() const {
41 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
42 }
43
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]44 constexpr FeatureBitset &set(unsigned I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]45 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]46 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
47 Bits[I / 32] = NewBits;
48 return *this;
49 }
50
51 constexpr bool operator[](unsigned I) const {
52 uint32_t Mask = uint32_t(1) << (I % 32);
53 return (Bits[I / 32] & Mask) != 0;
54 }
55
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]56 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
57 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
58 // GCC <6.2 crashes if this is written in a single statement.
59 uint32_t NewBits = Bits[I] & RHS.Bits[I];
60 Bits[I] = NewBits;
61 }
62 return *this;
63 }
64
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]65 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
66 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]67 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]68 uint32_t NewBits = Bits[I] | RHS.Bits[I];
69 Bits[I] = NewBits;
70 }
71 return *this;
72 }
73
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]74 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]75 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]76 FeatureBitset Result;
77 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
78 Result.Bits[I] = Bits[I] & RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]79 return Result;
80 }
81
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]82 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]83 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]84 FeatureBitset Result;
85 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
86 Result.Bits[I] = Bits[I] | RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]87 return Result;
88 }
89
90 constexpr FeatureBitset operator~() const {
91 FeatureBitset Result;
92 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
93 Result.Bits[I] = ~Bits[I];
94 return Result;
95 }
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]96
97 constexpr bool operator!=(const FeatureBitset &RHS) const {
98 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
99 if (Bits[I] != RHS.Bits[I])
100 return true;
101 return false;
102 }
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]103};
104
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]105struct ProcInfo {
106 StringLiteral Name;
107 X86::CPUKind Kind;
108 unsigned KeyFeature;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]109 FeatureBitset Features;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]110};
111
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]112struct FeatureInfo {
113 StringLiteral Name;
114 FeatureBitset ImpliedFeatures;
115};
116
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]117} // end anonymous namespace
118
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]119#define X86_FEATURE(ENUM, STRING) \
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]120 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]121#include "llvm/Support/X86TargetParser.def"
122
123// Pentium with MMX.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]124constexpr FeatureBitset FeaturesPentiumMMX =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]125 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
126
127// Pentium 2 and 3.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]128constexpr FeatureBitset FeaturesPentium2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]129 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]130constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]131
132// Pentium 4 CPUs
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]133constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
134constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
135constexpr FeatureBitset FeaturesNocona =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]136 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]137
138// Basic 64-bit capable CPU.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]139constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]140
141// Intel Core CPUs
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]142constexpr FeatureBitset FeaturesCore2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]143 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]144constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
145constexpr FeatureBitset FeaturesNehalem =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]146 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]147constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
148constexpr FeatureBitset FeaturesSandyBridge =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]149 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]150constexpr FeatureBitset FeaturesIvyBridge =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]151 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]152constexpr FeatureBitset FeaturesHaswell =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]153 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
154 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]155constexpr FeatureBitset FeaturesBroadwell =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]156 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
157
158// Intel Knights Landing and Knights Mill
159// Knights Landing has feature parity with Broadwell.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]160constexpr FeatureBitset FeaturesKNL =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]161 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
162 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]163constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]164
165// Intel Skylake processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]166constexpr FeatureBitset FeaturesSkylakeClient =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]167 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
168 FeatureXSAVES | FeatureSGX;
169// SkylakeServer inherits all SkylakeClient features except SGX.
170// FIXME: That doesn't match gcc.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]171constexpr FeatureBitset FeaturesSkylakeServer =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]172 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
173 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
174 FeaturePKU;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]175constexpr FeatureBitset FeaturesCascadeLake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]176 FeaturesSkylakeServer | FeatureAVX512VNNI;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]177constexpr FeatureBitset FeaturesCooperLake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]178 FeaturesCascadeLake | FeatureAVX512BF16;
179
180// Intel 10nm processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]181constexpr FeatureBitset FeaturesCannonlake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]182 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
183 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
184 FeaturePKU | FeatureSHA;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]185constexpr FeatureBitset FeaturesICLClient =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]186 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
187 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
188 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]189constexpr FeatureBitset FeaturesICLServer =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]190 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]191constexpr FeatureBitset FeaturesTigerlake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]192 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]193 FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]194constexpr FeatureBitset FeaturesSapphireRapids =
Freddy Yee02d0812020-08-25 12:27:02 +0800[diff] [blame]195 FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]196 FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE |
197 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
198 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]199
200// Intel Atom processors.
201// Bonnell has feature parity with Core2 and adds MOVBE.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]202constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]203// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]204constexpr FeatureBitset FeaturesSilvermont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]205 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]206constexpr FeatureBitset FeaturesGoldmont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]207 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
208 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
209 FeatureXSAVEOPT | FeatureXSAVES;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]210constexpr FeatureBitset FeaturesGoldmontPlus =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]211 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]212constexpr FeatureBitset FeaturesTremont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]213 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
214
215// Geode Processor.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]216constexpr FeatureBitset FeaturesGeode =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]217 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
218
219// K6 processor.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]220constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]221
222// K7 and K8 architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]223constexpr FeatureBitset FeaturesAthlon =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]224 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]225constexpr FeatureBitset FeaturesAthlonXP =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]226 FeaturesAthlon | FeatureFXSR | FeatureSSE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]227constexpr FeatureBitset FeaturesK8 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]228 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]229constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
230constexpr FeatureBitset FeaturesAMDFAM10 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]231 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]232 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]233
234// Bobcat architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]235constexpr FeatureBitset FeaturesBTVER1 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]236 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]237 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]238 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]239 FeatureSAHF;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]240constexpr FeatureBitset FeaturesBTVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]241 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
242 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
243
244// AMD Bulldozer architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]245constexpr FeatureBitset FeaturesBDVER1 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]246 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]247 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]248 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
249 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]250 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]251constexpr FeatureBitset FeaturesBDVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]252 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]253constexpr FeatureBitset FeaturesBDVER3 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]254 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]255constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
256 FeatureBMI2 | FeatureMOVBE |
257 FeatureMWAITX | FeatureRDRND;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]258
259// AMD Zen architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]260constexpr FeatureBitset FeaturesZNVER1 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]261 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
262 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]263 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]264 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
265 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
266 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
267 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]268 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]269 FeatureXSAVEOPT | FeatureXSAVES;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]270constexpr FeatureBitset FeaturesZNVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]271 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]272
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]273constexpr ProcInfo Processors[] = {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]274 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
275 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]276 // i386-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]277 { {"i386"}, CK_i386, ~0U, FeatureX87 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]278 // i486-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]279 { {"i486"}, CK_i486, ~0U, FeatureX87 },
280 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
281 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
282 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]283 // i586-generation processors, P5 microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]284 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
285 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
286 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]287 // i686-generation processors, P6 / Pentium M microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]288 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
289 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
290 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
291 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
292 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
293 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
294 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
295 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]296 // Netburst microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]297 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
298 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
299 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
300 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]301 // Core microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]302 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
303 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]304 // Atom processors
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]305 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
306 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
307 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
308 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
309 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
310 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
311 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]312 // Nehalem microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]313 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
314 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]315 // Westmere microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]316 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]317 // Sandy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]318 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
319 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]320 // Ivy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]321 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
322 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]323 // Haswell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]324 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
325 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]326 // Broadwell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]327 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]328 // Skylake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]329 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]330 // Skylake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]331 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
332 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]333 // Cascadelake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]334 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]335 // Cooperlake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]336 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]337 // Cannonlake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]338 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]339 // Icelake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]340 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]341 // Icelake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]342 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]343 // Tigerlake microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]344 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
Freddy Yee02d0812020-08-25 12:27:02 +0800[diff] [blame]345 // Sapphire Rapids microarchitecture based processors.
346 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]347 // Knights Landing processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]348 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]349 // Knights Mill processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]350 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]351 // Lakemont microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]352 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]353 // K6 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]354 { {"k6"}, CK_K6, ~0U, FeaturesK6 },
355 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
356 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]357 // K7 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]358 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
359 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
360 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
361 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
362 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]363 // K8 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]364 { {"k8"}, CK_K8, ~0U, FeaturesK8 },
365 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
366 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
367 { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
368 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
369 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
370 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
371 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
372 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]373 // Bobcat architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]374 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
375 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]376 // Bulldozer architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]377 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
378 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
379 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
380 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]381 // Zen architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]382 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
383 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]384 // Generic 64-bit processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]385 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]386 // Geode processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]387 { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]388};
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]389
390X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]391 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]392 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]393 return P.Kind;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]394
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]395 return CK_None;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]396}
397
398void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
399 bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]400 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]401 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]402 Values.emplace_back(P.Name);
403}
404
405ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
406 // FIXME: Can we avoid a linear search here? The table might be sorted by
407 // CPUKind so we could binary search?
408 for (const auto &P : Processors) {
409 if (P.Kind == Kind) {
410 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
411 return static_cast<ProcessorFeatures>(P.KeyFeature);
412 }
413 }
414
415 llvm_unreachable("Unable to find CPU kind!");
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]416}
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]417
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]418// Features with no dependencies.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]419constexpr FeatureBitset ImpliedFeatures64BIT = {};
420constexpr FeatureBitset ImpliedFeaturesADX = {};
421constexpr FeatureBitset ImpliedFeaturesBMI = {};
422constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
423constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
424constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
425constexpr FeatureBitset ImpliedFeaturesCLWB = {};
426constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
427constexpr FeatureBitset ImpliedFeaturesCMOV = {};
428constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
429constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
430constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
431constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
432constexpr FeatureBitset ImpliedFeaturesFXSR = {};
433constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
434constexpr FeatureBitset ImpliedFeaturesLWP = {};
435constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
436constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
437constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
438constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
439constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
440constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
441constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
442constexpr FeatureBitset ImpliedFeaturesPKU = {};
443constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
444constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
445constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
446constexpr FeatureBitset ImpliedFeaturesRDPID = {};
447constexpr FeatureBitset ImpliedFeaturesRDRND = {};
448constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
449constexpr FeatureBitset ImpliedFeaturesRTM = {};
450constexpr FeatureBitset ImpliedFeaturesSAHF = {};
451constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
452constexpr FeatureBitset ImpliedFeaturesSGX = {};
453constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
454constexpr FeatureBitset ImpliedFeaturesTBM = {};
455constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
456constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
457constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
458constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
459constexpr FeatureBitset ImpliedFeaturesX87 = {};
460constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]461
462// Not really CPU features, but need to be in the table because clang uses
463// target features to communicate them to the backend.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]464constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
465constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
466constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
467constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
468constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]469
470// XSAVE features are dependent on basic XSAVE.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]471constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
472constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
473constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]474
475// MMX->3DNOW->3DNOWA chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]476constexpr FeatureBitset ImpliedFeaturesMMX = {};
477constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
478constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]479
480// SSE/AVX/AVX512F chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]481constexpr FeatureBitset ImpliedFeaturesSSE = {};
482constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
483constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
484constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
485constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
486constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
487constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
488constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
489constexpr FeatureBitset ImpliedFeaturesAVX512F =
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]490 FeatureAVX2 | FeatureF16C | FeatureFMA;
491
492// Vector extensions that build on SSE or AVX.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]493constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
494constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
495constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
496constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
497constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
498constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
499constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
500constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]501
502// AVX512 features.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]503constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
504constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
505constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
506constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
507constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
508constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]509
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]510constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
511constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
512constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
513constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
514constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
515constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
516constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
517constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]518
519// FIXME: These two aren't really implemented and just exist in the feature
520// list for __builtin_cpu_supports. So omit their dependencies.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]521constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
522constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]523
524// SSE4_A->FMA4->XOP chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]525constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
526constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
527constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]528
529// AMX Features
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]530constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
531constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
532constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]533
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]534// Key Locker Features
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]535constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
536constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]537
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame^]538constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]539#define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]540#include "llvm/Support/X86TargetParser.def"
541};
542
543void llvm::X86::getFeaturesForCPU(StringRef CPU,
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]544 SmallVectorImpl<StringRef> &EnabledFeatures) {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]545 auto I = llvm::find_if(Processors,
546 [&](const ProcInfo &P) { return P.Name == CPU; });
547 assert(I != std::end(Processors) && "Processor not found!");
548
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]549 FeatureBitset Bits = I->Features;
550
551 // Remove the 64-bit feature which we only use to validate if a CPU can
552 // be used with 64-bit mode.
553 Bits &= ~Feature64BIT;
554
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]555 // Add the string version of all set bits.
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]556 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
557 if (Bits[i] && !FeatureInfos[i].Name.empty())
558 EnabledFeatures.push_back(FeatureInfos[i].Name);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]559}
560
561// For each feature that is (transitively) implied by this feature, set it.
562static void getImpliedEnabledFeatures(FeatureBitset &Bits,
563 const FeatureBitset &Implies) {
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]564 // Fast path: Implies is often empty.
565 if (!Implies.any())
566 return;
567 FeatureBitset Prev;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]568 Bits |= Implies;
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]569 do {
570 Prev = Bits;
571 for (unsigned i = CPU_FEATURE_MAX; i;)
572 if (Bits[--i])
573 Bits |= FeatureInfos[i].ImpliedFeatures;
574 } while (Prev != Bits);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]575}
576
577/// Create bit vector of features that are implied disabled if the feature
578/// passed in Value is disabled.
579static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
580 // Check all features looking for any dependent on this feature. If we find
581 // one, mark it and recursively find any feature that depend on it.
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]582 FeatureBitset Prev;
583 Bits.set(Value);
584 do {
585 Prev = Bits;
586 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
587 if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
588 Bits.set(i);
589 } while (Prev != Bits);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]590}
591
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]592void llvm::X86::updateImpliedFeatures(
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]593 StringRef Feature, bool Enabled,
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]594 StringMap<bool> &Features) {
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]595 auto I = llvm::find_if(
596 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
597 if (I == std::end(FeatureInfos)) {
Craig Topper44ea81a2020-07-07 00:27:50 -0700[diff] [blame]598 // FIXME: This shouldn't happen, but may not have all features in the table
599 // yet.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]600 return;
601 }
602
603 FeatureBitset ImpliedBits;
604 if (Enabled)
605 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
606 else
607 getImpliedDisabledFeatures(ImpliedBits,
608 std::distance(std::begin(FeatureInfos), I));
609
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]610 // Update the map entry for all implied features.
611 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
612 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
613 Features[FeatureInfos[i].Name] = Enabled;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]614}