| Tony Jiang | c260e0e | 2017-07-07 16:41:55 +0000 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s |
| 3 | ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s |
| 4 | |
| 5 | define zeroext i32 @ReverseBits(i32 zeroext %n) { |
| 6 | ; CHECK-LABEL: ReverseBits: |
| 7 | ; CHECK: # BB#0: # %entry |
| 8 | ; CHECK-NEXT: lis 4, -21846 |
| 9 | ; CHECK-NEXT: lis 5, 21845 |
| 10 | ; CHECK-NEXT: slwi 6, 3, 1 |
| 11 | ; CHECK-NEXT: srwi 3, 3, 1 |
| 12 | ; CHECK-NEXT: lis 7, -13108 |
| 13 | ; CHECK-NEXT: lis 8, 13107 |
| 14 | ; CHECK-NEXT: ori 4, 4, 43690 |
| 15 | ; CHECK-NEXT: ori 5, 5, 21845 |
| 16 | ; CHECK-NEXT: lis 10, -3856 |
| 17 | ; CHECK-NEXT: lis 11, 3855 |
| 18 | ; CHECK-NEXT: and 3, 3, 5 |
| 19 | ; CHECK-NEXT: and 4, 6, 4 |
| 20 | ; CHECK-NEXT: ori 5, 8, 13107 |
| 21 | ; CHECK-NEXT: or 3, 3, 4 |
| 22 | ; CHECK-NEXT: ori 4, 7, 52428 |
| 23 | ; CHECK-NEXT: slwi 9, 3, 2 |
| 24 | ; CHECK-NEXT: srwi 3, 3, 2 |
| 25 | ; CHECK-NEXT: and 3, 3, 5 |
| 26 | ; CHECK-NEXT: and 4, 9, 4 |
| 27 | ; CHECK-NEXT: ori 5, 11, 3855 |
| 28 | ; CHECK-NEXT: or 3, 3, 4 |
| 29 | ; CHECK-NEXT: ori 4, 10, 61680 |
| 30 | ; CHECK-NEXT: slwi 12, 3, 4 |
| 31 | ; CHECK-NEXT: srwi 3, 3, 4 |
| 32 | ; CHECK-NEXT: and 4, 12, 4 |
| 33 | ; CHECK-NEXT: and 3, 3, 5 |
| 34 | ; CHECK-NEXT: or 3, 3, 4 |
| 35 | ; CHECK-NEXT: rotlwi 4, 3, 24 |
| 36 | ; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15 |
| 37 | ; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31 |
| 38 | ; CHECK-NEXT: rldicl 3, 4, 0, 32 |
| 39 | ; CHECK-NEXT: clrldi 3, 3, 32 |
| 40 | ; CHECK-NEXT: blr |
| 41 | entry: |
| 42 | %shr = lshr i32 %n, 1 |
| 43 | %and = and i32 %shr, 1431655765 |
| 44 | %and1 = shl i32 %n, 1 |
| 45 | %shl = and i32 %and1, -1431655766 |
| 46 | %or = or i32 %and, %shl |
| 47 | %shr2 = lshr i32 %or, 2 |
| 48 | %and3 = and i32 %shr2, 858993459 |
| 49 | %and4 = shl i32 %or, 2 |
| 50 | %shl5 = and i32 %and4, -858993460 |
| 51 | %or6 = or i32 %and3, %shl5 |
| 52 | %shr7 = lshr i32 %or6, 4 |
| 53 | %and8 = and i32 %shr7, 252645135 |
| 54 | %and9 = shl i32 %or6, 4 |
| 55 | %shl10 = and i32 %and9, -252645136 |
| 56 | %or11 = or i32 %and8, %shl10 |
| 57 | %shr13 = lshr i32 %or11, 24 |
| 58 | %and14 = lshr i32 %or11, 8 |
| 59 | %shr15 = and i32 %and14, 65280 |
| 60 | %and17 = shl i32 %or11, 8 |
| 61 | %shl18 = and i32 %and17, 16711680 |
| 62 | %shl21 = shl i32 %or11, 24 |
| 63 | %or16 = or i32 %shl21, %shr13 |
| 64 | %or19 = or i32 %or16, %shr15 |
| 65 | %or22 = or i32 %or19, %shl18 |
| 66 | ret i32 %or22 |
| 67 | } |