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Dan Gohman10e730a2015-06-29 23:51:55 +00001//===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// \brief This file defines the WebAssembly-specific TargetTransformInfo
12/// implementation.
13///
14//===----------------------------------------------------------------------===//
15
16#include "WebAssemblyTargetTransformInfo.h"
David Blaikieb3bde2e2017-11-17 01:07:10 +000017#include "llvm/CodeGen/CostTable.h"
Dan Gohman10e730a2015-06-29 23:51:55 +000018#include "llvm/Support/Debug.h"
Dan Gohman10e730a2015-06-29 23:51:55 +000019using namespace llvm;
20
21#define DEBUG_TYPE "wasmtti"
22
23TargetTransformInfo::PopcntSupportKind
Dan Gohman01612f62015-08-24 16:51:46 +000024WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
Dan Gohman10e730a2015-06-29 23:51:55 +000025 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
Dan Gohman01612f62015-08-24 16:51:46 +000026 return TargetTransformInfo::PSK_FastHardware;
27}
Dan Gohman73d7a552016-05-23 22:47:07 +000028
29unsigned WebAssemblyTTIImpl::getNumberOfRegisters(bool Vector) {
30 unsigned Result = BaseT::getNumberOfRegisters(Vector);
31
32 // For SIMD, use at least 16 registers, as a rough guess.
33 if (Vector)
34 Result = std::max(Result, 16u);
35
36 return Result;
37}
38
Daniel Neilsonc0112ae2017-06-12 14:22:21 +000039unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const {
Dan Gohman73d7a552016-05-23 22:47:07 +000040 if (Vector && getST()->hasSIMD128())
41 return 128;
42
43 return 64;
44}
45
46unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
47 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
48 TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
Mohammed Agabaria2c96c432017-01-11 08:23:37 +000049 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) {
Dan Gohman73d7a552016-05-23 22:47:07 +000050
51 unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
52 Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
53
54 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
55 switch (Opcode) {
56 case Instruction::LShr:
57 case Instruction::AShr:
58 case Instruction::Shl:
59 // SIMD128's shifts currently only accept a scalar shift count. For each
60 // element, we'll need to extract, op, insert. The following is a rough
61 // approxmation.
62 if (Opd2Info != TTI::OK_UniformValue &&
63 Opd2Info != TTI::OK_UniformConstantValue)
64 Cost = VTy->getNumElements() *
65 (TargetTransformInfo::TCC_Basic +
66 getArithmeticInstrCost(Opcode, VTy->getElementType()) +
67 TargetTransformInfo::TCC_Basic);
68 break;
69 }
70 }
71 return Cost;
72}
73
74unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
75 unsigned Index) {
76 unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
77
78 // SIMD128's insert/extract currently only take constant indices.
79 if (Index == -1u)
80 return Cost + 25 * TargetTransformInfo::TCC_Expensive;
81
82 return Cost;
83}