| Sanjay Patel | a4546ef | 2017-04-03 22:45:46 +0000 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s |
| 3 | |
| 4 | define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind { |
| 5 | ; CHECK-LABEL: ne_neg1_and_ne_zero: |
| 6 | ; CHECK: @ BB#0: |
| 7 | ; CHECK-NEXT: add r1, r0, #1 |
| 8 | ; CHECK-NEXT: mov r0, #0 |
| 9 | ; CHECK-NEXT: cmp r1, #1 |
| 10 | ; CHECK-NEXT: movwhi r0, #1 |
| 11 | ; CHECK-NEXT: bx lr |
| 12 | %cmp1 = icmp ne i32 %x, -1 |
| 13 | %cmp2 = icmp ne i32 %x, 0 |
| 14 | %and = and i1 %cmp1, %cmp2 |
| 15 | ret i1 %and |
| 16 | } |
| 17 | |
| 18 | ; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401 |
| 19 | |
| 20 | define zeroext i1 @and_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { |
| 21 | ; CHECK-LABEL: and_eq: |
| 22 | ; CHECK: @ BB#0: |
| 23 | ; CHECK-NEXT: cmp r2, r3 |
| 24 | ; CHECK-NEXT: mov r2, #0 |
| 25 | ; CHECK-NEXT: movweq r2, #1 |
| 26 | ; CHECK-NEXT: mov r12, #0 |
| 27 | ; CHECK-NEXT: cmp r0, r1 |
| 28 | ; CHECK-NEXT: movweq r12, #1 |
| 29 | ; CHECK-NEXT: and r0, r12, r2 |
| 30 | ; CHECK-NEXT: bx lr |
| 31 | %cmp1 = icmp eq i32 %a, %b |
| 32 | %cmp2 = icmp eq i32 %c, %d |
| 33 | %and = and i1 %cmp1, %cmp2 |
| 34 | ret i1 %and |
| 35 | } |
| 36 | |
| 37 | define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { |
| 38 | ; CHECK-LABEL: or_ne: |
| 39 | ; CHECK: @ BB#0: |
| 40 | ; CHECK-NEXT: cmp r2, r3 |
| 41 | ; CHECK-NEXT: mov r2, #0 |
| 42 | ; CHECK-NEXT: movwne r2, #1 |
| 43 | ; CHECK-NEXT: mov r12, #0 |
| 44 | ; CHECK-NEXT: cmp r0, r1 |
| 45 | ; CHECK-NEXT: movwne r12, #1 |
| 46 | ; CHECK-NEXT: orr r0, r12, r2 |
| 47 | ; CHECK-NEXT: bx lr |
| 48 | %cmp1 = icmp ne i32 %a, %b |
| 49 | %cmp2 = icmp ne i32 %c, %d |
| 50 | %or = or i1 %cmp1, %cmp2 |
| 51 | ret i1 %or |
| 52 | } |
| 53 | |
| 54 | define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) nounwind { |
| 55 | ; CHECK-LABEL: and_eq_vec: |
| 56 | ; CHECK: @ BB#0: |
| 57 | ; CHECK-NEXT: .save {r11, lr} |
| 58 | ; CHECK-NEXT: push {r11, lr} |
| 59 | ; CHECK-NEXT: vmov d19, r2, r3 |
| 60 | ; CHECK-NEXT: add r12, sp, #40 |
| 61 | ; CHECK-NEXT: add lr, sp, #8 |
| 62 | ; CHECK-NEXT: vmov d18, r0, r1 |
| 63 | ; CHECK-NEXT: vld1.64 {d16, d17}, [lr] |
| 64 | ; CHECK-NEXT: add r0, sp, #24 |
| 65 | ; CHECK-NEXT: vld1.64 {d20, d21}, [r12] |
| 66 | ; CHECK-NEXT: vceq.i32 q8, q9, q8 |
| 67 | ; CHECK-NEXT: vld1.64 {d22, d23}, [r0] |
| 68 | ; CHECK-NEXT: vceq.i32 q9, q11, q10 |
| 69 | ; CHECK-NEXT: vmovn.i32 d16, q8 |
| 70 | ; CHECK-NEXT: vmovn.i32 d17, q9 |
| 71 | ; CHECK-NEXT: vand d16, d16, d17 |
| 72 | ; CHECK-NEXT: vmov r0, r1, d16 |
| 73 | ; CHECK-NEXT: pop {r11, pc} |
| 74 | %cmp1 = icmp eq <4 x i32> %a, %b |
| 75 | %cmp2 = icmp eq <4 x i32> %c, %d |
| 76 | %and = and <4 x i1> %cmp1, %cmp2 |
| 77 | ret <4 x i1> %and |
| 78 | } |
| 79 | |