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gerrit-public.fairphone.software / toolchain / llvm-project / 0218fb66867c7b53eacf916ff4d7978cc9c9ea97 / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: e73c73e3bfdde46589c42c2bfc5db3436a3fe507 [file] [log] [blame]
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1// Bitcasts between 512-bit vector types. Return the original type since
2// no instruction is needed for the conversion
3let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
17
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
48
49// Bitcasts between 256-bit vector types. Return the original type since
50// no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
81}
82
83//
84// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
85//
86
87let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
91}
92
93def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
97
98//===----------------------------------------------------------------------===//
99// AVX-512 - VECTOR INSERT
100//
101// -- 32x8 form --
102let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
107let mayLoad = 1 in
108def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
112}
113
114// -- 64x4 fp form --
115let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
120let mayLoad = 1 in
121def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
125}
126// -- 32x4 integer form --
127let neverHasSideEffects = 1 in {
128def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
132let mayLoad = 1 in
133def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
137
138}
139
140let neverHasSideEffects = 1 in {
141// -- 64x4 form --
142def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
146let mayLoad = 1 in
147def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
151}
152
153def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
165
166def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179
180def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
192
193def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206
207// vinsertps - insert f32 to XMM
208def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
212 EVEX_4V;
213def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
219
220//===----------------------------------------------------------------------===//
221// AVX-512 VECTOR EXTRACT
222//---
223let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
224// -- 32x4 form --
225def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
233
234// -- 64x4 form --
235def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
239let mayStore = 1 in
240def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
244}
245
246let neverHasSideEffects = 1 in {
247// -- 32x4 form --
248def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
256
257// -- 64x4 form --
258def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
262let mayStore = 1 in
263def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
267}
268
269def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
272
273def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
276
277def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
280
281def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
284
285
286def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
289
290def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
293
294def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
297
298def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
301
302// A 256-bit subvector extract from the first 512-bit vector position
303// is a subregister copy that needs no instruction.
304def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
312
313// zmm -> xmm
314def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
322
323
324// A 128-bit subvector insert to the first 512-bit vector position
325// is a subregister copy that needs no instruction.
326def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
329 sub_ymm)>;
330def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
333 sub_ymm)>;
334def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
337 sub_ymm)>;
338def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
341 sub_ymm)>;
342
343def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
351
352// vextractps - extract 32 bits from XMM
353def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
357 EVEX;
358
359def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
363 addr:$dst)]>, EVEX;
364
365//===---------------------------------------------------------------------===//
366// AVX-512 BROADCAST
367//---
368multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
373 []>, EVEX;
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
376}
377let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
379 VR128X, f32mem>,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
381}
382
383let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
385 VR128X, f64mem>,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
387}
388
389def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
393
394multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
395 RegisterClass SrcRC, RegisterClass KRC> {
396 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
398 []>, EVEX, EVEX_V512;
399 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
400 (ins KRC:$mask, SrcRC:$src),
401 !strconcat(OpcodeStr,
402 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
403 []>, EVEX, EVEX_V512, EVEX_KZ;
404}
405
406defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
407defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
408 VEX_W;
409
410def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
411 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
412
413def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
414 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
415
416def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
417 (VPBROADCASTDrZrr GR32:$src)>;
418def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
419 (VPBROADCASTQrZrr GR64:$src)>;
420
421multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
422 X86MemOperand x86memop, PatFrag ld_frag,
423 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
424 RegisterClass KRC> {
425 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
426 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
427 [(set DstRC:$dst,
428 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
429 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
430 VR128X:$src),
431 !strconcat(OpcodeStr,
432 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
433 [(set DstRC:$dst,
434 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
435 EVEX, EVEX_KZ;
436 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
437 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
438 [(set DstRC:$dst,
439 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
440 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
441 x86memop:$src),
442 !strconcat(OpcodeStr,
443 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
444 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
445 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
446}
447
448defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
449 loadi32, VR512, v16i32, v4i32, VK16WM>,
450 EVEX_V512, EVEX_CD8<32, CD8VT1>;
451defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
452 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
453 EVEX_CD8<64, CD8VT1>;
454
455def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
456 (VBROADCASTSSZrr VR128X:$src)>;
457def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
458 (VBROADCASTSDZrr VR128X:$src)>;
459
460// Provide fallback in case the load node that is used in the patterns above
461// is used by additional users, which prevents the pattern selection.
462def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
463 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
464def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
465 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
466
467
468let Predicates = [HasAVX512] in {
469def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
470 (EXTRACT_SUBREG
471 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
472 addr:$src)), sub_ymm)>;
473}
474//===----------------------------------------------------------------------===//
475// AVX-512 BROADCAST MASK TO VECTOR REGISTER
476//---
477
478multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
479 RegisterClass DstRC, RegisterClass KRC,
480 ValueType OpVT, ValueType SrcVT> {
481def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
483 []>, EVEX;
484}
485
486defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
487 VK16, v16i32, v16i1>, EVEX_V512;
488defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
489 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
490
491//===----------------------------------------------------------------------===//
492// AVX-512 - VPERM
493//
494// -- immediate form --
495multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
496 SDNode OpNode, PatFrag mem_frag,
497 X86MemOperand x86memop, ValueType OpVT> {
498 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
499 (ins RC:$src1, i8imm:$src2),
500 !strconcat(OpcodeStr,
501 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
502 [(set RC:$dst,
503 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
504 EVEX;
505 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
506 (ins x86memop:$src1, i8imm:$src2),
507 !strconcat(OpcodeStr,
508 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
509 [(set RC:$dst,
510 (OpVT (OpNode (mem_frag addr:$src1),
511 (i8 imm:$src2))))]>, EVEX;
512}
513
514defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
515 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
516let ExeDomain = SSEPackedDouble in
517defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
518 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
519
520// -- VPERM - register form --
521multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
523
524 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, RC:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
528 [(set RC:$dst,
529 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
530
531 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
532 (ins RC:$src1, x86memop:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
535 [(set RC:$dst,
536 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
537 EVEX_4V;
538}
539
540defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
541 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
542defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
543 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
544let ExeDomain = SSEPackedSingle in
545defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
546 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
547let ExeDomain = SSEPackedDouble in
548defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
549 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550
551// -- VPERM2I - 3 source operands form --
552multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
553 PatFrag mem_frag, X86MemOperand x86memop,
554 ValueType OpVT> {
555let Constraints = "$src1 = $dst" in {
556 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
557 (ins RC:$src1, RC:$src2, RC:$src3),
558 !strconcat(OpcodeStr,
559 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
560 [(set RC:$dst,
561 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
562 EVEX_4V;
563
564 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
565 (ins RC:$src1, RC:$src2, x86memop:$src3),
566 !strconcat(OpcodeStr,
567 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
568 [(set RC:$dst,
569 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
570 (mem_frag addr:$src3))))]>, EVEX_4V;
571 }
572}
573defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
574 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
575defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
576 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
578 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
579defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
580 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
581
582//===----------------------------------------------------------------------===//
583// AVX-512 - BLEND using mask
584//
585multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
586 RegisterClass KRC, RegisterClass RC,
587 X86MemOperand x86memop, PatFrag mem_frag,
588 SDNode OpNode, ValueType vt> {
589 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
590 (ins KRC:$mask, RC:$src1, RC:$src2),
591 !strconcat(OpcodeStr,
592 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
593 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
594 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
595
596 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
597 (ins KRC:$mask, RC:$src1, x86memop:$src2),
598 !strconcat(OpcodeStr,
599 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
600 []>,
601 EVEX_4V, EVEX_K;
602}
603
604let ExeDomain = SSEPackedSingle in
605defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
606 memopv16f32, vselect, v16f32>,
607 EVEX_CD8<32, CD8VF>, EVEX_V512;
608let ExeDomain = SSEPackedDouble in
609defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
610 memopv8f64, vselect, v8f64>,
611 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
612
613defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
614 memopv8i64, vselect, v16i32>,
615 EVEX_CD8<32, CD8VF>, EVEX_V512;
616
617defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
618 memopv8i64, vselect, v8i64>, VEX_W,
619 EVEX_CD8<64, CD8VF>, EVEX_V512;
620
621
622let Predicates = [HasAVX512] in {
623def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
624 (v8f32 VR256X:$src2))),
625 (EXTRACT_SUBREG
626 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
627 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
628 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
629
630def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
631 (v8i32 VR256X:$src2))),
632 (EXTRACT_SUBREG
633 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
634 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
635 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
636}
637
638multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
639 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
640 SDNode OpNode, ValueType vt> {
641 def rr : AVX512BI<opc, MRMSrcReg,
642 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
643 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
644 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
645 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
646 def rm : AVX512BI<opc, MRMSrcMem,
647 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
648 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
649 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
650 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
651}
652
653defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
654 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
655defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
656 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
657
658defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
659 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
660defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
661 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
662
663def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
664 (COPY_TO_REGCLASS (VPCMPGTDZrr
665 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
666 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
667
668def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
669 (COPY_TO_REGCLASS (VPCMPEQDZrr
670 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
671 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
672
673multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
674 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
675 SDNode OpNode, ValueType vt, Operand CC, string asm,
676 string asm_alt> {
677 def rri : AVX512AIi8<opc, MRMSrcReg,
678 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
679 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
680 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
681 def rmi : AVX512AIi8<opc, MRMSrcMem,
682 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
683 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
684 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
685 // Accept explicit immediate argument form instead of comparison code.
686 let neverHasSideEffects = 1 in {
687 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
688 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
689 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
690 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
691 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
692 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
693 }
694}
695
696defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
697 X86cmpm, v16i32, AVXCC,
698 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
699 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
700 EVEX_V512, EVEX_CD8<32, CD8VF>;
701defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
702 X86cmpmu, v16i32, AVXCC,
703 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
704 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
705 EVEX_V512, EVEX_CD8<32, CD8VF>;
706
707defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
708 X86cmpm, v8i64, AVXCC,
709 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
710 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
711 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
712defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
713 X86cmpmu, v8i64, AVXCC,
714 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
716 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
717
718// avx512_cmp_packed - sse 1 & 2 compare packed instructions
719multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
720 X86MemOperand x86memop, Operand CC,
721 SDNode OpNode, ValueType vt, string asm,
722 string asm_alt, Domain d> {
723 def rri : AVX512PIi8<0xC2, MRMSrcReg,
724 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
725 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
726 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
727 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
728 [(set KRC:$dst,
729 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
730
731 // Accept explicit immediate argument form instead of comparison code.
732 let neverHasSideEffects = 1 in {
733 def rri_alt : PIi8<0xC2, MRMSrcReg,
734 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
735 asm_alt, [], IIC_SSE_ALU_F32P_RR, d>;
736 def rmi_alt : PIi8<0xC2, MRMSrcMem,
737 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
738 asm_alt, [], IIC_SSE_ALU_F32P_RM, d>;
739 }
740}
741
742defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
743 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
744 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
745 SSEPackedSingle>, TB, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
746defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
747 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
749 SSEPackedDouble>, TB, OpSize, EVEX_4V, VEX_W, EVEX_V512,
750 EVEX_CD8<64, CD8VF>;
751
752def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
753 (COPY_TO_REGCLASS (VCMPPSZrri
754 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
755 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
756 imm:$cc), VK8)>;
757def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
758 (COPY_TO_REGCLASS (VPCMPDZrri
759 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
760 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
761 imm:$cc), VK8)>;
762def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
763 (COPY_TO_REGCLASS (VPCMPUDZrri
764 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
766 imm:$cc), VK8)>;
767
768// Mask register copy, including
769// - copy between mask registers
770// - load/store mask registers
771// - copy from GPR to mask register and vice versa
772//
773multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
774 string OpcodeStr, RegisterClass KRC,
775 ValueType vt, X86MemOperand x86memop> {
776 let neverHasSideEffects = 1 in {
777 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
778 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
779 let mayLoad = 1 in
780 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
782 [(set KRC:$dst, (vt (load addr:$src)))]>;
783 let mayStore = 1 in
784 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
785 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
786 }
787}
788
789multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
790 string OpcodeStr,
791 RegisterClass KRC, RegisterClass GRC> {
792 let neverHasSideEffects = 1 in {
793 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
794 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
795 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
796 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
797 }
798}
799
800let Predicates = [HasAVX512] in {
801 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
802 VEX, TB;
803 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
804 VEX, TB;
805}
806
807let Predicates = [HasAVX512] in {
808 // GR16 from/to 16-bit mask
809 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
810 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
811 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
812 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
813
814 // Store kreg in memory
815 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
816 (KMOVWmk addr:$dst, VK16:$src)>;
817
818 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
819 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
820}
821// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
822let Predicates = [HasAVX512] in {
823 // GR from/to 8-bit mask without native support
824 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
825 (COPY_TO_REGCLASS
826 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
827 VK8)>;
828 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
829 (EXTRACT_SUBREG
830 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
831 sub_8bit)>;
832}
833
834// Mask unary operation
835// - KNOT
836multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
837 RegisterClass KRC, SDPatternOperator OpNode> {
838 let Predicates = [HasAVX512] in
839 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
840 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
841 [(set KRC:$dst, (OpNode KRC:$src))]>;
842}
843
844multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
845 SDPatternOperator OpNode> {
846 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
847 VEX, TB;
848}
849
850defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
851
852def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
853def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
854 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
855
856// With AVX-512, 8-bit mask is promoted to 16-bit mask.
857def : Pat<(not VK8:$src),
858 (COPY_TO_REGCLASS
859 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
860
861// Mask binary operation
862// - KADD, KAND, KANDN, KOR, KXNOR, KXOR
863multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
864 RegisterClass KRC, SDPatternOperator OpNode> {
865 let Predicates = [HasAVX512] in
866 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
867 !strconcat(OpcodeStr,
868 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
869 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
870}
871
872multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
873 SDPatternOperator OpNode> {
874 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
875 VEX_4V, VEX_L, TB;
876}
877
878def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
879def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
880
881let isCommutable = 1 in {
882 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
883 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
884 let isCommutable = 0 in
885 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
886 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
887 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
888 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
889}
890
891multiclass avx512_mask_binop_int<string IntName, string InstName> {
892 let Predicates = [HasAVX512] in
893 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
894 VK16:$src1, VK16:$src2),
895 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
896}
897
898defm : avx512_mask_binop_int<"kadd", "KADD">;
899defm : avx512_mask_binop_int<"kand", "KAND">;
900defm : avx512_mask_binop_int<"kandn", "KANDN">;
901defm : avx512_mask_binop_int<"kor", "KOR">;
902defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
903defm : avx512_mask_binop_int<"kxor", "KXOR">;
904// With AVX-512, 8-bit mask is promoted to 16-bit mask.
905multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
906 let Predicates = [HasAVX512] in
907 def : Pat<(OpNode VK8:$src1, VK8:$src2),
908 (COPY_TO_REGCLASS
909 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
910 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
911}
912
913defm : avx512_binop_pat<and, KANDWrr>;
914defm : avx512_binop_pat<andn, KANDNWrr>;
915defm : avx512_binop_pat<or, KORWrr>;
916defm : avx512_binop_pat<xnor, KXNORWrr>;
917defm : avx512_binop_pat<xor, KXORWrr>;
918
919// Mask unpacking
920multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
921 RegisterClass KRC1, RegisterClass KRC2> {
922 let Predicates = [HasAVX512] in
923 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
924 !strconcat(OpcodeStr,
925 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
926}
927
928multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
929 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
930 VEX_4V, VEX_L, OpSize, TB;
931}
932
933defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
934
935multiclass avx512_mask_unpck_int<string IntName, string InstName> {
936 let Predicates = [HasAVX512] in
937 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
938 VK8:$src1, VK8:$src2),
939 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
940}
941
942defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
943// Mask bit testing
944multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
945 SDNode OpNode> {
946 let Predicates = [HasAVX512], Defs = [EFLAGS] in
947 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
948 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
949 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
950}
951
952multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
953 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
954 VEX, TB;
955}
956
957defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
958defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
959
960// Mask shift
961multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
962 SDNode OpNode> {
963 let Predicates = [HasAVX512] in
964 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
965 !strconcat(OpcodeStr,
966 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
967 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
968}
969
970multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
971 SDNode OpNode> {
972 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
973 VEX, OpSize, TA, VEX_W;
974}
975
976defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
977defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
978
979// Mask setting all 0s or 1s
980multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
981 let Predicates = [HasAVX512] in
982 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
983 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
984 [(set KRC:$dst, (VT Val))]>;
985}
986
987multiclass avx512_mask_setop_w<PatFrag Val> {
988 defm B : avx512_mask_setop<VK8, v8i1, Val>;
989 defm W : avx512_mask_setop<VK16, v16i1, Val>;
990}
991
992defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
993defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
994
995// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
996let Predicates = [HasAVX512] in {
997 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
998 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
999}
1000def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1001 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1002
1003def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1004 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1005
1006def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1007 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1008
1009//===----------------------------------------------------------------------===//
1010// AVX-512 - Aligned and unaligned load and store
1011//
1012
1013multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1014 X86MemOperand x86memop, PatFrag ld_frag,
1015 string asm, Domain d> {
1016let neverHasSideEffects = 1 in
1017 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1018 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1019 EVEX;
1020let canFoldAsLoad = 1 in
1021 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1022 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1023 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1024let Constraints = "$src1 = $dst" in {
1025 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1026 (ins RC:$src1, KRC:$mask, RC:$src2),
1027 !strconcat(asm,
1028 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1029 EVEX, EVEX_K;
1030 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1031 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1032 !strconcat(asm,
1033 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1034 [], d>, EVEX, EVEX_K;
1035}
1036}
1037
1038defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1039 "vmovaps", SSEPackedSingle>,
1040 EVEX_V512, EVEX_CD8<32, CD8VF>;
1041defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1042 "vmovapd", SSEPackedDouble>,
1043 OpSize, EVEX_V512, VEX_W,
1044 EVEX_CD8<64, CD8VF>;
1045defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1046 "vmovups", SSEPackedSingle>,
1047 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1048defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1049 "vmovupd", SSEPackedDouble>,
1050 OpSize, EVEX_V512, VEX_W,
1051 EVEX_CD8<64, CD8VF>;
1052def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1053 "vmovaps\t{$src, $dst|$dst, $src}",
1054 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1055 SSEPackedSingle>, EVEX, EVEX_V512, TB,
1056 EVEX_CD8<32, CD8VF>;
1057def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1058 "vmovapd\t{$src, $dst|$dst, $src}",
1059 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1060 SSEPackedDouble>, EVEX, EVEX_V512,
1061 OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
1062def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1063 "vmovups\t{$src, $dst|$dst, $src}",
1064 [(store (v16f32 VR512:$src), addr:$dst)],
1065 SSEPackedSingle>, EVEX, EVEX_V512, TB,
1066 EVEX_CD8<32, CD8VF>;
1067def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1068 "vmovupd\t{$src, $dst|$dst, $src}",
1069 [(store (v8f64 VR512:$src), addr:$dst)],
1070 SSEPackedDouble>, EVEX, EVEX_V512,
1071 OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
1072
1073// Use vmovaps/vmovups for AVX-512 integer load/store.
1074// 512-bit load/store
1075def : Pat<(alignedloadv8i64 addr:$src),
1076 (VMOVAPSZrm addr:$src)>;
1077def : Pat<(loadv8i64 addr:$src),
1078 (VMOVUPSZrm addr:$src)>;
1079
1080def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1081 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1082def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1083 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1084
1085def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1086 (VMOVUPDZmr addr:$dst, VR512:$src)>;
1087def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1088 (VMOVUPSZmr addr:$dst, VR512:$src)>;
1089
1090let neverHasSideEffects = 1 in {
1091 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1092 (ins VR512:$src),
1093 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1094 EVEX, EVEX_V512;
1095 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1096 (ins VR512:$src),
1097 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1098 EVEX, EVEX_V512, VEX_W;
1099let mayStore = 1 in {
1100 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1101 (ins i512mem:$dst, VR512:$src),
1102 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1103 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1104 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1105 (ins i512mem:$dst, VR512:$src),
1106 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1107 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1108}
1109let mayLoad = 1 in {
1110def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1111 (ins i512mem:$src),
1112 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1113 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1114def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1115 (ins i512mem:$src),
1116 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1117 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1118}
1119}
1120
1121multiclass avx512_mov_int<bits<8> opc, string asm, RegisterClass RC,
1122 RegisterClass KRC,
1123 PatFrag ld_frag, X86MemOperand x86memop> {
1124let neverHasSideEffects = 1 in
1125 def rr : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1126 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>,
1127 EVEX;
1128let canFoldAsLoad = 1 in
1129 def rm : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1130 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1131 [(set RC:$dst, (ld_frag addr:$src))]>,
1132 EVEX;
1133let Constraints = "$src1 = $dst" in {
1134 def rrk : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst),
1135 (ins RC:$src1, KRC:$mask, RC:$src2),
1136 !strconcat(asm,
1137 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1138 EVEX, EVEX_K;
1139 def rmk : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst),
1140 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1141 !strconcat(asm,
1142 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1143 []>, EVEX, EVEX_K;
1144}
1145}
1146
1147defm VMOVDQU32 : avx512_mov_int<0x6F, "vmovdqu32", VR512, VK16WM, memopv16i32, i512mem>,
1148 EVEX_V512, EVEX_CD8<32, CD8VF>;
1149defm VMOVDQU64 : avx512_mov_int<0x6F, "vmovdqu64", VR512, VK8WM, memopv8i64, i512mem>,
1150 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1151
1152let AddedComplexity = 20 in {
1153def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1154 (v16f32 VR512:$src2))),
1155 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1156def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1157 (v8f64 VR512:$src2))),
1158 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1159def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1160 (v16i32 VR512:$src2))),
1161 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1162def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1163 (v8i64 VR512:$src2))),
1164 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1165}
1166// Move Int Doubleword to Packed Double Int
1167//
1168def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1169 "vmovd{z}\t{$src, $dst|$dst, $src}",
1170 [(set VR128X:$dst,
1171 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1172 EVEX, VEX_LIG;
1173def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1174 "vmovd{z}\t{$src, $dst|$dst, $src}",
1175 [(set VR128X:$dst,
1176 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1177 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1178def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1179 "vmovq{z}\t{$src, $dst|$dst, $src}",
1180 [(set VR128X:$dst,
1181 (v2i64 (scalar_to_vector GR64:$src)))],
1182 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1183def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1184 "vmovq{z}\t{$src, $dst|$dst, $src}",
1185 [(set FR64:$dst, (bitconvert GR64:$src))],
1186 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1187def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1188 "vmovq{z}\t{$src, $dst|$dst, $src}",
1189 [(set GR64:$dst, (bitconvert FR64:$src))],
1190 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1191def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1192 "vmovq{z}\t{$src, $dst|$dst, $src}",
1193 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1194 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1195 EVEX_CD8<64, CD8VT1>;
1196
1197// Move Int Doubleword to Single Scalar
1198//
1199def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1200 "vmovd{z}\t{$src, $dst|$dst, $src}",
1201 [(set FR32X:$dst, (bitconvert GR32:$src))],
1202 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1203
1204def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1205 "vmovd{z}\t{$src, $dst|$dst, $src}",
1206 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1207 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1208
1209// Move Packed Doubleword Int to Packed Double Int
1210//
1211def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1212 "vmovd{z}\t{$src, $dst|$dst, $src}",
1213 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1214 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1215 EVEX, VEX_LIG;
1216def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1217 (ins i32mem:$dst, VR128X:$src),
1218 "vmovd{z}\t{$src, $dst|$dst, $src}",
1219 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1220 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1221 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1222
1223// Move Packed Doubleword Int first element to Doubleword Int
1224//
1225def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1226 "vmovq{z}\t{$src, $dst|$dst, $src}",
1227 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1228 (iPTR 0)))],
1229 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1230 Requires<[HasAVX512, In64BitMode]>;
1231
1232def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs),
1233 (ins i64mem:$dst, VR128X:$src),
1234 "vmovq{z}\t{$src, $dst|$dst, $src}",
1235 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1236 addr:$dst)], IIC_SSE_MOVDQ>,
1237 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1238 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1239
1240// Move Scalar Single to Double Int
1241//
1242def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1243 (ins FR32X:$src),
1244 "vmovd{z}\t{$src, $dst|$dst, $src}",
1245 [(set GR32:$dst, (bitconvert FR32X:$src))],
1246 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1247def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1248 (ins i32mem:$dst, FR32X:$src),
1249 "vmovd{z}\t{$src, $dst|$dst, $src}",
1250 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1251 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1252
1253// Move Quadword Int to Packed Quadword Int
1254//
1255def VMOVQI2PQIZrm : AVX512SI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1256 (ins i64mem:$src),
1257 "vmovq{z}\t{$src, $dst|$dst, $src}",
1258 [(set VR128X:$dst,
1259 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1260 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1261
1262//===----------------------------------------------------------------------===//
1263// AVX-512 MOVSS, MOVSD
1264//===----------------------------------------------------------------------===//
1265
1266multiclass avx512_move_scalar <string asm, RegisterClass RC,
1267 SDNode OpNode, ValueType vt,
1268 X86MemOperand x86memop, PatFrag mem_pat> {
1269 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1271 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1272 (scalar_to_vector RC:$src2))))],
1273 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1274 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1275 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1276 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1277 EVEX, VEX_LIG;
1278 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1279 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1280 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1281 EVEX, VEX_LIG;
1282}
1283
1284let ExeDomain = SSEPackedSingle in
1285defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1286 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1287
1288let ExeDomain = SSEPackedDouble in
1289defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1290 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1291
1292
1293// For the disassembler
1294let isCodeGenOnly = 1 in {
1295 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1296 (ins VR128X:$src1, FR32X:$src2),
1297 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1298 IIC_SSE_MOV_S_RR>,
1299 XS, EVEX_4V, VEX_LIG;
1300 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1301 (ins VR128X:$src1, FR64X:$src2),
1302 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1303 IIC_SSE_MOV_S_RR>,
1304 XD, EVEX_4V, VEX_LIG, VEX_W;
1305}
1306
1307let Predicates = [HasAVX512] in {
1308 let AddedComplexity = 15 in {
1309 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1310 // MOVS{S,D} to the lower bits.
1311 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1312 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1313 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1314 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1315 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1316 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1317 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1318 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1319
1320 // Move low f32 and clear high bits.
1321 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1322 (SUBREG_TO_REG (i32 0),
1323 (VMOVSSZrr (v4f32 (V_SET0)),
1324 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1325 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1326 (SUBREG_TO_REG (i32 0),
1327 (VMOVSSZrr (v4i32 (V_SET0)),
1328 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1329 }
1330
1331 let AddedComplexity = 20 in {
1332 // MOVSSrm zeros the high parts of the register; represent this
1333 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1334 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1335 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1336 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1337 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1338 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1339 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1340
1341 // MOVSDrm zeros the high parts of the register; represent this
1342 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1343 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1344 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1345 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1346 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1347 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1348 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1349 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1350 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1351 def : Pat<(v2f64 (X86vzload addr:$src)),
1352 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1353
1354 // Represent the same patterns above but in the form they appear for
1355 // 256-bit types
1356 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1357 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1358 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1359 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1360 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1361 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1362 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1363 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1364 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1365 }
1366 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1367 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1368 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1369 FR32X:$src)), sub_xmm)>;
1370 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1371 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1372 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1373 FR64X:$src)), sub_xmm)>;
1374 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1375 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1376 (SUBREG_TO_REG (i64 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1377
1378 // Move low f64 and clear high bits.
1379 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1380 (SUBREG_TO_REG (i32 0),
1381 (VMOVSDZrr (v2f64 (V_SET0)),
1382 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1383
1384 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1385 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1386 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1387
1388 // Extract and store.
1389 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1390 addr:$dst),
1391 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1392 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1393 addr:$dst),
1394 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1395
1396 // Shuffle with VMOVSS
1397 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1398 (VMOVSSZrr (v4i32 VR128X:$src1),
1399 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1400 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1401 (VMOVSSZrr (v4f32 VR128X:$src1),
1402 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1403
1404 // 256-bit variants
1405 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1406 (SUBREG_TO_REG (i32 0),
1407 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1408 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1409 sub_xmm)>;
1410 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1411 (SUBREG_TO_REG (i32 0),
1412 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1413 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1414 sub_xmm)>;
1415
1416 // Shuffle with VMOVSD
1417 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1418 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1419 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1420 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1421 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1422 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1423 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1424 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1425
1426 // 256-bit variants
1427 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1428 (SUBREG_TO_REG (i32 0),
1429 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1430 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1431 sub_xmm)>;
1432 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1433 (SUBREG_TO_REG (i32 0),
1434 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1435 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1436 sub_xmm)>;
1437
1438 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1439 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1440 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1441 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1442 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1443 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1444 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1445 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1446}
1447
1448let AddedComplexity = 15 in
1449def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1450 (ins VR128X:$src),
1451 "vmovq{z}\t{$src, $dst|$dst, $src}",
1452 [(set VR128X:$dst, (v2i64 (X86vzmovl
1453 (v2i64 VR128X:$src))))],
1454 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1455
1456let AddedComplexity = 20 in
1457def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1458 (ins i128mem:$src),
1459 "vmovq{z}\t{$src, $dst|$dst, $src}",
1460 [(set VR128X:$dst, (v2i64 (X86vzmovl
1461 (loadv2i64 addr:$src))))],
1462 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1463 EVEX_CD8<8, CD8VT8>;
1464
1465let Predicates = [HasAVX512] in {
1466 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1467 let AddedComplexity = 20 in {
1468 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1469 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1470 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1471 (VMOV64toPQIZrr GR64:$src)>;
1472 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1473 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1474
1475 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1476 (VMOVDI2PDIZrm addr:$src)>;
1477 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1478 (VMOVDI2PDIZrm addr:$src)>;
1479 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1480 (VMOVZPQILo2PQIZrm addr:$src)>;
1481 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1482 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1483 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1484
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1485 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1486 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1487 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1488 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1489 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1490 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1491 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1492}
1493
1494def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1495 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1496
1497def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1498 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1499
1500def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1501 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1502
1503def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1504 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1505
1506//===----------------------------------------------------------------------===//
1507// AVX-512 - Integer arithmetic
1508//
1509multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1510 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1511 X86MemOperand x86memop, PatFrag scalar_mfrag,
1512 X86MemOperand x86scalar_mop, string BrdcstStr,
1513 OpndItins itins, bit IsCommutable = 0> {
1514 let isCommutable = IsCommutable in
1515 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1516 (ins RC:$src1, RC:$src2),
1517 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1518 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1519 itins.rr>, EVEX_4V;
1520 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1521 (ins RC:$src1, x86memop:$src2),
1522 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1523 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1524 itins.rm>, EVEX_4V;
1525 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1526 (ins RC:$src1, x86scalar_mop:$src2),
1527 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1528 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1529 [(set RC:$dst, (OpNode RC:$src1,
1530 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1531 itins.rm>, EVEX_4V, EVEX_B;
1532}
1533multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1534 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1535 PatFrag memop_frag, X86MemOperand x86memop,
1536 OpndItins itins,
1537 bit IsCommutable = 0> {
1538 let isCommutable = IsCommutable in
1539 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1540 (ins RC:$src1, RC:$src2),
1541 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1542 []>, EVEX_4V, VEX_W;
1543 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1544 (ins RC:$src1, x86memop:$src2),
1545 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1546 []>, EVEX_4V, VEX_W;
1547}
1548
1549defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1550 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1551 EVEX_V512, EVEX_CD8<32, CD8VF>;
1552
1553defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1554 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1555 EVEX_V512, EVEX_CD8<32, CD8VF>;
1556
1557defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1558 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1559 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1560
1561defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1562 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1563 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1564
1565defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1566 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1567 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1568
1569defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1570 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1571 EVEX_V512, EVEX_CD8<64, CD8VF>;
1572
1573defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1574 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1575 EVEX_CD8<64, CD8VF>;
1576
1577def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1578 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1579
1580//===----------------------------------------------------------------------===//
1581// AVX-512 - Unpack Instructions
1582//===----------------------------------------------------------------------===//
1583
1584multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1585 PatFrag mem_frag, RegisterClass RC,
1586 X86MemOperand x86memop, string asm,
1587 Domain d> {
1588 def rr : AVX512PI<opc, MRMSrcReg,
1589 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1590 asm, [(set RC:$dst,
1591 (vt (OpNode RC:$src1, RC:$src2)))],
1592 d>, EVEX_4V, TB;
1593 def rm : AVX512PI<opc, MRMSrcMem,
1594 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1595 asm, [(set RC:$dst,
1596 (vt (OpNode RC:$src1,
1597 (bitconvert (mem_frag addr:$src2)))))],
1598 d>, EVEX_4V, TB;
1599}
1600
1601defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1602 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1603 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1604defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1605 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1606 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1607defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1608 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1609 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1610defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1611 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1612 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1613
1614multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1615 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1616 X86MemOperand x86memop> {
1617 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1618 (ins RC:$src1, RC:$src2),
1619 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1620 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1621 IIC_SSE_UNPCK>, EVEX_4V;
1622 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1623 (ins RC:$src1, x86memop:$src2),
1624 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1625 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1626 (bitconvert (memop_frag addr:$src2)))))],
1627 IIC_SSE_UNPCK>, EVEX_4V;
1628}
1629defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1630 VR512, memopv16i32, i512mem>, EVEX_V512,
1631 EVEX_CD8<32, CD8VF>;
1632defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1633 VR512, memopv8i64, i512mem>, EVEX_V512,
1634 VEX_W, EVEX_CD8<64, CD8VF>;
1635defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1636 VR512, memopv16i32, i512mem>, EVEX_V512,
1637 EVEX_CD8<32, CD8VF>;
1638defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1639 VR512, memopv8i64, i512mem>, EVEX_V512,
1640 VEX_W, EVEX_CD8<64, CD8VF>;
1641//===----------------------------------------------------------------------===//
1642// AVX-512 - PSHUFD
1643//
1644
1645multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1646 SDNode OpNode, PatFrag mem_frag,
1647 X86MemOperand x86memop, ValueType OpVT> {
1648 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1649 (ins RC:$src1, i8imm:$src2),
1650 !strconcat(OpcodeStr,
1651 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1652 [(set RC:$dst,
1653 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1654 EVEX;
1655 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1656 (ins x86memop:$src1, i8imm:$src2),
1657 !strconcat(OpcodeStr,
1658 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1659 [(set RC:$dst,
1660 (OpVT (OpNode (mem_frag addr:$src1),
1661 (i8 imm:$src2))))]>, EVEX;
1662}
1663
1664defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1665 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1666
1667let ExeDomain = SSEPackedSingle in
1668defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1669 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1670 EVEX_CD8<32, CD8VF>;
1671let ExeDomain = SSEPackedDouble in
1672defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1673 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1674 VEX_W, EVEX_CD8<32, CD8VF>;
1675
1676def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1677 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1678def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1679 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1680
1681//===----------------------------------------------------------------------===//
1682// AVX-512 Logical Instructions
1683//===----------------------------------------------------------------------===//
1684
1685defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1686 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1687 EVEX_V512, EVEX_CD8<32, CD8VF>;
1688defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1689 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1690 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1691defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1692 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1693 EVEX_V512, EVEX_CD8<32, CD8VF>;
1694defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1695 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1696 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1697defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1698 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1699 EVEX_V512, EVEX_CD8<32, CD8VF>;
1700defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1701 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1702 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1703defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1704 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1705 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1706defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1707 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1708 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1709
1710//===----------------------------------------------------------------------===//
1711// AVX-512 FP arithmetic
1712//===----------------------------------------------------------------------===//
1713
1714multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1715 SizeItins itins> {
1716 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1717 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1718 EVEX_CD8<32, CD8VT1>;
1719 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1720 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1721 EVEX_CD8<64, CD8VT1>;
1722}
1723
1724let isCommutable = 1 in {
1725defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1726defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1727defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1728defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1729}
1730let isCommutable = 0 in {
1731defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1732defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1733}
1734
1735multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1736 RegisterClass RC, ValueType vt,
1737 X86MemOperand x86memop, PatFrag mem_frag,
1738 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1739 string BrdcstStr,
1740 Domain d, OpndItins itins, bit commutable> {
1741 let isCommutable = commutable in
1742 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1743 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1744 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1745 EVEX_4V;
1746 let mayLoad = 1 in {
1747 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1748 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1749 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1750 itins.rm, d>, EVEX_4V;
1751 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1752 (ins RC:$src1, x86scalar_mop:$src2),
1753 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1754 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1755 [(set RC:$dst, (OpNode RC:$src1,
1756 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1757 itins.rm, d>, EVEX_4V, EVEX_B;
1758 }
1759}
1760
1761defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1762 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1763 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1764
1765defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1766 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1767 SSE_ALU_ITINS_P.d, 1>,
1768 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1769
1770defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1771 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1772 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1773defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1774 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1775 SSE_ALU_ITINS_P.d, 1>,
1776 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1777
1778defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1779 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1780 SSE_ALU_ITINS_P.s, 1>,
1781 EVEX_V512, EVEX_CD8<32, CD8VF>;
1782defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1783 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1784 SSE_ALU_ITINS_P.s, 1>,
1785 EVEX_V512, EVEX_CD8<32, CD8VF>;
1786
1787defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1788 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1789 SSE_ALU_ITINS_P.d, 1>,
1790 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1791defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1792 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1793 SSE_ALU_ITINS_P.d, 1>,
1794 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1795
1796defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1797 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1798 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1799defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1800 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1801 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1802
1803defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1804 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1805 SSE_ALU_ITINS_P.d, 0>,
1806 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1807defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1808 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1809 SSE_ALU_ITINS_P.d, 0>,
1810 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1811
1812//===----------------------------------------------------------------------===//
1813// AVX-512 VPTESTM instructions
1814//===----------------------------------------------------------------------===//
1815
1816multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1817 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1818 SDNode OpNode, ValueType vt> {
1819 def rr : AVX5128I<opc, MRMSrcReg,
1820 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1821 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1822 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1823 def rm : AVX5128I<opc, MRMSrcMem,
1824 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1826 [(set KRC:$dst, (OpNode (vt RC:$src1),
1827 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1828}
1829
1830defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1831 memopv16i32, X86testm, v16i32>, EVEX_V512,
1832 EVEX_CD8<32, CD8VF>;
1833defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1834 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1835 EVEX_CD8<64, CD8VF>;
1836
1837//===----------------------------------------------------------------------===//
1838// AVX-512 Shift instructions
1839//===----------------------------------------------------------------------===//
1840multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1841 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1842 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1843 RegisterClass KRC> {
1844 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1845 (ins RC:$src1, i32i8imm:$src2),
1846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1847 [(set RC:$dst, (vt (OpNode RC:$src1, (i32 imm:$src2))))],
1848 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1849 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1850 (ins KRC:$mask, RC:$src1, i32i8imm:$src2),
1851 !strconcat(OpcodeStr,
1852 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1853 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1854 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1855 (ins x86memop:$src1, i32i8imm:$src2),
1856 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1857 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
1858 (i32 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1859 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1860 (ins KRC:$mask, x86memop:$src1, i32i8imm:$src2),
1861 !strconcat(OpcodeStr,
1862 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1863 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1864}
1865
1866multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1867 RegisterClass RC, ValueType vt, ValueType SrcVT,
1868 PatFrag bc_frag, RegisterClass KRC> {
1869 // src2 is always 128-bit
1870 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1871 (ins RC:$src1, VR128X:$src2),
1872 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1873 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1874 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1875 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1876 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1877 !strconcat(OpcodeStr,
1878 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1879 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1880 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1881 (ins RC:$src1, i128mem:$src2),
1882 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1883 [(set RC:$dst, (vt (OpNode RC:$src1,
1884 (bc_frag (memopv2i64 addr:$src2)))))],
1885 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1886 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1887 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1888 !strconcat(OpcodeStr,
1889 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1890 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1891}
1892
1893defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1894 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1895 EVEX_V512, EVEX_CD8<32, CD8VF>;
1896defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1897 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1898 EVEX_CD8<32, CD8VQ>;
1899
1900defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1901 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1902 EVEX_CD8<64, CD8VF>, VEX_W;
1903defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1904 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1905 EVEX_CD8<64, CD8VQ>, VEX_W;
1906
1907defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1908 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1909 EVEX_CD8<32, CD8VF>;
1910defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1911 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1912 EVEX_CD8<32, CD8VQ>;
1913
1914defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1915 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1916 EVEX_CD8<64, CD8VF>, VEX_W;
1917defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1918 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1919 EVEX_CD8<64, CD8VQ>, VEX_W;
1920
1921defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1922 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1923 EVEX_V512, EVEX_CD8<32, CD8VF>;
1924defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1925 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1926 EVEX_CD8<32, CD8VQ>;
1927
1928defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1929 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1930 EVEX_CD8<64, CD8VF>, VEX_W;
1931defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1932 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1933 EVEX_CD8<64, CD8VQ>, VEX_W;
1934
1935//===-------------------------------------------------------------------===//
1936// Variable Bit Shifts
1937//===-------------------------------------------------------------------===//
1938multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1939 RegisterClass RC, ValueType vt,
1940 X86MemOperand x86memop, PatFrag mem_frag> {
1941 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1942 (ins RC:$src1, RC:$src2),
1943 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1944 [(set RC:$dst,
1945 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1946 EVEX_4V;
1947 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1948 (ins RC:$src1, x86memop:$src2),
1949 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1950 [(set RC:$dst,
1951 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
1952 EVEX_4V;
1953}
1954
1955defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
1956 i512mem, memopv16i32>, EVEX_V512,
1957 EVEX_CD8<32, CD8VF>;
1958defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
1959 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1960 EVEX_CD8<64, CD8VF>;
1961defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
1962 i512mem, memopv16i32>, EVEX_V512,
1963 EVEX_CD8<32, CD8VF>;
1964defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
1965 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1966 EVEX_CD8<64, CD8VF>;
1967defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
1968 i512mem, memopv16i32>, EVEX_V512,
1969 EVEX_CD8<32, CD8VF>;
1970defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
1971 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1972 EVEX_CD8<64, CD8VF>;
1973
1974//===----------------------------------------------------------------------===//
1975// AVX-512 - MOVDDUP
1976//===----------------------------------------------------------------------===//
1977
1978multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
1979 X86MemOperand x86memop, PatFrag memop_frag> {
1980def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1981 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1982 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
1983def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1984 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1985 [(set RC:$dst,
1986 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
1987}
1988
1989defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
1990 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1991def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
1992 (VMOVDDUPZrm addr:$src)>;
1993
1994def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
1995 (ins VR128X:$src1, VR128X:$src2),
1996 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1997 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
1998 IIC_SSE_MOV_LH>, EVEX_4V;
1999def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2000 (ins VR128X:$src1, VR128X:$src2),
2001 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2002 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2003 IIC_SSE_MOV_LH>, EVEX_4V;
2004
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2005let Predicates = [HasAVX512] in {
2006 // MOVLHPS patterns
2007 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2008 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2009 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2010 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2011
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2012 // MOVHLPS patterns
2013 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2014 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2015}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2016
2017//===----------------------------------------------------------------------===//
2018// FMA - Fused Multiply Operations
2019//
2020let Constraints = "$src1 = $dst" in {
2021multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2022 RegisterClass RC, X86MemOperand x86memop,
2023 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2024 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2025 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2026 (ins RC:$src1, RC:$src2, RC:$src3),
2027 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2028 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2029
2030 let mayLoad = 1 in
2031 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2032 (ins RC:$src1, RC:$src2, x86memop:$src3),
2033 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2034 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2035 (mem_frag addr:$src3))))]>;
2036 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2037 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2038 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2039 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2040 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2041 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2042}
2043} // Constraints = "$src1 = $dst"
2044
2045let ExeDomain = SSEPackedSingle in {
2046 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2047 memopv16f32, f32mem, loadf32, "{1to16}",
2048 X86Fmadd, v16f32>, EVEX_V512,
2049 EVEX_CD8<32, CD8VF>;
2050 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2051 memopv16f32, f32mem, loadf32, "{1to16}",
2052 X86Fmsub, v16f32>, EVEX_V512,
2053 EVEX_CD8<32, CD8VF>;
2054 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2055 memopv16f32, f32mem, loadf32, "{1to16}",
2056 X86Fmaddsub, v16f32>,
2057 EVEX_V512, EVEX_CD8<32, CD8VF>;
2058 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2059 memopv16f32, f32mem, loadf32, "{1to16}",
2060 X86Fmsubadd, v16f32>,
2061 EVEX_V512, EVEX_CD8<32, CD8VF>;
2062 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2063 memopv16f32, f32mem, loadf32, "{1to16}",
2064 X86Fnmadd, v16f32>, EVEX_V512,
2065 EVEX_CD8<32, CD8VF>;
2066 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2067 memopv16f32, f32mem, loadf32, "{1to16}",
2068 X86Fnmsub, v16f32>, EVEX_V512,
2069 EVEX_CD8<32, CD8VF>;
2070}
2071let ExeDomain = SSEPackedDouble in {
2072 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2073 memopv8f64, f64mem, loadf64, "{1to8}",
2074 X86Fmadd, v8f64>, EVEX_V512,
2075 VEX_W, EVEX_CD8<64, CD8VF>;
2076 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2077 memopv8f64, f64mem, loadf64, "{1to8}",
2078 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2079 EVEX_CD8<64, CD8VF>;
2080 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2081 memopv8f64, f64mem, loadf64, "{1to8}",
2082 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2083 EVEX_CD8<64, CD8VF>;
2084 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2085 memopv8f64, f64mem, loadf64, "{1to8}",
2086 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2087 EVEX_CD8<64, CD8VF>;
2088 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2089 memopv8f64, f64mem, loadf64, "{1to8}",
2090 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2091 EVEX_CD8<64, CD8VF>;
2092 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2093 memopv8f64, f64mem, loadf64, "{1to8}",
2094 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2095 EVEX_CD8<64, CD8VF>;
2096}
2097
2098let Constraints = "$src1 = $dst" in {
2099multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2100 RegisterClass RC, X86MemOperand x86memop,
2101 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2102 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2103 let mayLoad = 1 in
2104 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2105 (ins RC:$src1, RC:$src3, x86memop:$src2),
2106 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2107 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2108 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2109 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2110 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2111 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2112 [(set RC:$dst, (OpNode RC:$src1,
2113 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2114}
2115} // Constraints = "$src1 = $dst"
2116
2117
2118let ExeDomain = SSEPackedSingle in {
2119 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2120 memopv16f32, f32mem, loadf32, "{1to16}",
2121 X86Fmadd, v16f32>, EVEX_V512,
2122 EVEX_CD8<32, CD8VF>;
2123 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2124 memopv16f32, f32mem, loadf32, "{1to16}",
2125 X86Fmsub, v16f32>, EVEX_V512,
2126 EVEX_CD8<32, CD8VF>;
2127 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2128 memopv16f32, f32mem, loadf32, "{1to16}",
2129 X86Fmaddsub, v16f32>,
2130 EVEX_V512, EVEX_CD8<32, CD8VF>;
2131 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2132 memopv16f32, f32mem, loadf32, "{1to16}",
2133 X86Fmsubadd, v16f32>,
2134 EVEX_V512, EVEX_CD8<32, CD8VF>;
2135 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2136 memopv16f32, f32mem, loadf32, "{1to16}",
2137 X86Fnmadd, v16f32>, EVEX_V512,
2138 EVEX_CD8<32, CD8VF>;
2139 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2140 memopv16f32, f32mem, loadf32, "{1to16}",
2141 X86Fnmsub, v16f32>, EVEX_V512,
2142 EVEX_CD8<32, CD8VF>;
2143}
2144let ExeDomain = SSEPackedDouble in {
2145 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2146 memopv8f64, f64mem, loadf64, "{1to8}",
2147 X86Fmadd, v8f64>, EVEX_V512,
2148 VEX_W, EVEX_CD8<64, CD8VF>;
2149 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2150 memopv8f64, f64mem, loadf64, "{1to8}",
2151 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2152 EVEX_CD8<64, CD8VF>;
2153 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2154 memopv8f64, f64mem, loadf64, "{1to8}",
2155 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2156 EVEX_CD8<64, CD8VF>;
2157 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2158 memopv8f64, f64mem, loadf64, "{1to8}",
2159 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2160 EVEX_CD8<64, CD8VF>;
2161 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2162 memopv8f64, f64mem, loadf64, "{1to8}",
2163 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2164 EVEX_CD8<64, CD8VF>;
2165 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2166 memopv8f64, f64mem, loadf64, "{1to8}",
2167 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2168 EVEX_CD8<64, CD8VF>;
2169}
2170
2171// Scalar FMA
2172let Constraints = "$src1 = $dst" in {
2173multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2174 RegisterClass RC, ValueType OpVT,
2175 X86MemOperand x86memop, Operand memop,
2176 PatFrag mem_frag> {
2177 let isCommutable = 1 in
2178 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2179 (ins RC:$src1, RC:$src2, RC:$src3),
2180 !strconcat(OpcodeStr,
2181 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2182 [(set RC:$dst,
2183 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2184 let mayLoad = 1 in
2185 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2186 (ins RC:$src1, RC:$src2, f128mem:$src3),
2187 !strconcat(OpcodeStr,
2188 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2189 [(set RC:$dst,
2190 (OpVT (OpNode RC:$src2, RC:$src1,
2191 (mem_frag addr:$src3))))]>;
2192}
2193
2194} // Constraints = "$src1 = $dst"
2195
2196defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2197 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2198defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2199 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2200defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2201 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2202defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2203 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2204defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2205 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2206defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2207 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2208defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2209 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2210defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2211 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2212
2213//===----------------------------------------------------------------------===//
2214// AVX-512 Scalar convert from sign integer to float/double
2215//===----------------------------------------------------------------------===//
2216
2217multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2218 X86MemOperand x86memop, string asm> {
2219let neverHasSideEffects = 1 in {
2220 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2221 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, EVEX_4V;
2222 let mayLoad = 1 in
2223 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2224 (ins DstRC:$src1, x86memop:$src),
2225 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, EVEX_4V;
2226} // neverHasSideEffects = 1
2227}
2228
2229defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2230 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2231defm VCVTSI2SS64Z : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
2232 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2233defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2234 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2235defm VCVTSI2SD64Z : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
2236 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2237
2238def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2239 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2240def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2241 (VCVTSI2SS64Zrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2242def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2243 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2244def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2245 (VCVTSI2SD64Zrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2246
2247def : Pat<(f32 (sint_to_fp GR32:$src)),
2248 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2249def : Pat<(f32 (sint_to_fp GR64:$src)),
2250 (VCVTSI2SS64Zrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2251def : Pat<(f64 (sint_to_fp GR32:$src)),
2252 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2253def : Pat<(f64 (sint_to_fp GR64:$src)),
2254 (VCVTSI2SD64Zrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2255
2256
2257//===----------------------------------------------------------------------===//
2258// AVX-512 Convert form float to double and back
2259//===----------------------------------------------------------------------===//
2260let neverHasSideEffects = 1 in {
2261def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2262 (ins FR32X:$src1, FR32X:$src2),
2263 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2264 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2265let mayLoad = 1 in
2266def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2267 (ins FR32X:$src1, f32mem:$src2),
2268 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2269 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2270 EVEX_CD8<32, CD8VT1>;
2271
2272// Convert scalar double to scalar single
2273def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2274 (ins FR64X:$src1, FR64X:$src2),
2275 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2276 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2277let mayLoad = 1 in
2278def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2279 (ins FR64X:$src1, f64mem:$src2),
2280 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2281 []>, EVEX_4V, VEX_LIG, VEX_W,
2282 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2283}
2284
2285def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2286 Requires<[HasAVX512]>;
2287def : Pat<(fextend (loadf32 addr:$src)),
2288 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2289
2290def : Pat<(extloadf32 addr:$src),
2291 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2292 Requires<[HasAVX512, OptForSize]>;
2293
2294def : Pat<(extloadf32 addr:$src),
2295 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2296 Requires<[HasAVX512, OptForSpeed]>;
2297
2298def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2299 Requires<[HasAVX512]>;
2300
2301multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2302 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2303 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2304 Domain d> {
2305let neverHasSideEffects = 1 in {
2306 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2307 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2308 [(set DstRC:$dst,
2309 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2310 let mayLoad = 1 in
2311 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2312 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2313 [(set DstRC:$dst,
2314 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2315} // neverHasSideEffects = 1
2316}
2317
2318defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2319 memopv8f64, f512mem, v8f32, v8f64,
2320 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2321 EVEX_CD8<64, CD8VF>;
2322
2323defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2324 memopv4f64, f256mem, v8f64, v8f32,
2325 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2326def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2327 (VCVTPS2PDZrm addr:$src)>;
2328
2329//===----------------------------------------------------------------------===//
2330// AVX-512 Vector convert from sign integer to float/double
2331//===----------------------------------------------------------------------===//
2332
2333defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2334 memopv8i64, i512mem, v16f32, v16i32,
2335 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2336
2337defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2338 memopv4i64, i256mem, v8f64, v8i32,
2339 SSEPackedDouble>, EVEX_V512, XS,
2340 EVEX_CD8<32, CD8VH>;
2341
2342defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2343 memopv16f32, f512mem, v16i32, v16f32,
2344 SSEPackedSingle>, EVEX_V512, XS,
2345 EVEX_CD8<32, CD8VF>;
2346
2347defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2348 memopv8f64, f512mem, v8i32, v8f64,
2349 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2350 EVEX_CD8<64, CD8VF>;
2351
2352defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2353 memopv16f32, f512mem, v16i32, v16f32,
2354 SSEPackedSingle>, EVEX_V512,
2355 EVEX_CD8<32, CD8VF>;
2356
2357defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2358 memopv8f64, f512mem, v8i32, v8f64,
2359 SSEPackedDouble>, EVEX_V512, VEX_W,
2360 EVEX_CD8<64, CD8VF>;
2361
2362defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2363 memopv4i64, f256mem, v8f64, v8i32,
2364 SSEPackedDouble>, EVEX_V512, XS,
2365 EVEX_CD8<32, CD8VH>;
2366
2367defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2368 memopv16i32, f512mem, v16f32, v16i32,
2369 SSEPackedSingle>, EVEX_V512, XD,
2370 EVEX_CD8<32, CD8VF>;
2371
2372def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2373 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2374 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2375
2376
2377def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2378 (VCVTDQ2PSZrr VR512:$src)>;
2379def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2380 (VCVTDQ2PSZrm addr:$src)>;
2381
2382def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2383 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2384 [(set VR512:$dst,
2385 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2386 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2387def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2388 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2389 [(set VR512:$dst,
2390 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2391 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2392
2393
2394let Predicates = [HasAVX512] in {
2395 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2396 (VCVTPD2PSZrm addr:$src)>;
2397 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2398 (VCVTPS2PDZrm addr:$src)>;
2399}
2400
2401let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2402 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2403 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2404 EVEX_CD8<32, CD8VT1>;
2405 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2406 "ucomisd{z}">, TB, OpSize, EVEX,
2407 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2408 let Pattern = []<dag> in {
2409 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2410 "comiss{z}">, TB, EVEX, VEX_LIG,
2411 EVEX_CD8<32, CD8VT1>;
2412 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2413 "comisd{z}">, TB, OpSize, EVEX,
2414 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2415 }
2416 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2417 load, "ucomiss">, TB, EVEX, VEX_LIG,
2418 EVEX_CD8<32, CD8VT1>;
2419 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2420 load, "ucomisd">, TB, OpSize, EVEX,
2421 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2422
2423 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2424 load, "comiss">, TB, EVEX, VEX_LIG,
2425 EVEX_CD8<32, CD8VT1>;
2426 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2427 load, "comisd">, TB, OpSize, EVEX,
2428 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2429}
2430
2431/// avx512_unop_p - AVX-512 unops in packed form.
2432multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2433 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2434 !strconcat(OpcodeStr,
2435 "ps\t{$src, $dst|$dst, $src}"),
2436 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2437 EVEX, EVEX_V512;
2438 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2439 !strconcat(OpcodeStr,
2440 "ps\t{$src, $dst|$dst, $src}"),
2441 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2442 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2443 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2444 !strconcat(OpcodeStr,
2445 "pd\t{$src, $dst|$dst, $src}"),
2446 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2447 EVEX, EVEX_V512, VEX_W;
2448 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2449 !strconcat(OpcodeStr,
2450 "pd\t{$src, $dst|$dst, $src}"),
2451 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2452 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2453}
2454
2455/// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2456multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2457 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2458 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2459 !strconcat(OpcodeStr,
2460 "ps\t{$src, $dst|$dst, $src}"),
2461 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2462 EVEX, EVEX_V512;
2463 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2464 !strconcat(OpcodeStr,
2465 "ps\t{$src, $dst|$dst, $src}"),
2466 [(set VR512:$dst,
2467 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2468 EVEX_V512, EVEX_CD8<32, CD8VF>;
2469 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2470 !strconcat(OpcodeStr,
2471 "pd\t{$src, $dst|$dst, $src}"),
2472 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2473 EVEX, EVEX_V512, VEX_W;
2474 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2475 !strconcat(OpcodeStr,
2476 "pd\t{$src, $dst|$dst, $src}"),
2477 [(set VR512:$dst,
2478 (V8F64Int (memopv8f64 addr:$src)))]>,
2479 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2480}
2481
2482/// avx512_fp_unop_s - AVX-512 unops in scalar form.
2483multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr,
2484 Intrinsic F32Int, Intrinsic F64Int> {
2485 let hasSideEffects = 0 in {
2486 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2487 (ins FR32X:$src1, FR32X:$src2),
2488 !strconcat(OpcodeStr,
2489 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2490 []>, EVEX_4V;
2491 let mayLoad = 1 in {
2492 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2493 (ins FR32X:$src1, f32mem:$src2),
2494 !strconcat(OpcodeStr,
2495 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2496 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2497 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2498 (ins VR128X:$src1, ssmem:$src2),
2499 !strconcat(OpcodeStr,
2500 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2501 [(set VR128X:$dst, (F32Int VR128X:$src1, sse_load_f32:$src2))]>,
2502 EVEX_4V, EVEX_CD8<32, CD8VT1>;
2503 }
2504 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2505 (ins FR64X:$src1, FR64X:$src2),
2506 !strconcat(OpcodeStr,
2507 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2508 EVEX_4V, VEX_W;
2509 let mayLoad = 1 in {
2510 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2511 (ins FR64X:$src1, f64mem:$src2),
2512 !strconcat(OpcodeStr,
2513 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2514 EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
2515 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2516 (ins VR128X:$src1, sdmem:$src2),
2517 !strconcat(OpcodeStr,
2518 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2519 [(set VR128X:$dst, (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2520 EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
2521 }
2522}
2523}
2524
2525defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14", int_x86_avx512_rcp14_ss,
2526 int_x86_avx512_rcp14_sd>,
2527 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2528 avx512_fp_unop_p_int<0x4C, "vrcp14",
2529 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2530
2531defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14", int_x86_avx512_rsqrt14_ss,
2532 int_x86_avx512_rsqrt14_sd>,
2533 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2534 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2535 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2536
2537multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2538 Intrinsic V16F32Int, Intrinsic V8F64Int,
2539 OpndItins itins_s, OpndItins itins_d> {
2540 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2541 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2542 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2543 EVEX, EVEX_V512;
2544
2545 let mayLoad = 1 in
2546 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2547 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2548 [(set VR512:$dst,
2549 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2550 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2551
2552 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2553 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2554 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2555 EVEX, EVEX_V512;
2556
2557 let mayLoad = 1 in
2558 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2559 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2560 [(set VR512:$dst, (OpNode
2561 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2562 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2563
2564 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2565 !strconcat(OpcodeStr,
2566 "ps\t{$src, $dst|$dst, $src}"),
2567 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2568 EVEX, EVEX_V512;
2569 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2570 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2571 [(set VR512:$dst,
2572 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2573 EVEX_V512, EVEX_CD8<32, CD8VF>;
2574 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2575 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2576 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2577 EVEX, EVEX_V512, VEX_W;
2578 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2579 !strconcat(OpcodeStr,
2580 "pd\t{$src, $dst|$dst, $src}"),
2581 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2582 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2583}
2584
2585multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2586 Intrinsic F32Int, Intrinsic F64Int,
2587 OpndItins itins_s, OpndItins itins_d> {
2588 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2589 (ins FR32X:$src1, FR32X:$src2),
2590 !strconcat(OpcodeStr,
2591 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2592 [], itins_s.rr>, XS, EVEX_4V;
2593 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2594 (ins VR128X:$src1, VR128X:$src2),
2595 !strconcat(OpcodeStr,
2596 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2597 [(set VR128X:$dst,
2598 (F32Int VR128X:$src1, VR128X:$src2))],
2599 itins_s.rr>, XS, EVEX_4V;
2600 let mayLoad = 1 in {
2601 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2602 (ins FR32X:$src1, f32mem:$src2),
2603 !strconcat(OpcodeStr,
2604 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2605 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2606 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2607 (ins VR128X:$src1, ssmem:$src2),
2608 !strconcat(OpcodeStr,
2609 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2610 [(set VR128X:$dst,
2611 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2612 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2613 }
2614 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2615 (ins FR64X:$src1, FR64X:$src2),
2616 !strconcat(OpcodeStr,
2617 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2618 XD, EVEX_4V, VEX_W;
2619 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2620 (ins VR128X:$src1, VR128X:$src2),
2621 !strconcat(OpcodeStr,
2622 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2623 [(set VR128X:$dst,
2624 (F64Int VR128X:$src1, VR128X:$src2))],
2625 itins_s.rr>, XD, EVEX_4V, VEX_W;
2626 let mayLoad = 1 in {
2627 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2628 (ins FR64X:$src1, f64mem:$src2),
2629 !strconcat(OpcodeStr,
2630 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2631 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2632 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2633 (ins VR128X:$src1, sdmem:$src2),
2634 !strconcat(OpcodeStr,
2635 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2636 [(set VR128X:$dst,
2637 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2638 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2639 }
2640}
2641
2642
2643defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2644 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2645 SSE_SQRTSS, SSE_SQRTSD>,
2646 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2647 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2648 SSE_SQRTPS, SSE_SQRTPD>;
2649
2650def : Pat<(f32 (fsqrt FR32X:$src)),
2651 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2652def : Pat<(f32 (fsqrt (load addr:$src))),
2653 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2654 Requires<[OptForSize]>;
2655def : Pat<(f64 (fsqrt FR64X:$src)),
2656 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2657def : Pat<(f64 (fsqrt (load addr:$src))),
2658 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2659 Requires<[OptForSize]>;
2660
2661def : Pat<(f32 (X86frsqrt FR32X:$src)),
2662 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2663def : Pat<(f32 (X86frsqrt (load addr:$src))),
2664 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2665 Requires<[OptForSize]>;
2666
2667def : Pat<(f32 (X86frcp FR32X:$src)),
2668 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2669def : Pat<(f32 (X86frcp (load addr:$src))),
2670 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2671 Requires<[OptForSize]>;
2672
2673multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2674 X86MemOperand x86memop, RegisterClass RC,
2675 PatFrag mem_frag32, PatFrag mem_frag64,
2676 Intrinsic V4F32Int, Intrinsic V2F64Int,
2677 CD8VForm VForm> {
2678let ExeDomain = SSEPackedSingle in {
2679 // Intrinsic operation, reg.
2680 // Vector intrinsic operation, reg
2681 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2682 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2683 !strconcat(OpcodeStr,
2684 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2685 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2686
2687 // Vector intrinsic operation, mem
2688 def PSm : AVX512AIi8<opcps, MRMSrcMem,
2689 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2690 !strconcat(OpcodeStr,
2691 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2692 [(set RC:$dst,
2693 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
2694 EVEX_CD8<32, VForm>;
2695} // ExeDomain = SSEPackedSingle
2696
2697let ExeDomain = SSEPackedDouble in {
2698 // Vector intrinsic operation, reg
2699 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
2700 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2701 !strconcat(OpcodeStr,
2702 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2703 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
2704
2705 // Vector intrinsic operation, mem
2706 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
2707 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2708 !strconcat(OpcodeStr,
2709 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2710 [(set RC:$dst,
2711 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
2712 EVEX_CD8<64, VForm>;
2713} // ExeDomain = SSEPackedDouble
2714}
2715
2716multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
2717 string OpcodeStr,
2718 Intrinsic F32Int,
2719 Intrinsic F64Int> {
2720let ExeDomain = GenericDomain in {
2721 // Operation, reg.
2722 let hasSideEffects = 0 in
2723 def SSr : AVX512AIi8<opcss, MRMSrcReg,
2724 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
2725 !strconcat(OpcodeStr,
2726 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2727 []>;
2728
2729 // Intrinsic operation, reg.
2730 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
2731 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2732 !strconcat(OpcodeStr,
2733 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2734 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
2735
2736 // Intrinsic operation, mem.
2737 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
2738 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
2739 !strconcat(OpcodeStr,
2740 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2741 [(set VR128X:$dst, (F32Int VR128X:$src1,
2742 sse_load_f32:$src2, imm:$src3))]>,
2743 EVEX_CD8<32, CD8VT1>;
2744
2745 // Operation, reg.
2746 let hasSideEffects = 0 in
2747 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
2748 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
2749 !strconcat(OpcodeStr,
2750 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2751 []>, VEX_W;
2752
2753 // Intrinsic operation, reg.
2754 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
2755 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2756 !strconcat(OpcodeStr,
2757 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2758 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
2759 VEX_W;
2760
2761 // Intrinsic operation, mem.
2762 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
2763 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
2764 !strconcat(OpcodeStr,
2765 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2766 [(set VR128X:$dst,
2767 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
2768 VEX_W, EVEX_CD8<64, CD8VT1>;
2769} // ExeDomain = GenericDomain
2770}
2771
2772let Predicates = [HasAVX512] in {
2773 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
2774 int_x86_avx512_rndscale_ss,
2775 int_x86_avx512_rndscale_sd>, EVEX_4V;
2776
2777 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
2778 memopv16f32, memopv8f64,
2779 int_x86_avx512_rndscale_ps_512,
2780 int_x86_avx512_rndscale_pd_512, CD8VF>,
2781 EVEX, EVEX_V512;
2782}
2783
2784def : Pat<(ffloor FR32X:$src),
2785 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
2786def : Pat<(f64 (ffloor FR64X:$src)),
2787 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
2788def : Pat<(f32 (fnearbyint FR32X:$src)),
2789 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
2790def : Pat<(f64 (fnearbyint FR64X:$src)),
2791 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
2792def : Pat<(f32 (fceil FR32X:$src)),
2793 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
2794def : Pat<(f64 (fceil FR64X:$src)),
2795 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
2796def : Pat<(f32 (frint FR32X:$src)),
2797 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
2798def : Pat<(f64 (frint FR64X:$src)),
2799 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
2800def : Pat<(f32 (ftrunc FR32X:$src)),
2801 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
2802def : Pat<(f64 (ftrunc FR64X:$src)),
2803 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
2804
2805def : Pat<(v16f32 (ffloor VR512:$src)),
2806 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
2807def : Pat<(v16f32 (fnearbyint VR512:$src)),
2808 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
2809def : Pat<(v16f32 (fceil VR512:$src)),
2810 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
2811def : Pat<(v16f32 (frint VR512:$src)),
2812 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
2813def : Pat<(v16f32 (ftrunc VR512:$src)),
2814 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
2815
2816def : Pat<(v8f64 (ffloor VR512:$src)),
2817 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
2818def : Pat<(v8f64 (fnearbyint VR512:$src)),
2819 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
2820def : Pat<(v8f64 (fceil VR512:$src)),
2821 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
2822def : Pat<(v8f64 (frint VR512:$src)),
2823 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
2824def : Pat<(v8f64 (ftrunc VR512:$src)),
2825 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
2826
2827//-------------------------------------------------
2828// Integer truncate and extend operations
2829//-------------------------------------------------
2830
2831multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
2832 RegisterClass dstRC, RegisterClass srcRC,
2833 RegisterClass KRC, X86MemOperand x86memop> {
2834 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
2835 (ins srcRC:$src),
2836 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2837 []>, EVEX;
2838
2839 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
2840 (ins KRC:$mask, srcRC:$src),
2841 !strconcat(OpcodeStr,
2842 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2843 []>, EVEX, EVEX_KZ;
2844
2845 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
2846 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2847 []>, EVEX;
2848}
2849defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
2850 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
2851defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
2852 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
2853defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
2854 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
2855defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
2856 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
2857defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
2858 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
2859defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
2860 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
2861defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
2862 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2863defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
2864 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2865defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
2866 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2867defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
2868 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
2869defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
2870 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
2871defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
2872 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
2873defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
2874 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
2875defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
2876 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
2877defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
2878 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
2879
2880def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
2881def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
2882def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
2883def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
2884def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
2885
2886def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
2887 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
2888def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
2889 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
2890def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
2891 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
2892def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
2893 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
2894
2895
2896multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
2897 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
2898 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
2899
2900 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
2901 (ins SrcRC:$src),
2902 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2903 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
2904 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
2905 (ins x86memop:$src),
2906 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2907 [(set DstRC:$dst,
2908 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
2909 EVEX;
2910}
2911
2912defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
2913 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
2914 EVEX_CD8<8, CD8VQ>;
2915defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
2916 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
2917 EVEX_CD8<8, CD8VO>;
2918defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
2919 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
2920 EVEX_CD8<16, CD8VH>;
2921defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
2922 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
2923 EVEX_CD8<16, CD8VQ>;
2924defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
2925 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
2926 EVEX_CD8<32, CD8VH>;
2927
2928defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
2929 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
2930 EVEX_CD8<8, CD8VQ>;
2931defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
2932 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
2933 EVEX_CD8<8, CD8VO>;
2934defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
2935 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
2936 EVEX_CD8<16, CD8VH>;
2937defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
2938 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
2939 EVEX_CD8<16, CD8VQ>;
2940defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
2941 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
2942 EVEX_CD8<32, CD8VH>;
2943
2944//===----------------------------------------------------------------------===//
2945// GATHER - SCATTER Operations
2946
2947multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2948 RegisterClass RC, X86MemOperand memop> {
2949let mayLoad = 1,
2950 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
2951 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
2952 (ins RC:$src1, KRC:$mask, memop:$src2),
2953 !strconcat(OpcodeStr,
2954 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
2955 []>, EVEX, EVEX_K;
2956}
2957defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
2958 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2959defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
2960 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2961
2962defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
2963 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2964defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
2965 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2966
2967defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
2968 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2969defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
2970 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2971
2972defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
2973 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2974defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
2975 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2976
2977multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2978 RegisterClass RC, X86MemOperand memop> {
2979let mayStore = 1, Constraints = "$mask = $mask_wb" in
2980 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
2981 (ins memop:$dst, KRC:$mask, RC:$src2),
2982 !strconcat(OpcodeStr,
2983 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
2984 []>, EVEX, EVEX_K;
2985}
2986
2987defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
2988 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2989defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
2990 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2991
2992defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
2993 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2994defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
2995 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2996
2997defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
2998 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2999defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3000 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3001
3002defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3003 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3004defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3005 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3006
3007//===----------------------------------------------------------------------===//
3008// VSHUFPS - VSHUFPD Operations
3009
3010multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3011 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3012 Domain d> {
3013 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3014 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3015 !strconcat(OpcodeStr,
3016 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3017 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3018 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3019 EVEX_4V, TB, Sched<[WriteShuffleLd, ReadAfterLd]>;
3020 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3021 (ins RC:$src1, RC:$src2, i8imm:$src3),
3022 !strconcat(OpcodeStr,
3023 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3024 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3025 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3026 EVEX_4V, TB, Sched<[WriteShuffle]>;
3027}
3028
3029defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3030 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3031defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3032 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3033
3034
3035multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3036 X86MemOperand x86memop> {
3037 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3038 (ins RC:$src1, RC:$src2, i8imm:$src3),
3039 !strconcat(OpcodeStr,
3040 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3041 []>, EVEX_4V;
3042 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3043 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3044 !strconcat(OpcodeStr,
3045 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3046 []>, EVEX_4V;
3047}
3048defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3049 EVEX_V512, EVEX_CD8<32, CD8VF>;
3050defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3051 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3052
3053def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3054 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3055def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3056 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3057def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3058 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3059def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3060 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3061
3062multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3063 X86MemOperand x86memop> {
3064 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3065 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3066 EVEX;
3067 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3068 (ins x86memop:$src),
3069 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3070 EVEX;
3071}
3072
3073defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3074 EVEX_CD8<32, CD8VF>;
3075defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3076 EVEX_CD8<64, CD8VF>;
3077