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gerrit-public.fairphone.software / toolchain / llvm-project / b4adf55e0f050a494cc0c9a98b0bd46e8e30070a / . / llvm / test / CodeGen / ARM / fmscs.ll
blob: 5aff74c4cc2b36291558e1f1e81d0473da1b9211 [file] [log] [blame]
Saleem Abdulrasool72587352014-04-03 16:01:44 +0000[diff] [blame]1; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s -check-prefix=VFP2
2; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON
3; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8
David Goodwin3b9c52c2009-08-04 17:53:06 +0000[diff] [blame]4
Evan Cheng2d59ee32010-11-12 20:32:20 +0000[diff] [blame]5define float @t1(float %acc, float %a, float %b) {
David Goodwin3b9c52c2009-08-04 17:53:06 +0000[diff] [blame]6entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]7; VFP2-LABEL: t1:
Evan Cheng2d59ee32010-11-12 20:32:20 +0000[diff] [blame]8; VFP2: vnmls.f32
9
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]10; NEON-LABEL: t1:
Evan Cheng2d59ee32010-11-12 20:32:20 +0000[diff] [blame]11; NEON: vnmls.f32
12
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]13; A8-LABEL: t1:
Evan Cheng2d59ee32010-11-12 20:32:20 +0000[diff] [blame]14; A8: vmul.f32
15; A8: vsub.f32
David Goodwin3b9c52c2009-08-04 17:53:06 +0000[diff] [blame]16 %0 = fmul float %a, %b
17 %1 = fsub float %0, %acc
18 ret float %1
19}
20
Evan Cheng2d59ee32010-11-12 20:32:20 +0000[diff] [blame]21define double @t2(double %acc, double %a, double %b) {
22entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]23; VFP2-LABEL: t2:
Evan Cheng2d59ee32010-11-12 20:32:20 +0000[diff] [blame]24; VFP2: vnmls.f64
Edward O'Callaghan21d7e8a2009-11-22 14:23:33 +0000[diff] [blame]25
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]26; NEON-LABEL: t2:
Evan Cheng2d59ee32010-11-12 20:32:20 +0000[diff] [blame]27; NEON: vnmls.f64
Edward O'Callaghan21d7e8a2009-11-22 14:23:33 +0000[diff] [blame]28
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]29; A8-LABEL: t2:
Evan Cheng2d59ee32010-11-12 20:32:20 +0000[diff] [blame]30; A8: vmul.f64
31; A8: vsub.f64
32 %0 = fmul double %a, %b
33 %1 = fsub double %0, %acc
34 ret double %1
35}