Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / eb61f388fae0f62c5692512b2605336149fa026f / . / llvm / test / CodeGen / AMDGPU / amdgpu-codegenprepare-i16-to-i32.ll
blob: a4a882ed844a3f5094b13076e5cdce6d62d7a30c [file] [log] [blame]
Konstantin Zhuravlyove14df4b2016-09-28 20:05:39 +0000[diff] [blame]1; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare %s | FileCheck -check-prefix=SI %s
2; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck -check-prefix=VI %s
3
4; SI-NOT: zext
5; SI-NOT: sext
6; SI-NOT: trunc
7
8; VI-LABEL: @add_i16(
9; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
10; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
11; VI: %[[R_32:[0-9]+]] = add i32 %[[A_32]], %[[B_32]]
12; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
13; VI: ret i16 %[[R_16]]
14define i16 @add_i16(i16 %a, i16 %b) {
15 %r = add i16 %a, %b
16 ret i16 %r
17}
18
19; VI-LABEL: @add_nsw_i16(
20; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
21; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
22; VI: %[[R_32:[0-9]+]] = add nsw i32 %[[A_32]], %[[B_32]]
23; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
24; VI: ret i16 %[[R_16]]
25define i16 @add_nsw_i16(i16 %a, i16 %b) {
26 %r = add nsw i16 %a, %b
27 ret i16 %r
28}
29
30; VI-LABEL: @add_nuw_i16(
31; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
32; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
33; VI: %[[R_32:[0-9]+]] = add nuw i32 %[[A_32]], %[[B_32]]
34; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
35; VI: ret i16 %[[R_16]]
36define i16 @add_nuw_i16(i16 %a, i16 %b) {
37 %r = add nuw i16 %a, %b
38 ret i16 %r
39}
40
41; VI-LABEL: @add_nuw_nsw_i16(
42; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
43; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
44; VI: %[[R_32:[0-9]+]] = add nuw nsw i32 %[[A_32]], %[[B_32]]
45; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
46; VI: ret i16 %[[R_16]]
47define i16 @add_nuw_nsw_i16(i16 %a, i16 %b) {
48 %r = add nuw nsw i16 %a, %b
49 ret i16 %r
50}
51
52; VI-LABEL: @sub_i16(
53; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
54; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
55; VI: %[[R_32:[0-9]+]] = sub i32 %[[A_32]], %[[B_32]]
56; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
57; VI: ret i16 %[[R_16]]
58define i16 @sub_i16(i16 %a, i16 %b) {
59 %r = sub i16 %a, %b
60 ret i16 %r
61}
62
63; VI-LABEL: @sub_nsw_i16(
64; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
65; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
66; VI: %[[R_32:[0-9]+]] = sub nsw i32 %[[A_32]], %[[B_32]]
67; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
68; VI: ret i16 %[[R_16]]
69define i16 @sub_nsw_i16(i16 %a, i16 %b) {
70 %r = sub nsw i16 %a, %b
71 ret i16 %r
72}
73
74; VI-LABEL: @sub_nuw_i16(
75; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
76; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
77; VI: %[[R_32:[0-9]+]] = sub nuw i32 %[[A_32]], %[[B_32]]
78; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
79; VI: ret i16 %[[R_16]]
80define i16 @sub_nuw_i16(i16 %a, i16 %b) {
81 %r = sub nuw i16 %a, %b
82 ret i16 %r
83}
84
85; VI-LABEL: @sub_nuw_nsw_i16(
86; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
87; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
88; VI: %[[R_32:[0-9]+]] = sub nuw nsw i32 %[[A_32]], %[[B_32]]
89; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
90; VI: ret i16 %[[R_16]]
91define i16 @sub_nuw_nsw_i16(i16 %a, i16 %b) {
92 %r = sub nuw nsw i16 %a, %b
93 ret i16 %r
94}
95
96; VI-LABEL: @mul_i16(
97; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
98; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
99; VI: %[[R_32:[0-9]+]] = mul i32 %[[A_32]], %[[B_32]]
100; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
101; VI: ret i16 %[[R_16]]
102define i16 @mul_i16(i16 %a, i16 %b) {
103 %r = mul i16 %a, %b
104 ret i16 %r
105}
106
107; VI-LABEL: @mul_nsw_i16(
108; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
109; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
110; VI: %[[R_32:[0-9]+]] = mul nsw i32 %[[A_32]], %[[B_32]]
111; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
112; VI: ret i16 %[[R_16]]
113define i16 @mul_nsw_i16(i16 %a, i16 %b) {
114 %r = mul nsw i16 %a, %b
115 ret i16 %r
116}
117
118; VI-LABEL: @mul_nuw_i16(
119; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
120; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
121; VI: %[[R_32:[0-9]+]] = mul nuw i32 %[[A_32]], %[[B_32]]
122; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
123; VI: ret i16 %[[R_16]]
124define i16 @mul_nuw_i16(i16 %a, i16 %b) {
125 %r = mul nuw i16 %a, %b
126 ret i16 %r
127}
128
129; VI-LABEL: @mul_nuw_nsw_i16(
130; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
131; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
132; VI: %[[R_32:[0-9]+]] = mul nuw nsw i32 %[[A_32]], %[[B_32]]
133; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
134; VI: ret i16 %[[R_16]]
135define i16 @mul_nuw_nsw_i16(i16 %a, i16 %b) {
136 %r = mul nuw nsw i16 %a, %b
137 ret i16 %r
138}
139
140; VI-LABEL: @urem_i16(
141; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
142; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
143; VI: %[[R_32:[0-9]+]] = urem i32 %[[A_32]], %[[B_32]]
144; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
145; VI: ret i16 %[[R_16]]
146define i16 @urem_i16(i16 %a, i16 %b) {
147 %r = urem i16 %a, %b
148 ret i16 %r
149}
150
151; VI-LABEL: @srem_i16(
152; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
153; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32
154; VI: %[[R_32:[0-9]+]] = srem i32 %[[A_32]], %[[B_32]]
155; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
156; VI: ret i16 %[[R_16]]
157define i16 @srem_i16(i16 %a, i16 %b) {
158 %r = srem i16 %a, %b
159 ret i16 %r
160}
161
162; VI-LABEL: @shl_i16(
163; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
164; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
165; VI: %[[R_32:[0-9]+]] = shl i32 %[[A_32]], %[[B_32]]
166; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
167; VI: ret i16 %[[R_16]]
168define i16 @shl_i16(i16 %a, i16 %b) {
169 %r = shl i16 %a, %b
170 ret i16 %r
171}
172
173; VI-LABEL: @shl_nsw_i16(
174; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
175; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
176; VI: %[[R_32:[0-9]+]] = shl nsw i32 %[[A_32]], %[[B_32]]
177; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
178; VI: ret i16 %[[R_16]]
179define i16 @shl_nsw_i16(i16 %a, i16 %b) {
180 %r = shl nsw i16 %a, %b
181 ret i16 %r
182}
183
184; VI-LABEL: @shl_nuw_i16(
185; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
186; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
187; VI: %[[R_32:[0-9]+]] = shl nuw i32 %[[A_32]], %[[B_32]]
188; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
189; VI: ret i16 %[[R_16]]
190define i16 @shl_nuw_i16(i16 %a, i16 %b) {
191 %r = shl nuw i16 %a, %b
192 ret i16 %r
193}
194
195; VI-LABEL: @shl_nuw_nsw_i16(
196; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
197; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
198; VI: %[[R_32:[0-9]+]] = shl nuw nsw i32 %[[A_32]], %[[B_32]]
199; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
200; VI: ret i16 %[[R_16]]
201define i16 @shl_nuw_nsw_i16(i16 %a, i16 %b) {
202 %r = shl nuw nsw i16 %a, %b
203 ret i16 %r
204}
205
206; VI-LABEL: @lshr_i16(
207; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
208; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
209; VI: %[[R_32:[0-9]+]] = lshr i32 %[[A_32]], %[[B_32]]
210; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
211; VI: ret i16 %[[R_16]]
212define i16 @lshr_i16(i16 %a, i16 %b) {
213 %r = lshr i16 %a, %b
214 ret i16 %r
215}
216
217; VI-LABEL: @lshr_exact_i16(
218; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
219; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
220; VI: %[[R_32:[0-9]+]] = lshr exact i32 %[[A_32]], %[[B_32]]
221; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
222; VI: ret i16 %[[R_16]]
223define i16 @lshr_exact_i16(i16 %a, i16 %b) {
224 %r = lshr exact i16 %a, %b
225 ret i16 %r
226}
227
228; VI-LABEL: @ashr_i16(
Konstantin Zhuravlyov691e2e02016-10-03 18:29:01 +0000[diff] [blame]229; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
230; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32
Konstantin Zhuravlyove14df4b2016-09-28 20:05:39 +0000[diff] [blame]231; VI: %[[R_32:[0-9]+]] = ashr i32 %[[A_32]], %[[B_32]]
232; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
233; VI: ret i16 %[[R_16]]
234define i16 @ashr_i16(i16 %a, i16 %b) {
235 %r = ashr i16 %a, %b
236 ret i16 %r
237}
238
239; VI-LABEL: @ashr_exact_i16(
Konstantin Zhuravlyov691e2e02016-10-03 18:29:01 +0000[diff] [blame]240; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
241; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32
Konstantin Zhuravlyove14df4b2016-09-28 20:05:39 +0000[diff] [blame]242; VI: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]]
243; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
244; VI: ret i16 %[[R_16]]
245define i16 @ashr_exact_i16(i16 %a, i16 %b) {
246 %r = ashr exact i16 %a, %b
247 ret i16 %r
248}
249
250; VI-LABEL: @and_i16(
251; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
252; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
253; VI: %[[R_32:[0-9]+]] = and i32 %[[A_32]], %[[B_32]]
254; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
255; VI: ret i16 %[[R_16]]
256define i16 @and_i16(i16 %a, i16 %b) {
257 %r = and i16 %a, %b
258 ret i16 %r
259}
260
261; VI-LABEL: @or_i16(
262; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
263; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
264; VI: %[[R_32:[0-9]+]] = or i32 %[[A_32]], %[[B_32]]
265; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
266; VI: ret i16 %[[R_16]]
267define i16 @or_i16(i16 %a, i16 %b) {
268 %r = or i16 %a, %b
269 ret i16 %r
270}
271
272; VI-LABEL: @xor_i16(
273; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
274; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
275; VI: %[[R_32:[0-9]+]] = xor i32 %[[A_32]], %[[B_32]]
276; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
277; VI: ret i16 %[[R_16]]
278define i16 @xor_i16(i16 %a, i16 %b) {
279 %r = xor i16 %a, %b
280 ret i16 %r
281}
282
283; VI-LABEL: @select_eq_i16(
284; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32
285; VI: %[[B_32_0:[0-9]+]] = zext i16 %b to i32
286; VI: %[[CMP:[0-9]+]] = icmp eq i32 %[[A_32_0]], %[[B_32_0]]
287; VI: %[[A_32_1:[0-9]+]] = zext i16 %a to i32
288; VI: %[[B_32_1:[0-9]+]] = zext i16 %b to i32
289; VI: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]]
290; VI: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16
291; VI: ret i16 %[[SEL_16]]
292define i16 @select_eq_i16(i16 %a, i16 %b) {
293 %cmp = icmp eq i16 %a, %b
294 %sel = select i1 %cmp, i16 %a, i16 %b
295 ret i16 %sel
296}
297
298; VI-LABEL: @select_ne_i16(
299; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32
300; VI: %[[B_32_0:[0-9]+]] = zext i16 %b to i32
301; VI: %[[CMP:[0-9]+]] = icmp ne i32 %[[A_32_0]], %[[B_32_0]]
302; VI: %[[A_32_1:[0-9]+]] = zext i16 %a to i32
303; VI: %[[B_32_1:[0-9]+]] = zext i16 %b to i32
304; VI: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]]
305; VI: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16
306; VI: ret i16 %[[SEL_16]]
307define i16 @select_ne_i16(i16 %a, i16 %b) {
308 %cmp = icmp ne i16 %a, %b
309 %sel = select i1 %cmp, i16 %a, i16 %b
310 ret i16 %sel
311}
312
313; VI-LABEL: @select_ugt_i16(
314; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32
315; VI: %[[B_32_0:[0-9]+]] = zext i16 %b to i32
316; VI: %[[CMP:[0-9]+]] = icmp ugt i32 %[[A_32_0]], %[[B_32_0]]
317; VI: %[[A_32_1:[0-9]+]] = zext i16 %a to i32
318; VI: %[[B_32_1:[0-9]+]] = zext i16 %b to i32
319; VI: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]]
320; VI: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16
321; VI: ret i16 %[[SEL_16]]
322define i16 @select_ugt_i16(i16 %a, i16 %b) {
323 %cmp = icmp ugt i16 %a, %b
324 %sel = select i1 %cmp, i16 %a, i16 %b
325 ret i16 %sel
326}
327
328; VI-LABEL: @select_uge_i16(
329; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32
330; VI: %[[B_32_0:[0-9]+]] = zext i16 %b to i32
331; VI: %[[CMP:[0-9]+]] = icmp uge i32 %[[A_32_0]], %[[B_32_0]]
332; VI: %[[A_32_1:[0-9]+]] = zext i16 %a to i32
333; VI: %[[B_32_1:[0-9]+]] = zext i16 %b to i32
334; VI: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]]
335; VI: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16
336; VI: ret i16 %[[SEL_16]]
337define i16 @select_uge_i16(i16 %a, i16 %b) {
338 %cmp = icmp uge i16 %a, %b
339 %sel = select i1 %cmp, i16 %a, i16 %b
340 ret i16 %sel
341}
342
343; VI-LABEL: @select_ult_i16(
344; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32
345; VI: %[[B_32_0:[0-9]+]] = zext i16 %b to i32
346; VI: %[[CMP:[0-9]+]] = icmp ult i32 %[[A_32_0]], %[[B_32_0]]
347; VI: %[[A_32_1:[0-9]+]] = zext i16 %a to i32
348; VI: %[[B_32_1:[0-9]+]] = zext i16 %b to i32
349; VI: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]]
350; VI: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16
351; VI: ret i16 %[[SEL_16]]
352define i16 @select_ult_i16(i16 %a, i16 %b) {
353 %cmp = icmp ult i16 %a, %b
354 %sel = select i1 %cmp, i16 %a, i16 %b
355 ret i16 %sel
356}
357
358; VI-LABEL: @select_ule_i16(
359; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32
360; VI: %[[B_32_0:[0-9]+]] = zext i16 %b to i32
361; VI: %[[CMP:[0-9]+]] = icmp ule i32 %[[A_32_0]], %[[B_32_0]]
362; VI: %[[A_32_1:[0-9]+]] = zext i16 %a to i32
363; VI: %[[B_32_1:[0-9]+]] = zext i16 %b to i32
364; VI: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]]
365; VI: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16
366; VI: ret i16 %[[SEL_16]]
367define i16 @select_ule_i16(i16 %a, i16 %b) {
368 %cmp = icmp ule i16 %a, %b
369 %sel = select i1 %cmp, i16 %a, i16 %b
370 ret i16 %sel
371}
372
373; VI-LABEL: @select_sgt_i16(
374; VI: %[[A_32_0:[0-9]+]] = sext i16 %a to i32
375; VI: %[[B_32_0:[0-9]+]] = sext i16 %b to i32
376; VI: %[[CMP:[0-9]+]] = icmp sgt i32 %[[A_32_0]], %[[B_32_0]]
377; VI: %[[A_32_1:[0-9]+]] = sext i16 %a to i32
378; VI: %[[B_32_1:[0-9]+]] = sext i16 %b to i32
379; VI: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]]
380; VI: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16
381; VI: ret i16 %[[SEL_16]]
382define i16 @select_sgt_i16(i16 %a, i16 %b) {
383 %cmp = icmp sgt i16 %a, %b
384 %sel = select i1 %cmp, i16 %a, i16 %b
385 ret i16 %sel
386}
387
388; VI-LABEL: @select_sge_i16(
389; VI: %[[A_32_0:[0-9]+]] = sext i16 %a to i32
390; VI: %[[B_32_0:[0-9]+]] = sext i16 %b to i32
391; VI: %[[CMP:[0-9]+]] = icmp sge i32 %[[A_32_0]], %[[B_32_0]]
392; VI: %[[A_32_1:[0-9]+]] = sext i16 %a to i32
393; VI: %[[B_32_1:[0-9]+]] = sext i16 %b to i32
394; VI: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]]
395; VI: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16
396; VI: ret i16 %[[SEL_16]]
397define i16 @select_sge_i16(i16 %a, i16 %b) {
398 %cmp = icmp sge i16 %a, %b
399 %sel = select i1 %cmp, i16 %a, i16 %b
400 ret i16 %sel
401}
402
403; VI-LABEL: @select_slt_i16(
404; VI: %[[A_32_0:[0-9]+]] = sext i16 %a to i32
405; VI: %[[B_32_0:[0-9]+]] = sext i16 %b to i32
406; VI: %[[CMP:[0-9]+]] = icmp slt i32 %[[A_32_0]], %[[B_32_0]]
407; VI: %[[A_32_1:[0-9]+]] = sext i16 %a to i32
408; VI: %[[B_32_1:[0-9]+]] = sext i16 %b to i32
409; VI: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]]
410; VI: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16
411; VI: ret i16 %[[SEL_16]]
412define i16 @select_slt_i16(i16 %a, i16 %b) {
413 %cmp = icmp slt i16 %a, %b
414 %sel = select i1 %cmp, i16 %a, i16 %b
415 ret i16 %sel
416}
417
418; VI-LABEL: @select_sle_i16(
419; VI: %[[A_32_0:[0-9]+]] = sext i16 %a to i32
420; VI: %[[B_32_0:[0-9]+]] = sext i16 %b to i32
421; VI: %[[CMP:[0-9]+]] = icmp sle i32 %[[A_32_0]], %[[B_32_0]]
422; VI: %[[A_32_1:[0-9]+]] = sext i16 %a to i32
423; VI: %[[B_32_1:[0-9]+]] = sext i16 %b to i32
424; VI: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]]
425; VI: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16
426; VI: ret i16 %[[SEL_16]]
427define i16 @select_sle_i16(i16 %a, i16 %b) {
428 %cmp = icmp sle i16 %a, %b
429 %sel = select i1 %cmp, i16 %a, i16 %b
430 ret i16 %sel
431}
432
433; VI-LABEL: @add_3xi16(
434; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
435; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
436; VI: %[[R_32:[0-9]+]] = add <3 x i32> %[[A_32]], %[[B_32]]
437; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
438; VI: ret <3 x i16> %[[R_16]]
439define <3 x i16> @add_3xi16(<3 x i16> %a, <3 x i16> %b) {
440 %r = add <3 x i16> %a, %b
441 ret <3 x i16> %r
442}
443
444; VI-LABEL: @add_nsw_3xi16(
445; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
446; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
447; VI: %[[R_32:[0-9]+]] = add nsw <3 x i32> %[[A_32]], %[[B_32]]
448; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
449; VI: ret <3 x i16> %[[R_16]]
450define <3 x i16> @add_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) {
451 %r = add nsw <3 x i16> %a, %b
452 ret <3 x i16> %r
453}
454
455; VI-LABEL: @add_nuw_3xi16(
456; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
457; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
458; VI: %[[R_32:[0-9]+]] = add nuw <3 x i32> %[[A_32]], %[[B_32]]
459; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
460; VI: ret <3 x i16> %[[R_16]]
461define <3 x i16> @add_nuw_3xi16(<3 x i16> %a, <3 x i16> %b) {
462 %r = add nuw <3 x i16> %a, %b
463 ret <3 x i16> %r
464}
465
466; VI-LABEL: @add_nuw_nsw_3xi16(
467; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
468; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
469; VI: %[[R_32:[0-9]+]] = add nuw nsw <3 x i32> %[[A_32]], %[[B_32]]
470; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
471; VI: ret <3 x i16> %[[R_16]]
472define <3 x i16> @add_nuw_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) {
473 %r = add nuw nsw <3 x i16> %a, %b
474 ret <3 x i16> %r
475}
476
477; VI-LABEL: @sub_3xi16(
478; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
479; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
480; VI: %[[R_32:[0-9]+]] = sub <3 x i32> %[[A_32]], %[[B_32]]
481; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
482; VI: ret <3 x i16> %[[R_16]]
483define <3 x i16> @sub_3xi16(<3 x i16> %a, <3 x i16> %b) {
484 %r = sub <3 x i16> %a, %b
485 ret <3 x i16> %r
486}
487
488; VI-LABEL: @sub_nsw_3xi16(
489; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
490; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
491; VI: %[[R_32:[0-9]+]] = sub nsw <3 x i32> %[[A_32]], %[[B_32]]
492; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
493; VI: ret <3 x i16> %[[R_16]]
494define <3 x i16> @sub_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) {
495 %r = sub nsw <3 x i16> %a, %b
496 ret <3 x i16> %r
497}
498
499; VI-LABEL: @sub_nuw_3xi16(
500; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
501; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
502; VI: %[[R_32:[0-9]+]] = sub nuw <3 x i32> %[[A_32]], %[[B_32]]
503; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
504; VI: ret <3 x i16> %[[R_16]]
505define <3 x i16> @sub_nuw_3xi16(<3 x i16> %a, <3 x i16> %b) {
506 %r = sub nuw <3 x i16> %a, %b
507 ret <3 x i16> %r
508}
509
510; VI-LABEL: @sub_nuw_nsw_3xi16(
511; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
512; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
513; VI: %[[R_32:[0-9]+]] = sub nuw nsw <3 x i32> %[[A_32]], %[[B_32]]
514; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
515; VI: ret <3 x i16> %[[R_16]]
516define <3 x i16> @sub_nuw_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) {
517 %r = sub nuw nsw <3 x i16> %a, %b
518 ret <3 x i16> %r
519}
520
521; VI-LABEL: @mul_3xi16(
522; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
523; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
524; VI: %[[R_32:[0-9]+]] = mul <3 x i32> %[[A_32]], %[[B_32]]
525; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
526; VI: ret <3 x i16> %[[R_16]]
527define <3 x i16> @mul_3xi16(<3 x i16> %a, <3 x i16> %b) {
528 %r = mul <3 x i16> %a, %b
529 ret <3 x i16> %r
530}
531
532; VI-LABEL: @mul_nsw_3xi16(
533; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
534; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
535; VI: %[[R_32:[0-9]+]] = mul nsw <3 x i32> %[[A_32]], %[[B_32]]
536; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
537; VI: ret <3 x i16> %[[R_16]]
538define <3 x i16> @mul_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) {
539 %r = mul nsw <3 x i16> %a, %b
540 ret <3 x i16> %r
541}
542
543; VI-LABEL: @mul_nuw_3xi16(
544; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
545; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
546; VI: %[[R_32:[0-9]+]] = mul nuw <3 x i32> %[[A_32]], %[[B_32]]
547; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
548; VI: ret <3 x i16> %[[R_16]]
549define <3 x i16> @mul_nuw_3xi16(<3 x i16> %a, <3 x i16> %b) {
550 %r = mul nuw <3 x i16> %a, %b
551 ret <3 x i16> %r
552}
553
554; VI-LABEL: @mul_nuw_nsw_3xi16(
555; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
556; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
557; VI: %[[R_32:[0-9]+]] = mul nuw nsw <3 x i32> %[[A_32]], %[[B_32]]
558; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
559; VI: ret <3 x i16> %[[R_16]]
560define <3 x i16> @mul_nuw_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) {
561 %r = mul nuw nsw <3 x i16> %a, %b
562 ret <3 x i16> %r
563}
564
565; VI-LABEL: @urem_3xi16(
566; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
567; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
568; VI: %[[R_32:[0-9]+]] = urem <3 x i32> %[[A_32]], %[[B_32]]
569; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
570; VI: ret <3 x i16> %[[R_16]]
571define <3 x i16> @urem_3xi16(<3 x i16> %a, <3 x i16> %b) {
572 %r = urem <3 x i16> %a, %b
573 ret <3 x i16> %r
574}
575
576; VI-LABEL: @srem_3xi16(
577; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
578; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
579; VI: %[[R_32:[0-9]+]] = srem <3 x i32> %[[A_32]], %[[B_32]]
580; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
581; VI: ret <3 x i16> %[[R_16]]
582define <3 x i16> @srem_3xi16(<3 x i16> %a, <3 x i16> %b) {
583 %r = srem <3 x i16> %a, %b
584 ret <3 x i16> %r
585}
586
587; VI-LABEL: @shl_3xi16(
588; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
589; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
590; VI: %[[R_32:[0-9]+]] = shl <3 x i32> %[[A_32]], %[[B_32]]
591; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
592; VI: ret <3 x i16> %[[R_16]]
593define <3 x i16> @shl_3xi16(<3 x i16> %a, <3 x i16> %b) {
594 %r = shl <3 x i16> %a, %b
595 ret <3 x i16> %r
596}
597
598; VI-LABEL: @shl_nsw_3xi16(
599; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
600; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
601; VI: %[[R_32:[0-9]+]] = shl nsw <3 x i32> %[[A_32]], %[[B_32]]
602; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
603; VI: ret <3 x i16> %[[R_16]]
604define <3 x i16> @shl_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) {
605 %r = shl nsw <3 x i16> %a, %b
606 ret <3 x i16> %r
607}
608
609; VI-LABEL: @shl_nuw_3xi16(
610; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
611; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
612; VI: %[[R_32:[0-9]+]] = shl nuw <3 x i32> %[[A_32]], %[[B_32]]
613; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
614; VI: ret <3 x i16> %[[R_16]]
615define <3 x i16> @shl_nuw_3xi16(<3 x i16> %a, <3 x i16> %b) {
616 %r = shl nuw <3 x i16> %a, %b
617 ret <3 x i16> %r
618}
619
620; VI-LABEL: @shl_nuw_nsw_3xi16(
621; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
622; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
623; VI: %[[R_32:[0-9]+]] = shl nuw nsw <3 x i32> %[[A_32]], %[[B_32]]
624; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
625; VI: ret <3 x i16> %[[R_16]]
626define <3 x i16> @shl_nuw_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) {
627 %r = shl nuw nsw <3 x i16> %a, %b
628 ret <3 x i16> %r
629}
630
631; VI-LABEL: @lshr_3xi16(
632; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
633; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
634; VI: %[[R_32:[0-9]+]] = lshr <3 x i32> %[[A_32]], %[[B_32]]
635; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
636; VI: ret <3 x i16> %[[R_16]]
637define <3 x i16> @lshr_3xi16(<3 x i16> %a, <3 x i16> %b) {
638 %r = lshr <3 x i16> %a, %b
639 ret <3 x i16> %r
640}
641
642; VI-LABEL: @lshr_exact_3xi16(
643; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
644; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
645; VI: %[[R_32:[0-9]+]] = lshr exact <3 x i32> %[[A_32]], %[[B_32]]
646; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
647; VI: ret <3 x i16> %[[R_16]]
648define <3 x i16> @lshr_exact_3xi16(<3 x i16> %a, <3 x i16> %b) {
649 %r = lshr exact <3 x i16> %a, %b
650 ret <3 x i16> %r
651}
652
653; VI-LABEL: @ashr_3xi16(
Konstantin Zhuravlyov691e2e02016-10-03 18:29:01 +0000[diff] [blame]654; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
655; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
Konstantin Zhuravlyove14df4b2016-09-28 20:05:39 +0000[diff] [blame]656; VI: %[[R_32:[0-9]+]] = ashr <3 x i32> %[[A_32]], %[[B_32]]
657; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
658; VI: ret <3 x i16> %[[R_16]]
659define <3 x i16> @ashr_3xi16(<3 x i16> %a, <3 x i16> %b) {
660 %r = ashr <3 x i16> %a, %b
661 ret <3 x i16> %r
662}
663
664; VI-LABEL: @ashr_exact_3xi16(
Konstantin Zhuravlyov691e2e02016-10-03 18:29:01 +0000[diff] [blame]665; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
666; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
Konstantin Zhuravlyove14df4b2016-09-28 20:05:39 +0000[diff] [blame]667; VI: %[[R_32:[0-9]+]] = ashr exact <3 x i32> %[[A_32]], %[[B_32]]
668; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
669; VI: ret <3 x i16> %[[R_16]]
670define <3 x i16> @ashr_exact_3xi16(<3 x i16> %a, <3 x i16> %b) {
671 %r = ashr exact <3 x i16> %a, %b
672 ret <3 x i16> %r
673}
674
675; VI-LABEL: @and_3xi16(
676; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
677; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
678; VI: %[[R_32:[0-9]+]] = and <3 x i32> %[[A_32]], %[[B_32]]
679; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
680; VI: ret <3 x i16> %[[R_16]]
681define <3 x i16> @and_3xi16(<3 x i16> %a, <3 x i16> %b) {
682 %r = and <3 x i16> %a, %b
683 ret <3 x i16> %r
684}
685
686; VI-LABEL: @or_3xi16(
687; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
688; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
689; VI: %[[R_32:[0-9]+]] = or <3 x i32> %[[A_32]], %[[B_32]]
690; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
691; VI: ret <3 x i16> %[[R_16]]
692define <3 x i16> @or_3xi16(<3 x i16> %a, <3 x i16> %b) {
693 %r = or <3 x i16> %a, %b
694 ret <3 x i16> %r
695}
696
697; VI-LABEL: @xor_3xi16(
698; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
699; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
700; VI: %[[R_32:[0-9]+]] = xor <3 x i32> %[[A_32]], %[[B_32]]
701; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
702; VI: ret <3 x i16> %[[R_16]]
703define <3 x i16> @xor_3xi16(<3 x i16> %a, <3 x i16> %b) {
704 %r = xor <3 x i16> %a, %b
705 ret <3 x i16> %r
706}
707
708; VI-LABEL: @select_eq_3xi16(
709; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
710; VI: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
711; VI: %[[CMP:[0-9]+]] = icmp eq <3 x i32> %[[A_32_0]], %[[B_32_0]]
712; VI: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
713; VI: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
714; VI: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]]
715; VI: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16>
716; VI: ret <3 x i16> %[[SEL_16]]
717define <3 x i16> @select_eq_3xi16(<3 x i16> %a, <3 x i16> %b) {
718 %cmp = icmp eq <3 x i16> %a, %b
719 %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
720 ret <3 x i16> %sel
721}
722
723; VI-LABEL: @select_ne_3xi16(
724; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
725; VI: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
726; VI: %[[CMP:[0-9]+]] = icmp ne <3 x i32> %[[A_32_0]], %[[B_32_0]]
727; VI: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
728; VI: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
729; VI: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]]
730; VI: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16>
731; VI: ret <3 x i16> %[[SEL_16]]
732define <3 x i16> @select_ne_3xi16(<3 x i16> %a, <3 x i16> %b) {
733 %cmp = icmp ne <3 x i16> %a, %b
734 %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
735 ret <3 x i16> %sel
736}
737
738; VI-LABEL: @select_ugt_3xi16(
739; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
740; VI: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
741; VI: %[[CMP:[0-9]+]] = icmp ugt <3 x i32> %[[A_32_0]], %[[B_32_0]]
742; VI: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
743; VI: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
744; VI: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]]
745; VI: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16>
746; VI: ret <3 x i16> %[[SEL_16]]
747define <3 x i16> @select_ugt_3xi16(<3 x i16> %a, <3 x i16> %b) {
748 %cmp = icmp ugt <3 x i16> %a, %b
749 %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
750 ret <3 x i16> %sel
751}
752
753; VI-LABEL: @select_uge_3xi16(
754; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
755; VI: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
756; VI: %[[CMP:[0-9]+]] = icmp uge <3 x i32> %[[A_32_0]], %[[B_32_0]]
757; VI: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
758; VI: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
759; VI: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]]
760; VI: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16>
761; VI: ret <3 x i16> %[[SEL_16]]
762define <3 x i16> @select_uge_3xi16(<3 x i16> %a, <3 x i16> %b) {
763 %cmp = icmp uge <3 x i16> %a, %b
764 %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
765 ret <3 x i16> %sel
766}
767
768; VI-LABEL: @select_ult_3xi16(
769; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
770; VI: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
771; VI: %[[CMP:[0-9]+]] = icmp ult <3 x i32> %[[A_32_0]], %[[B_32_0]]
772; VI: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
773; VI: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
774; VI: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]]
775; VI: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16>
776; VI: ret <3 x i16> %[[SEL_16]]
777define <3 x i16> @select_ult_3xi16(<3 x i16> %a, <3 x i16> %b) {
778 %cmp = icmp ult <3 x i16> %a, %b
779 %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
780 ret <3 x i16> %sel
781}
782
783; VI-LABEL: @select_ule_3xi16(
784; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
785; VI: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
786; VI: %[[CMP:[0-9]+]] = icmp ule <3 x i32> %[[A_32_0]], %[[B_32_0]]
787; VI: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
788; VI: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
789; VI: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]]
790; VI: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16>
791; VI: ret <3 x i16> %[[SEL_16]]
792define <3 x i16> @select_ule_3xi16(<3 x i16> %a, <3 x i16> %b) {
793 %cmp = icmp ule <3 x i16> %a, %b
794 %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
795 ret <3 x i16> %sel
796}
797
798; VI-LABEL: @select_sgt_3xi16(
799; VI: %[[A_32_0:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
800; VI: %[[B_32_0:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
801; VI: %[[CMP:[0-9]+]] = icmp sgt <3 x i32> %[[A_32_0]], %[[B_32_0]]
802; VI: %[[A_32_1:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
803; VI: %[[B_32_1:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
804; VI: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]]
805; VI: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16>
806; VI: ret <3 x i16> %[[SEL_16]]
807define <3 x i16> @select_sgt_3xi16(<3 x i16> %a, <3 x i16> %b) {
808 %cmp = icmp sgt <3 x i16> %a, %b
809 %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
810 ret <3 x i16> %sel
811}
812
813; VI-LABEL: @select_sge_3xi16(
814; VI: %[[A_32_0:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
815; VI: %[[B_32_0:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
816; VI: %[[CMP:[0-9]+]] = icmp sge <3 x i32> %[[A_32_0]], %[[B_32_0]]
817; VI: %[[A_32_1:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
818; VI: %[[B_32_1:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
819; VI: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]]
820; VI: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16>
821; VI: ret <3 x i16> %[[SEL_16]]
822define <3 x i16> @select_sge_3xi16(<3 x i16> %a, <3 x i16> %b) {
823 %cmp = icmp sge <3 x i16> %a, %b
824 %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
825 ret <3 x i16> %sel
826}
827
828; VI-LABEL: @select_slt_3xi16(
829; VI: %[[A_32_0:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
830; VI: %[[B_32_0:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
831; VI: %[[CMP:[0-9]+]] = icmp slt <3 x i32> %[[A_32_0]], %[[B_32_0]]
832; VI: %[[A_32_1:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
833; VI: %[[B_32_1:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
834; VI: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]]
835; VI: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16>
836; VI: ret <3 x i16> %[[SEL_16]]
837define <3 x i16> @select_slt_3xi16(<3 x i16> %a, <3 x i16> %b) {
838 %cmp = icmp slt <3 x i16> %a, %b
839 %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
840 ret <3 x i16> %sel
841}
842
843; VI-LABEL: @select_sle_3xi16(
844; VI: %[[A_32_0:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
845; VI: %[[B_32_0:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
846; VI: %[[CMP:[0-9]+]] = icmp sle <3 x i32> %[[A_32_0]], %[[B_32_0]]
847; VI: %[[A_32_1:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
848; VI: %[[B_32_1:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
849; VI: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]]
850; VI: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16>
851; VI: ret <3 x i16> %[[SEL_16]]
852define <3 x i16> @select_sle_3xi16(<3 x i16> %a, <3 x i16> %b) {
853 %cmp = icmp sle <3 x i16> %a, %b
854 %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
855 ret <3 x i16> %sel
856}