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gerrit-public.fairphone.software / toolchain / llvm-project / b51a9bc35854509b9d4b125d232c4ff07ab765f5 / . / llvm / test / CodeGen / AMDGPU / predicates.ll
blob: 566b48eb88642d911343a01ba26433a0007fce09 [file] [log] [blame]
Matt Arsenaultc5816112016-06-24 06:30:22 +0000[diff] [blame]1; RUN: llc -spec-exec-max-speculation-cost=0 -march=r600 -r600-ir-structurize=0 -mcpu=redwood < %s | FileCheck %s
Tom Stellard7d411612013-02-05 17:09:13 +0000[diff] [blame]2
3; These tests make sure the compiler is optimizing branches using predicates
4; when it is legal to do so.
5
Matt Arsenaultf42c6922016-06-15 00:11:01 +0000[diff] [blame]6; CHECK-LABEL: {{^}}simple_if:
Vincent Lejeunef97af792013-05-02 21:52:30 +0000[diff] [blame]7; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
8; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]9define amdgpu_kernel void @simple_if(i32 addrspace(1)* %out, i32 %in) {
Tom Stellard7d411612013-02-05 17:09:13 +0000[diff] [blame]10entry:
Matt Arsenaultf42c6922016-06-15 00:11:01 +0000[diff] [blame]11 %cmp0 = icmp sgt i32 %in, 0
12 br i1 %cmp0, label %IF, label %ENDIF
Tom Stellard7d411612013-02-05 17:09:13 +0000[diff] [blame]13
14IF:
Matt Arsenaultf42c6922016-06-15 00:11:01 +0000[diff] [blame]15 %tmp1 = shl i32 %in, 1
Tom Stellard7d411612013-02-05 17:09:13 +0000[diff] [blame]16 br label %ENDIF
17
18ENDIF:
Matt Arsenaultf42c6922016-06-15 00:11:01 +0000[diff] [blame]19 %tmp2 = phi i32 [ %in, %entry ], [ %tmp1, %IF ]
20 store i32 %tmp2, i32 addrspace(1)* %out
Tom Stellard7d411612013-02-05 17:09:13 +0000[diff] [blame]21 ret void
22}
23
Matt Arsenaultf42c6922016-06-15 00:11:01 +0000[diff] [blame]24; CHECK-LABEL: {{^}}simple_if_else:
Vincent Lejeunef97af792013-05-02 21:52:30 +0000[diff] [blame]25; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
26; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
27; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]28define amdgpu_kernel void @simple_if_else(i32 addrspace(1)* %out, i32 %in) {
Tom Stellard7d411612013-02-05 17:09:13 +0000[diff] [blame]29entry:
30 %0 = icmp sgt i32 %in, 0
31 br i1 %0, label %IF, label %ELSE
32
33IF:
34 %1 = shl i32 %in, 1
35 br label %ENDIF
36
37ELSE:
38 %2 = lshr i32 %in, 1
39 br label %ENDIF
40
41ENDIF:
42 %3 = phi i32 [ %1, %IF ], [ %2, %ELSE ]
43 store i32 %3, i32 addrspace(1)* %out
44 ret void
45}
46
Matt Arsenaultf42c6922016-06-15 00:11:01 +0000[diff] [blame]47; CHECK-LABEL: {{^}}nested_if:
Vincent Lejeunebfaa63a62013-04-01 21:48:05 +0000[diff] [blame]48; CHECK: ALU_PUSH_BEFORE
Vincent Lejeunebfaa63a62013-04-01 21:48:05 +0000[diff] [blame]49; CHECK: JUMP
Vincent Lejeune3abdbf12013-04-30 00:14:38 +0000[diff] [blame]50; CHECK: POP
Vincent Lejeunef97af792013-05-02 21:52:30 +0000[diff] [blame]51; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec
52; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
53; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]54define amdgpu_kernel void @nested_if(i32 addrspace(1)* %out, i32 %in) {
Tom Stellard7d411612013-02-05 17:09:13 +0000[diff] [blame]55entry:
56 %0 = icmp sgt i32 %in, 0
57 br i1 %0, label %IF0, label %ENDIF
58
59IF0:
60 %1 = add i32 %in, 10
61 %2 = icmp sgt i32 %1, 0
62 br i1 %2, label %IF1, label %ENDIF
63
64IF1:
65 %3 = shl i32 %1, 1
66 br label %ENDIF
67
68ENDIF:
69 %4 = phi i32 [%in, %entry], [%1, %IF0], [%3, %IF1]
70 store i32 %4, i32 addrspace(1)* %out
71 ret void
72}
73
Matt Arsenaultf42c6922016-06-15 00:11:01 +0000[diff] [blame]74; CHECK-LABEL: {{^}}nested_if_else:
Vincent Lejeunebfaa63a62013-04-01 21:48:05 +0000[diff] [blame]75; CHECK: ALU_PUSH_BEFORE
Vincent Lejeunebfaa63a62013-04-01 21:48:05 +0000[diff] [blame]76; CHECK: JUMP
Vincent Lejeune3abdbf12013-04-30 00:14:38 +0000[diff] [blame]77; CHECK: POP
Vincent Lejeunef97af792013-05-02 21:52:30 +0000[diff] [blame]78; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec
79; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
80; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
81; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]82define amdgpu_kernel void @nested_if_else(i32 addrspace(1)* %out, i32 %in) {
Tom Stellard7d411612013-02-05 17:09:13 +0000[diff] [blame]83entry:
84 %0 = icmp sgt i32 %in, 0
85 br i1 %0, label %IF0, label %ENDIF
86
87IF0:
88 %1 = add i32 %in, 10
89 %2 = icmp sgt i32 %1, 0
90 br i1 %2, label %IF1, label %ELSE1
91
92IF1:
93 %3 = shl i32 %1, 1
94 br label %ENDIF
95
96ELSE1:
97 %4 = lshr i32 %in, 1
98 br label %ENDIF
99
100ENDIF:
101 %5 = phi i32 [%in, %entry], [%3, %IF1], [%4, %ELSE1]
102 store i32 %5, i32 addrspace(1)* %out
103 ret void
104}