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gerrit-public.fairphone.software / toolchain / llvm-project / b51a9bc35854509b9d4b125d232c4ff07ab765f5 / . / llvm / test / CodeGen / PowerPC / crsave.ll
blob: d7be2fd18c9c3818a43cd1b3a8bf5abf56ff9c03 [file] [log] [blame]
Ulrich Weigand49f487e2013-07-03 17:59:07 +0000[diff] [blame]1; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32
2; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64
Chuang-Yu Cheng8676c3d2016-04-27 02:59:28 +0000[diff] [blame]3; RUN: llc -O0 -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s -check-prefix=PPC64-ELFv2
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]4
5declare void @foo()
6
Rafael Espindolaa5c7cee2013-05-16 03:48:50 +0000[diff] [blame]7define i32 @test_cr2() nounwind uwtable {
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]8entry:
9 %ret = alloca i32, align 4
Ulrich Weigand6b577e22015-01-13 19:43:45 +0000[diff] [blame]10 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]11 store i32 %0, i32* %ret, align 4
12 call void @foo()
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]13 %1 = load i32, i32* %ret, align 4
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]14 ret i32 %1
15}
16
Krzysztof Parzyszek020ec292016-09-06 12:30:00 +0000[diff] [blame]17; PPC32-LABEL: test_cr2:
Bill Schmidtef3d1a22013-05-14 16:08:32 +0000[diff] [blame]18; PPC32: stwu 1, -32(1)
Krzysztof Parzyszek020ec292016-09-06 12:30:00 +0000[diff] [blame]19; PPC32: stw 31, 28(1)
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]20; PPC32: mfcr 12
Bill Schmidtef3d1a22013-05-14 16:08:32 +0000[diff] [blame]21; PPC32-NEXT: stw 12, 24(31)
22; PPC32: lwz 12, 24(31)
Ulrich Weigand49f487e2013-07-03 17:59:07 +0000[diff] [blame]23; PPC32-NEXT: mtocrf 32, 12
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]24
Rafael Espindolaa5c7cee2013-05-16 03:48:50 +0000[diff] [blame]25; PPC64: .cfi_startproc
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]26; PPC64: mfcr 12
Hal Finkel67369882013-04-15 02:07:05 +0000[diff] [blame]27; PPC64: stw 12, 8(1)
28; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
Rafael Espindolaa5c7cee2013-05-16 03:48:50 +0000[diff] [blame]29; PPC64: .cfi_def_cfa_offset 128
30; PPC64: .cfi_offset lr, 16
31; PPC64: .cfi_offset cr2, 8
Hal Finkel67369882013-04-15 02:07:05 +0000[diff] [blame]32; PPC64: addi 1, 1, [[AMT]]
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]33; PPC64: lwz 12, 8(1)
Ulrich Weigand49f487e2013-07-03 17:59:07 +0000[diff] [blame]34; PPC64: mtocrf 32, 12
Rafael Espindolaa5c7cee2013-05-16 03:48:50 +0000[diff] [blame]35; PPC64: .cfi_endproc
Hal Finkeld85a04b2013-04-13 08:09:20 +0000[diff] [blame]36
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]37define i32 @test_cr234() nounwind {
38entry:
39 %ret = alloca i32, align 4
Ulrich Weigand6b577e22015-01-13 19:43:45 +0000[diff] [blame]40 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09cmpw 3,$2,$2\0A\09cmpw 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]41 store i32 %0, i32* %ret, align 4
42 call void @foo()
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]43 %1 = load i32, i32* %ret, align 4
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]44 ret i32 %1
45}
46
Krzysztof Parzyszek020ec292016-09-06 12:30:00 +0000[diff] [blame]47; PPC32-LABEL: test_cr234:
Bill Schmidtef3d1a22013-05-14 16:08:32 +0000[diff] [blame]48; PPC32: stwu 1, -32(1)
Krzysztof Parzyszek020ec292016-09-06 12:30:00 +0000[diff] [blame]49; PPC32: stw 31, 28(1)
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]50; PPC32: mfcr 12
Bill Schmidtef3d1a22013-05-14 16:08:32 +0000[diff] [blame]51; PPC32-NEXT: stw 12, 24(31)
52; PPC32: lwz 12, 24(31)
Ulrich Weigand49f487e2013-07-03 17:59:07 +0000[diff] [blame]53; PPC32-NEXT: mtocrf 32, 12
54; PPC32-NEXT: mtocrf 16, 12
55; PPC32-NEXT: mtocrf 8, 12
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]56
57; PPC64: mfcr 12
Hal Finkel67369882013-04-15 02:07:05 +0000[diff] [blame]58; PPC64: stw 12, 8(1)
59; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
60; PPC64: addi 1, 1, [[AMT]]
Roman Divackyc9e23d92012-09-12 14:47:47 +0000[diff] [blame]61; PPC64: lwz 12, 8(1)
Ulrich Weigand49f487e2013-07-03 17:59:07 +0000[diff] [blame]62; PPC64: mtocrf 32, 12
63; PPC64: mtocrf 16, 12
64; PPC64: mtocrf 8, 12
Hal Finkeld85a04b2013-04-13 08:09:20 +0000[diff] [blame]65
Chuang-Yu Cheng6efde2f2016-04-12 03:04:44 +0000[diff] [blame]66; Generate mfocrf in prologue when we need to save 1 nonvolatile CR field
67define void @cloberOneNvCrField() {
68entry:
69 tail call void asm sideeffect "# clobbers", "~{cr2}"()
70 ret void
71
72; PPC64-ELFv2-LABEL: @cloberOneNvCrField
73; PPC64-ELFv2: mfocrf [[REG1:[0-9]+]], 32
74}
75
76; Generate mfcr in prologue when we need to save all nonvolatile CR field
77define void @cloberAllNvCrField() {
78entry:
79 tail call void asm sideeffect "# clobbers", "~{cr2},~{cr3},~{cr4}"()
80 ret void
81
82; PPC64-ELFv2-LABEL: @cloberAllNvCrField
83; PPC64-ELFv2: mfcr [[REG1:[0-9]+]]
84}