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gerrit-public.fairphone.software / toolchain / llvm-project / b5798b09d302a5f49a05ad9a2df2ae8c646b3802 / . / llvm / lib / Target / AMDGPU / AMDGPU.td
blob: 2e7e39a54d3385f9ca9430345e0221037d8169dd [file] [log] [blame]
Matt Arsenault585b5662015-05-07 17:02:32 +0000[diff] [blame]1//===-- AMDGPU.td - AMDGPU Tablegen files ------------------*- tablegen -*-===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
Matt Arsenault585b5662015-05-07 17:02:32 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]9
Tom Stellardbc5b5372014-06-13 16:38:59 +0000[diff] [blame]10include "llvm/Target/Target.td"
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]11
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]12//===----------------------------------------------------------------------===//
13// Subtarget Features
14//===----------------------------------------------------------------------===//
15
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]16// Debugging Features
17
18def FeatureDumpCode : SubtargetFeature <"DumpCode",
19 "DumpCode",
20 "true",
21 "Dump MachineInstrs in the CodeEmitter">;
22
Tom Stellard0a0fa032015-04-28 17:37:00 +0000[diff] [blame]23def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
24 "DumpCode",
25 "true",
26 "Dump MachineInstrs in the CodeEmitter">;
27
Tom Stellard66df8a22013-11-18 19:43:44 +0000[diff] [blame]28def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
Tom Stellarded0ceec2013-10-10 17:11:12 +0000[diff] [blame]29 "EnableIRStructurizer",
Tom Stellard66df8a22013-11-18 19:43:44 +0000[diff] [blame]30 "false",
31 "Disable IR Structurizer">;
Tom Stellarded0ceec2013-10-10 17:11:12 +0000[diff] [blame]32
Matt Arsenaultd9a23ab2014-07-13 02:08:26 +0000[diff] [blame]33def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
34 "EnablePromoteAlloca",
35 "true",
36 "Enable promote alloca pass">;
37
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]38// Target features
39
Tom Stellard783893a2013-11-18 19:43:33 +0000[diff] [blame]40def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
41 "EnableIfCvt",
42 "false",
43 "Disable the if conversion pass">;
44
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]45def FeatureFP64 : SubtargetFeature<"fp64",
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]46 "FP64",
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]47 "true",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]48 "Enable double precision operations">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]49
Matt Arsenaultf171cf22014-07-14 23:40:49 +0000[diff] [blame]50def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
51 "FP64Denormals",
52 "true",
53 "Enable double precision denormal handling",
54 [FeatureFP64]>;
55
Matt Arsenaultb035a572015-01-29 19:34:25 +0000[diff] [blame]56def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
57 "FastFMAF32",
58 "true",
59 "Assuming f32 fma is at least as fast as mul + add",
60 []>;
61
Matt Arsenaultf171cf22014-07-14 23:40:49 +0000[diff] [blame]62// Some instructions do not support denormals despite this flag. Using
63// fp32 denormals also causes instructions to run at the double
64// precision rate for the device.
65def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
66 "FP32Denormals",
67 "true",
68 "Enable single precision denormal handling">;
69
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]70def Feature64BitPtr : SubtargetFeature<"64BitPtr",
71 "Is64bit",
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]72 "true",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]73 "Specify if 64-bit addressing should be used">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]74
75def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
76 "R600ALUInst",
77 "false",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]78 "Older version of ALU instructions encoding">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]79
80def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
81 "HasVertexCache",
82 "true",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]83 "Specify use of dedicated vertex cache">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]84
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]85def FeatureCaymanISA : SubtargetFeature<"caymanISA",
86 "CaymanISA",
87 "true",
88 "Use Cayman ISA">;
89
Tom Stellard348273d2014-01-23 16:18:02 +0000[diff] [blame]90def FeatureCFALUBug : SubtargetFeature<"cfalubug",
91 "CFALUBug",
92 "true",
93 "GPU has CF_ALU bug">;
94
Matt Arsenault41033282014-10-10 22:01:59 +0000[diff] [blame]95// XXX - This should probably be removed once enabled by default
96def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
97 "EnableLoadStoreOpt",
98 "true",
99 "Enable SI load/store optimizer pass">;
100
Matt Arsenault3f981402014-09-15 15:41:53 +0000[diff] [blame]101def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
102 "FlatAddressSpace",
103 "true",
104 "Support flat address space">;
105
Tom Stellarde99fb652015-01-20 19:33:04 +0000[diff] [blame]106def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
107 "EnableVGPRSpilling",
108 "true",
109 "Enable spilling of VGPRs to scratch memory">;
110
Marek Olsak4d00dd22015-03-09 15:48:09 +0000[diff] [blame]111def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
112 "SGPRInitBug",
113 "true",
114 "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
115
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]116class SubtargetFeatureFetchLimit <string Value> :
117 SubtargetFeature <"fetch"#Value,
118 "TexVTXClauseSize",
119 Value,
120 "Limit the maximum number of fetches in a clause to "#Value>;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]121
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]122def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
123def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
124
Tom Stellard8c347b02014-01-22 21:55:40 +0000[diff] [blame]125class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
126 "wavefrontsize"#Value,
127 "WavefrontSize",
128 !cast<string>(Value),
129 "The number of threads per wavefront">;
130
131def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
132def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
133def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
134
Tom Stellardec87f842015-05-25 16:15:54 +0000[diff] [blame]135class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
136 "ldsbankcount"#Value,
137 "LDSBankCount",
138 !cast<string>(Value),
139 "The number of LDS banks per compute unit.">;
140
141def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
142def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
143
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]144class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
145 "localmemorysize"#Value,
146 "LocalMemorySize",
147 !cast<string>(Value),
148 "The size of local memory in bytes">;
149
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]150def FeatureGCN : SubtargetFeature<"gcn",
151 "IsGCN",
152 "true",
153 "GCN or newer GPU">;
154
155def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
156 "GCN1Encoding",
157 "true",
158 "Encoding format for SI and CI">;
159
160def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
161 "GCN3Encoding",
162 "true",
163 "Encoding format for VI">;
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame]164
165def FeatureCIInsts : SubtargetFeature<"ci-insts",
166 "CIInsts",
167 "true",
168 "Additional intstructions for CI+">;
169
170// Dummy feature used to disable assembler instructions.
171def FeatureDisable : SubtargetFeature<"",
172 "FeatureDisable","true",
173 "Dummy feature to disable assembler"
174 " instructions">;
175
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]176class SubtargetFeatureGeneration <string Value,
177 list<SubtargetFeature> Implies> :
178 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
179 Value#" GPU generation", Implies>;
180
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]181def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
182def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
183def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
184
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]185def FeatureR600 : SubtargetFeatureGeneration<"R600",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]186 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]187
188def FeatureR700 : SubtargetFeatureGeneration<"R700",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]189 [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]190
191def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]192 [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]193
194def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]195 [FeatureFetchLimit16, FeatureWavefrontSize64,
196 FeatureLocalMemorySize32768]
197>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]198
199def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
Tom Stellard42639a52014-07-21 15:44:58 +0000[diff] [blame]200 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
Tom Stellardec87f842015-05-25 16:15:54 +0000[diff] [blame]201 FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
202 FeatureLDSBankCount32]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]203
Tom Stellard6e1ee472013-10-29 16:37:28 +0000[diff] [blame]204def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
Tom Stellard42639a52014-07-21 15:44:58 +0000[diff] [blame]205 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]206 FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame]207 FeatureGCN1Encoding, FeatureCIInsts]>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]208
209def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
210 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]211 FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
Tom Stellardec87f842015-05-25 16:15:54 +0000[diff] [blame]212 FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]213
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]214//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]215
216def AMDGPUInstrInfo : InstrInfo {
217 let guessInstructionProperties = 1;
Matt Arsenault1ecac062015-02-18 02:15:32 +0000[diff] [blame]218 let noNamedPositionallyEncodedOperands = 1;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]219}
220
Tom Stellard9d7ddd52014-11-14 14:08:00 +0000[diff] [blame]221def AMDGPUAsmParser : AsmParser {
222 // Some of the R600 registers have the same name, so this crashes.
223 // For example T0_XYZW and T0_XY both have the asm name T0.
224 let ShouldEmitMatchRegisterName = 0;
225}
226
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]227def AMDGPU : Target {
228 // Pull in Instruction Info:
229 let InstructionSet = AMDGPUInstrInfo;
Tom Stellard9d7ddd52014-11-14 14:08:00 +0000[diff] [blame]230 let AssemblyParsers = [AMDGPUAsmParser];
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]231}
232
Tom Stellardbc5b5372014-06-13 16:38:59 +0000[diff] [blame]233// Dummy Instruction itineraries for pseudo instructions
234def ALU_NULL : FuncUnit;
235def NullALU : InstrItinClass;
236
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]237//===----------------------------------------------------------------------===//
238// Predicate helper class
239//===----------------------------------------------------------------------===//
240
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame]241def TruePredicate : Predicate<"true">;
242def isSICI : Predicate<
243 "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
244 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
245>, AssemblerPredicate<"FeatureGCN1Encoding">;
246
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]247class PredicateControl {
248 Predicate SubtargetPredicate;
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame]249 Predicate SIAssemblerPredicate = isSICI;
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]250 list<Predicate> AssemblerPredicates = [];
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame]251 Predicate AssemblerPredicate = TruePredicate;
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]252 list<Predicate> OtherPredicates = [];
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame]253 list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]254 AssemblerPredicates,
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]255 OtherPredicates);
256}
257
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]258// Include AMDGPU TD files
259include "R600Schedule.td"
260include "SISchedule.td"
261include "Processors.td"
262include "AMDGPUInstrInfo.td"
263include "AMDGPUIntrinsics.td"
264include "AMDGPURegisterInfo.td"
265include "AMDGPUInstructions.td"
Christian Konig2c8f6d52013-03-07 09:03:52 +0000[diff] [blame]266include "AMDGPUCallingConv.td"