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gerrit-public.fairphone.software / toolchain / llvm-project / b811c1d6a57beae697be440144b9f8b8b33e0605 / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: f2f11c0004e8b427cd188ae30ce67e57feee5932 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]21#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]22#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]23#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]25#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]26#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]27#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]28#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]29#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]31#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]32#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]33#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]34#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]35#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]38#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]39#include <limits>
40
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]41using namespace llvm;
42
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]43#define DEBUG_TYPE "x86-instr-info"
44
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]45#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]46#include "X86GenInstrInfo.inc"
47
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]48static cl::opt<bool>
49NoFusing("disable-spill-fusing",
50 cl::desc("Disable fusing of spill code into instructions"));
51static cl::opt<bool>
52PrintFailedFusing("print-failed-fuse-candidates",
53 cl::desc("Print instructions that the allocator wants to"
54 " fuse, but the X86 backend currently can't"),
55 cl::Hidden);
56static cl::opt<bool>
57ReMatPICStubLoad("remat-pic-stub-load",
58 cl::desc("Re-materialize load from stub in PIC mode"),
59 cl::init(false), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]60
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]61enum {
62 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]63 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]64 TB_INDEX_0 = 0,
65 TB_INDEX_1 = 1,
66 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]67 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]68 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]69 TB_INDEX_MASK = 0xf,
70
71 // Do not insert the reverse map (MemOp -> RegOp) into the table.
72 // This may be needed because there is a many -> one mapping.
73 TB_NO_REVERSE = 1 << 4,
74
75 // Do not insert the forward map (RegOp -> MemOp) into the table.
76 // This is needed for Native Client, which prohibits branch
77 // instructions from using a memory operand.
78 TB_NO_FORWARD = 1 << 5,
79
80 TB_FOLDED_LOAD = 1 << 6,
81 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]82
83 // Minimum alignment required for load/store.
84 // Used for RegOp->MemOp conversion.
85 // (stored in bits 8 - 15)
86 TB_ALIGN_SHIFT = 8,
87 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
88 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
89 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]90 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]91 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]92};
93
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]94struct X86OpTblEntry {
95 uint16_t RegOp;
96 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]97 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]98};
99
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]100// Pin the vtable to this file.
101void X86InstrInfo::anchor() {}
102
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]103X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104 : X86GenInstrInfo(
Pavel Chupinbe9f1212014-09-22 13:11:35 +0000[diff] [blame]105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]107 Subtarget(STI), RI(STI) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]108
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]109 static const X86OpTblEntry OpTbl2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]110 { X86::ADC32ri, X86::ADC32mi, 0 },
111 { X86::ADC32ri8, X86::ADC32mi8, 0 },
112 { X86::ADC32rr, X86::ADC32mr, 0 },
113 { X86::ADC64ri32, X86::ADC64mi32, 0 },
114 { X86::ADC64ri8, X86::ADC64mi8, 0 },
115 { X86::ADC64rr, X86::ADC64mr, 0 },
116 { X86::ADD16ri, X86::ADD16mi, 0 },
117 { X86::ADD16ri8, X86::ADD16mi8, 0 },
118 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
119 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
120 { X86::ADD16rr, X86::ADD16mr, 0 },
121 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
122 { X86::ADD32ri, X86::ADD32mi, 0 },
123 { X86::ADD32ri8, X86::ADD32mi8, 0 },
124 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
125 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
126 { X86::ADD32rr, X86::ADD32mr, 0 },
127 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
128 { X86::ADD64ri32, X86::ADD64mi32, 0 },
129 { X86::ADD64ri8, X86::ADD64mi8, 0 },
130 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
131 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
132 { X86::ADD64rr, X86::ADD64mr, 0 },
133 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
134 { X86::ADD8ri, X86::ADD8mi, 0 },
135 { X86::ADD8rr, X86::ADD8mr, 0 },
136 { X86::AND16ri, X86::AND16mi, 0 },
137 { X86::AND16ri8, X86::AND16mi8, 0 },
138 { X86::AND16rr, X86::AND16mr, 0 },
139 { X86::AND32ri, X86::AND32mi, 0 },
140 { X86::AND32ri8, X86::AND32mi8, 0 },
141 { X86::AND32rr, X86::AND32mr, 0 },
142 { X86::AND64ri32, X86::AND64mi32, 0 },
143 { X86::AND64ri8, X86::AND64mi8, 0 },
144 { X86::AND64rr, X86::AND64mr, 0 },
145 { X86::AND8ri, X86::AND8mi, 0 },
146 { X86::AND8rr, X86::AND8mr, 0 },
147 { X86::DEC16r, X86::DEC16m, 0 },
148 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]149 { X86::DEC64r, X86::DEC64m, 0 },
150 { X86::DEC8r, X86::DEC8m, 0 },
151 { X86::INC16r, X86::INC16m, 0 },
152 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]153 { X86::INC64r, X86::INC64m, 0 },
154 { X86::INC8r, X86::INC8m, 0 },
155 { X86::NEG16r, X86::NEG16m, 0 },
156 { X86::NEG32r, X86::NEG32m, 0 },
157 { X86::NEG64r, X86::NEG64m, 0 },
158 { X86::NEG8r, X86::NEG8m, 0 },
159 { X86::NOT16r, X86::NOT16m, 0 },
160 { X86::NOT32r, X86::NOT32m, 0 },
161 { X86::NOT64r, X86::NOT64m, 0 },
162 { X86::NOT8r, X86::NOT8m, 0 },
163 { X86::OR16ri, X86::OR16mi, 0 },
164 { X86::OR16ri8, X86::OR16mi8, 0 },
165 { X86::OR16rr, X86::OR16mr, 0 },
166 { X86::OR32ri, X86::OR32mi, 0 },
167 { X86::OR32ri8, X86::OR32mi8, 0 },
168 { X86::OR32rr, X86::OR32mr, 0 },
169 { X86::OR64ri32, X86::OR64mi32, 0 },
170 { X86::OR64ri8, X86::OR64mi8, 0 },
171 { X86::OR64rr, X86::OR64mr, 0 },
172 { X86::OR8ri, X86::OR8mi, 0 },
173 { X86::OR8rr, X86::OR8mr, 0 },
174 { X86::ROL16r1, X86::ROL16m1, 0 },
175 { X86::ROL16rCL, X86::ROL16mCL, 0 },
176 { X86::ROL16ri, X86::ROL16mi, 0 },
177 { X86::ROL32r1, X86::ROL32m1, 0 },
178 { X86::ROL32rCL, X86::ROL32mCL, 0 },
179 { X86::ROL32ri, X86::ROL32mi, 0 },
180 { X86::ROL64r1, X86::ROL64m1, 0 },
181 { X86::ROL64rCL, X86::ROL64mCL, 0 },
182 { X86::ROL64ri, X86::ROL64mi, 0 },
183 { X86::ROL8r1, X86::ROL8m1, 0 },
184 { X86::ROL8rCL, X86::ROL8mCL, 0 },
185 { X86::ROL8ri, X86::ROL8mi, 0 },
186 { X86::ROR16r1, X86::ROR16m1, 0 },
187 { X86::ROR16rCL, X86::ROR16mCL, 0 },
188 { X86::ROR16ri, X86::ROR16mi, 0 },
189 { X86::ROR32r1, X86::ROR32m1, 0 },
190 { X86::ROR32rCL, X86::ROR32mCL, 0 },
191 { X86::ROR32ri, X86::ROR32mi, 0 },
192 { X86::ROR64r1, X86::ROR64m1, 0 },
193 { X86::ROR64rCL, X86::ROR64mCL, 0 },
194 { X86::ROR64ri, X86::ROR64mi, 0 },
195 { X86::ROR8r1, X86::ROR8m1, 0 },
196 { X86::ROR8rCL, X86::ROR8mCL, 0 },
197 { X86::ROR8ri, X86::ROR8mi, 0 },
198 { X86::SAR16r1, X86::SAR16m1, 0 },
199 { X86::SAR16rCL, X86::SAR16mCL, 0 },
200 { X86::SAR16ri, X86::SAR16mi, 0 },
201 { X86::SAR32r1, X86::SAR32m1, 0 },
202 { X86::SAR32rCL, X86::SAR32mCL, 0 },
203 { X86::SAR32ri, X86::SAR32mi, 0 },
204 { X86::SAR64r1, X86::SAR64m1, 0 },
205 { X86::SAR64rCL, X86::SAR64mCL, 0 },
206 { X86::SAR64ri, X86::SAR64mi, 0 },
207 { X86::SAR8r1, X86::SAR8m1, 0 },
208 { X86::SAR8rCL, X86::SAR8mCL, 0 },
209 { X86::SAR8ri, X86::SAR8mi, 0 },
210 { X86::SBB32ri, X86::SBB32mi, 0 },
211 { X86::SBB32ri8, X86::SBB32mi8, 0 },
212 { X86::SBB32rr, X86::SBB32mr, 0 },
213 { X86::SBB64ri32, X86::SBB64mi32, 0 },
214 { X86::SBB64ri8, X86::SBB64mi8, 0 },
215 { X86::SBB64rr, X86::SBB64mr, 0 },
216 { X86::SHL16rCL, X86::SHL16mCL, 0 },
217 { X86::SHL16ri, X86::SHL16mi, 0 },
218 { X86::SHL32rCL, X86::SHL32mCL, 0 },
219 { X86::SHL32ri, X86::SHL32mi, 0 },
220 { X86::SHL64rCL, X86::SHL64mCL, 0 },
221 { X86::SHL64ri, X86::SHL64mi, 0 },
222 { X86::SHL8rCL, X86::SHL8mCL, 0 },
223 { X86::SHL8ri, X86::SHL8mi, 0 },
224 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
225 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
226 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
227 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
228 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
229 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
230 { X86::SHR16r1, X86::SHR16m1, 0 },
231 { X86::SHR16rCL, X86::SHR16mCL, 0 },
232 { X86::SHR16ri, X86::SHR16mi, 0 },
233 { X86::SHR32r1, X86::SHR32m1, 0 },
234 { X86::SHR32rCL, X86::SHR32mCL, 0 },
235 { X86::SHR32ri, X86::SHR32mi, 0 },
236 { X86::SHR64r1, X86::SHR64m1, 0 },
237 { X86::SHR64rCL, X86::SHR64mCL, 0 },
238 { X86::SHR64ri, X86::SHR64mi, 0 },
239 { X86::SHR8r1, X86::SHR8m1, 0 },
240 { X86::SHR8rCL, X86::SHR8mCL, 0 },
241 { X86::SHR8ri, X86::SHR8mi, 0 },
242 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
243 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
244 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
245 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
246 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
247 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
248 { X86::SUB16ri, X86::SUB16mi, 0 },
249 { X86::SUB16ri8, X86::SUB16mi8, 0 },
250 { X86::SUB16rr, X86::SUB16mr, 0 },
251 { X86::SUB32ri, X86::SUB32mi, 0 },
252 { X86::SUB32ri8, X86::SUB32mi8, 0 },
253 { X86::SUB32rr, X86::SUB32mr, 0 },
254 { X86::SUB64ri32, X86::SUB64mi32, 0 },
255 { X86::SUB64ri8, X86::SUB64mi8, 0 },
256 { X86::SUB64rr, X86::SUB64mr, 0 },
257 { X86::SUB8ri, X86::SUB8mi, 0 },
258 { X86::SUB8rr, X86::SUB8mr, 0 },
259 { X86::XOR16ri, X86::XOR16mi, 0 },
260 { X86::XOR16ri8, X86::XOR16mi8, 0 },
261 { X86::XOR16rr, X86::XOR16mr, 0 },
262 { X86::XOR32ri, X86::XOR32mi, 0 },
263 { X86::XOR32ri8, X86::XOR32mi8, 0 },
264 { X86::XOR32rr, X86::XOR32mr, 0 },
265 { X86::XOR64ri32, X86::XOR64mi32, 0 },
266 { X86::XOR64ri8, X86::XOR64mi8, 0 },
267 { X86::XOR64rr, X86::XOR64mr, 0 },
268 { X86::XOR8ri, X86::XOR8mi, 0 },
269 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]270 };
271
272 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]273 unsigned RegOp = OpTbl2Addr[i].RegOp;
274 unsigned MemOp = OpTbl2Addr[i].MemOp;
275 unsigned Flags = OpTbl2Addr[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]276 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
277 RegOp, MemOp,
278 // Index 0, folded load and store, no alignment requirement.
279 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]280 }
281
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]282 static const X86OpTblEntry OpTbl0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]283 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
284 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
285 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
286 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
287 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]288 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
289 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
290 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
291 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
292 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
293 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
294 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
295 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
296 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
297 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
298 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
299 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
300 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
301 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
302 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]303 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]304 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
305 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
306 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
307 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
308 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
309 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
310 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
311 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
312 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
313 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
314 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
315 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
316 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
317 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
318 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
319 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
320 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
321 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
322 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
325 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]326 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
327 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
328 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
329 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
330 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
331 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]332 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
333 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
334 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
335 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]336 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
337 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]338 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
339 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
340 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
341 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
342 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
343 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
344 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
345 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
346 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
347 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
348 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
349 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
350 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
351 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
352 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
353 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
354 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
355 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]356 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]357 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
358 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
359 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]360 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]361
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]362 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]363 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]364 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]365 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
367 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
368 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
369 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
370 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
371 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
372 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
373 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]374 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
375 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]376
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]377 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]378 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]379 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
380 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
381 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
382 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]383 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]384
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]385 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]386 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
387 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
388 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
389 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
390 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
391 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
392 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]393 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
394 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]395 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]396 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]397
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]398 // AVX-512 foldable instructions (256-bit versions)
399 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
400 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
401 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
402 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
403 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
404 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
405 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
406 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
407 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
408 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]409
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]410 // AVX-512 foldable instructions (128-bit versions)
411 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
412 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
413 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
414 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
415 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
416 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
417 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
418 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
419 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]420 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]421
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]422 // F16C foldable instructions
423 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
424 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]425 };
426
427 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]428 unsigned RegOp = OpTbl0[i].RegOp;
429 unsigned MemOp = OpTbl0[i].MemOp;
430 unsigned Flags = OpTbl0[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]431 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
432 RegOp, MemOp, TB_INDEX_0 | Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]433 }
434
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]435 static const X86OpTblEntry OpTbl1[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]436 { X86::CMP16rr, X86::CMP16rm, 0 },
437 { X86::CMP32rr, X86::CMP32rm, 0 },
438 { X86::CMP64rr, X86::CMP64rm, 0 },
439 { X86::CMP8rr, X86::CMP8rm, 0 },
440 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
441 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
442 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
443 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
444 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
445 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
446 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
447 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
448 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
449 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]450 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
451 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
452 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
453 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
454 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
455 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
456 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
457 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]458 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
459 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]460 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
461 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]462 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]463 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]464 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]465 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]466 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]467 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]468 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
469 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
470 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
471 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
472 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
473 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
474 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
475 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]476 { X86::MOV16rr, X86::MOV16rm, 0 },
477 { X86::MOV32rr, X86::MOV32rm, 0 },
478 { X86::MOV64rr, X86::MOV64rm, 0 },
479 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
480 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
481 { X86::MOV8rr, X86::MOV8rm, 0 },
482 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
483 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]484 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
485 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
486 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
487 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]488 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
489 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
490 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
491 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
492 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
493 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
494 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
495 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
496 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
497 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]498 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
499 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
500 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
501 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
502 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
503 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]504 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
505 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
506 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]507 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
508 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
509 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
510 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
511 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
512 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
513 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
514 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
515 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
516 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
517 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
518 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
519 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
520 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
521 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
522 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
523 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]524 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
525 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
526 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]527 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]528 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
529 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]530 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
531 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]532 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
533 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
534 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
535 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
536 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]537 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]538 { X86::SQRTSDr, X86::SQRTSDm, 0 },
539 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
540 { X86::SQRTSSr, X86::SQRTSSm, 0 },
541 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
542 { X86::TEST16rr, X86::TEST16rm, 0 },
543 { X86::TEST32rr, X86::TEST32rm, 0 },
544 { X86::TEST64rr, X86::TEST64rm, 0 },
545 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]546 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]547 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
548 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]549
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]550 // AVX 128-bit versions of foldable instructions
551 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
552 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]553 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
554 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]555 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
556 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]557 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]558 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
559 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
560 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
561 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
562 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
563 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
564 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
565 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
566 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]567 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]568 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]569 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]570 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]571 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]572 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]573 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
574 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]575 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
576 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
577 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
578 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
579 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
580 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
581 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
582 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]583 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
584 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]585 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]586 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]587 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
588 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]589 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
590 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
591 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]592 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
593 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
594 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
595 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
596 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]597 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
598 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]599 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
600 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
601 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
602 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
603 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
604 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
605 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
606 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
607 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
608 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
609 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
610 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]611 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
612 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
613 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]614 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]615 { X86::VRCPPSr, X86::VRCPPSm, 0 },
616 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]617 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
618 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]619 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
620 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 },
621 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]622 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]623 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
624 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]625 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]626 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]627
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]628 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]629 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]630 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]631 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]632 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]633 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]634 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]635 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
636 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]637 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
638 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]639 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]640 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]641 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
642 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]643 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]644 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]645 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
646 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]647 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]648 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
649 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]650 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
651 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]652 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]653 { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]654 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
655 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]656 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
657 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]658
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]659 // AVX2 foldable instructions
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]660 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
661 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
662 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]663 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
664 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
665 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]666 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
667 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
668 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
669 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
670 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
671 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
672 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
673 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
674 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
675 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
676 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
677 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
678 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
679 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
680 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
681 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
682 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
683 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
684 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
685 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
686 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
687 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]688 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
689 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
690 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]691
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]692 // XOP foldable instructions
693 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
694 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
695 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
696 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
697 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
698 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
699 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
700 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
701 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
702 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
703 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
704 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
705 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
706 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
707 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
708 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
709 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
710 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
711 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
712 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
713 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
714 { X86::VPROTBri, X86::VPROTBmi, 0 },
715 { X86::VPROTBrr, X86::VPROTBmr, 0 },
716 { X86::VPROTDri, X86::VPROTDmi, 0 },
717 { X86::VPROTDrr, X86::VPROTDmr, 0 },
718 { X86::VPROTQri, X86::VPROTQmi, 0 },
719 { X86::VPROTQrr, X86::VPROTQmr, 0 },
720 { X86::VPROTWri, X86::VPROTWmi, 0 },
721 { X86::VPROTWrr, X86::VPROTWmr, 0 },
722 { X86::VPSHABrr, X86::VPSHABmr, 0 },
723 { X86::VPSHADrr, X86::VPSHADmr, 0 },
724 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
725 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
726 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
727 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
728 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
729 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
730
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]731 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]732 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
733 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]734 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
735 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
736 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
737 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
738 { X86::BLCI32rr, X86::BLCI32rm, 0 },
739 { X86::BLCI64rr, X86::BLCI64rm, 0 },
740 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
741 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
742 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
743 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
744 { X86::BLCS32rr, X86::BLCS32rm, 0 },
745 { X86::BLCS64rr, X86::BLCS64rm, 0 },
746 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
747 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]748 { X86::BLSI32rr, X86::BLSI32rm, 0 },
749 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]750 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
751 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]752 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
753 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
754 { X86::BLSR32rr, X86::BLSR32rm, 0 },
755 { X86::BLSR64rr, X86::BLSR64rm, 0 },
756 { X86::BZHI32rr, X86::BZHI32rm, 0 },
757 { X86::BZHI64rr, X86::BZHI64rm, 0 },
758 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
759 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
760 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
761 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
762 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
763 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]764 { X86::RORX32ri, X86::RORX32mi, 0 },
765 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]766 { X86::SARX32rr, X86::SARX32rm, 0 },
767 { X86::SARX64rr, X86::SARX64rm, 0 },
768 { X86::SHRX32rr, X86::SHRX32rm, 0 },
769 { X86::SHRX64rr, X86::SHRX64rm, 0 },
770 { X86::SHLX32rr, X86::SHLX32rm, 0 },
771 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]772 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
773 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]774 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
775 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
776 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]777 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
778 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]779
780 // AVX-512 foldable instructions
781 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
782 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]783 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
784 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]785 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
786 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]787 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
788 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]789 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
790 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]791 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
792 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]793 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
794 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]795 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
796 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]797
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]798 // AVX-512 foldable instructions (256-bit versions)
799 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
800 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
801 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
802 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
803 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
804 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
805 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
806 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
807 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
808 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]809 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
810 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]811
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]812 // AVX-512 foldable instructions (256-bit versions)
813 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
814 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
815 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
816 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
817 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
818 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
819 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
820 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
821 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
822 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]823 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]824
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]825 // F16C foldable instructions
826 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
827 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]828
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]829 // AES foldable instructions
830 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
831 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
Simon Pilgrim295eaad2015-02-12 20:01:03 +0000[diff] [blame]832 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
833 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]834 };
835
836 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]837 unsigned RegOp = OpTbl1[i].RegOp;
838 unsigned MemOp = OpTbl1[i].MemOp;
839 unsigned Flags = OpTbl1[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]840 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
841 RegOp, MemOp,
842 // Index 1, folded load
843 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]844 }
845
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]846 static const X86OpTblEntry OpTbl2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]847 { X86::ADC32rr, X86::ADC32rm, 0 },
848 { X86::ADC64rr, X86::ADC64rm, 0 },
849 { X86::ADD16rr, X86::ADD16rm, 0 },
850 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
851 { X86::ADD32rr, X86::ADD32rm, 0 },
852 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
853 { X86::ADD64rr, X86::ADD64rm, 0 },
854 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
855 { X86::ADD8rr, X86::ADD8rm, 0 },
856 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
857 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
858 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]859 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]860 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]861 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]862 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
863 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
864 { X86::AND16rr, X86::AND16rm, 0 },
865 { X86::AND32rr, X86::AND32rm, 0 },
866 { X86::AND64rr, X86::AND64rm, 0 },
867 { X86::AND8rr, X86::AND8rm, 0 },
868 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
869 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
870 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
871 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]872 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
873 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
874 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
875 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]876 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
877 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
878 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
879 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
880 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
881 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
882 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
883 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
884 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
885 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
886 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
887 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
888 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
889 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
890 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
891 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
892 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
893 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
894 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
895 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
896 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
897 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
898 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
899 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
900 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
901 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
902 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
903 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
904 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
905 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
906 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
907 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
908 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
909 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
910 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
911 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
912 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
913 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
914 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
915 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
916 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
917 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
918 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
919 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
920 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
921 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
922 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
923 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
924 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
925 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
926 { X86::CMPSDrr, X86::CMPSDrm, 0 },
927 { X86::CMPSSrr, X86::CMPSSrm, 0 },
928 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
929 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
930 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]931 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]932 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]933 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
934 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
935 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame^]936
937 // FIXME: We should not be folding Fs* scalar loads into vector
938 // instructions because the vector instructions require vector-sized
939 // loads. Lowering should create vector-sized instructions (the Fv*
940 // variants below) to allow load folding.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]941 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
942 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
943 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
944 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
945 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
946 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
947 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
948 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame^]949
950 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
951 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
952 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
953 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
954 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
955 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
956 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
957 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]958 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
959 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
960 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
961 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
962 { X86::IMUL16rr, X86::IMUL16rm, 0 },
963 { X86::IMUL32rr, X86::IMUL32rm, 0 },
964 { X86::IMUL64rr, X86::IMUL64rm, 0 },
965 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
966 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]967 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
968 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
969 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
970 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
971 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
972 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]973 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]974 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]975 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]976 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]977 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]978 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]979 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]980 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]981 { X86::MINSDrr, X86::MINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]982 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]983 { X86::MINSSrr, X86::MINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]984 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]985 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]986 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
987 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
988 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]989 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]990 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]991 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]992 { X86::OR16rr, X86::OR16rm, 0 },
993 { X86::OR32rr, X86::OR32rm, 0 },
994 { X86::OR64rr, X86::OR64rm, 0 },
995 { X86::OR8rr, X86::OR8rm, 0 },
996 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
997 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
998 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
999 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1000 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1001 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1002 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1003 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1004 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1005 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1006 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1007 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1008 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1009 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1010 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1011 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1012 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1013 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1014 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1015 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1016 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1017 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1018 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1019 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1020 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1021 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1022 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1023 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1024 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1025 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1026 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1027 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1028 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1029 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1030 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1031 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1032 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1033 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1034 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1035 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1036 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1037 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1038 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1039 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1040 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1041 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1042 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1043 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1044 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1045 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1046 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1047 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1048 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1049 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1050 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1051 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1052 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1053 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1054 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1055 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1056 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1057 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1058 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1059 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
1060 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
1061 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
1062 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1063 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1064 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1065 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1066 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1067 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1068 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1069 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1070 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1071 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1072 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1073 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1074 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1075 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1076 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1077 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1078 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1079 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1080 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1081 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1082 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1083 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1084 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1085 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1086 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1087 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
1088 { X86::SBB32rr, X86::SBB32rm, 0 },
1089 { X86::SBB64rr, X86::SBB64rm, 0 },
1090 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1091 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1092 { X86::SUB16rr, X86::SUB16rm, 0 },
1093 { X86::SUB32rr, X86::SUB32rm, 0 },
1094 { X86::SUB64rr, X86::SUB64rm, 0 },
1095 { X86::SUB8rr, X86::SUB8rm, 0 },
1096 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1097 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1098 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1099 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1100 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1101 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1102 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1103 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1104 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1105 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1106 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1107 { X86::XOR16rr, X86::XOR16rm, 0 },
1108 { X86::XOR32rr, X86::XOR32rm, 0 },
1109 { X86::XOR64rr, X86::XOR64rm, 0 },
1110 { X86::XOR8rr, X86::XOR8rm, 0 },
1111 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1112 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1113
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1114 // AVX 128-bit versions of foldable instructions
1115 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1116 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1117 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1118 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1119 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1120 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1121 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1122 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1123 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1124 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1125 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1126 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1127 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1128 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
1129 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
1130 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1131 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1132 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1133 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1134 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1135 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1136 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1137 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1138 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1139 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1140 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1141 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1142 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1143 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1144 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1145 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1146 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1147 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1148 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1149 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1150 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1151 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1152 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1153 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1154 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1155 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1156 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1157 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1158 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame^]1159 // Do not fold VFs* loads because there are no scalar load variants for
1160 // these instructions. When folded, the load is required to be 128-bits, so
1161 // the load size would not match.
1162 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1163 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1164 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1165 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1166 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1167 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1168 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1169 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1170 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1171 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1172 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1173 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1174 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1175 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1176 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1177 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1178 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1179 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1180 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1181 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1182 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1183 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1184 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1185 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1186 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1187 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1188 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1189 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1190 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1191 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1192 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1193 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1194 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1195 { X86::VORPDrr, X86::VORPDrm, 0 },
1196 { X86::VORPSrr, X86::VORPSrm, 0 },
1197 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1198 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1199 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1200 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1201 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1202 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1203 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1204 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1205 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1206 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1207 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1208 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1209 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1210 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1211 { X86::VPANDrr, X86::VPANDrm, 0 },
1212 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1213 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1214 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1215 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1216 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1217 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1218 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1219 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1220 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1221 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1222 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1223 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1224 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1225 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1226 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1227 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1228 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1229 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1230 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1231 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1232 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1233 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1234 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1235 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1236 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1237 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1238 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1239 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1240 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1241 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1242 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1243 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1244 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1245 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1246 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1247 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1248 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1249 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1250 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1251 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1252 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1253 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1254 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1255 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1256 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1257 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1258 { X86::VPORrr, X86::VPORrm, 0 },
1259 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1260 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1261 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
1262 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
1263 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
1264 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1265 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1266 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1267 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1268 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1269 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1270 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1271 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1272 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1273 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1274 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1275 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1276 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1277 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1278 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1279 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1280 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1281 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1282 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1283 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1284 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1285 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1286 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1287 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1288 { X86::VPXORrr, X86::VPXORrm, 0 },
1289 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1290 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1291 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1292 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1293 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1294 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1295 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1296 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1297 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1298 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1299 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1300 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1301 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1302 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1303
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1304 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1305 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1306 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1307 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1308 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1309 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1310 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1311 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1312 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1313 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1314 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1315 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1316 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1317 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1318 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1319 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1320 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1321 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1322 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1323 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1324 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1325 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1326 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1327 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1328 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1329 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1330 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1331 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1332 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1333 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1334 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1335 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1336 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1337 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1338 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1339 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1340 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1341 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1342 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1343 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1344 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1345 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1346 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1347 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1348
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1349 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1350 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1351 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1352 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1353 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1354 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1355 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1356 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1357 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1358 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1359 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1360 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1361 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1362 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1363 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1364 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1365 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1366 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1367 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1368 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1369 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1370 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1371 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1372 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1373 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1374 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1375 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1376 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1377 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1378 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1379 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1380 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1381 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1382 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1383 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1384 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1385 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1386 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1387 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1388 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1389 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1390 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1391 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1392 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1393 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1394 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1395 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1396 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1397 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1398 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1399 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1400 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1401 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1402 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1403 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1404 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1405 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1406 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1407 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1408 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1409 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1410 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1411 { X86::VPORYrr, X86::VPORYrm, 0 },
1412 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1413 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1414 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1415 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1416 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1417 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1418 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1419 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1420 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1421 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1422 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1423 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1424 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1425 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1426 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1427 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1428 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1429 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1430 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1431 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1432 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1433 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1434 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1435 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1436 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1437 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1438 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1439 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1440 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1441 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1442 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1443 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1444 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1445 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1446 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1447 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1448 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1449 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1450 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1451 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1452
1453 // FMA4 foldable patterns
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1454 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1455 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
1456 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, 0 },
1457 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, 0 },
1458 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, 0 },
1459 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, 0 },
1460 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1461 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
1462 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, 0 },
1463 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, 0 },
1464 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, 0 },
1465 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, 0 },
1466 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1467 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
1468 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, 0 },
1469 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, 0 },
1470 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, 0 },
1471 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, 0 },
1472 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1473 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
1474 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, 0 },
1475 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, 0 },
1476 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, 0 },
1477 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, 0 },
1478 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, 0 },
1479 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, 0 },
1480 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, 0 },
1481 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, 0 },
1482 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, 0 },
1483 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, 0 },
1484 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, 0 },
1485 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1486
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1487 // XOP foldable instructions
1488 { X86::VPCMOVrr, X86::VPCMOVmr, 0 },
1489 { X86::VPCMOVrrY, X86::VPCMOVmrY, 0 },
1490 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1491 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1492 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1493 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1494 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1495 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1496 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1497 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1498 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1499 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1500 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1501 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1502 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1503 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1504 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1505 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1506 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1507 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1508 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1509 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1510 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1511 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1512 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1513 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
1514 { X86::VPPERMrr, X86::VPPERMmr, 0 },
1515 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1516 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1517 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1518 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1519 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1520 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1521 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1522 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1523 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1524 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1525 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1526 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1527
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1528 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1529 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1530 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1531 { X86::MULX32rr, X86::MULX32rm, 0 },
1532 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1533 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1534 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1535 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1536 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1537
1538 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1539 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1540 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1541 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1542 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1543 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1544 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1545 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1546 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1547 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1548 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1549 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1550 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1551 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1552 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1553 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1554 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1555 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1556 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1557 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1558 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1559 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1560 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1561 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1562 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1563 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1564 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1565 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1566 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1567 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1568 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1569 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1570 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1571 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1572 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1573 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },
1574 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1575 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1576 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1577 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1578
1579 // AVX-512{F,VL} foldable instructions
1580 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1581 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1582 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1583
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1584 // AVX-512{F,VL} foldable instructions
1585 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1586 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1587 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1588 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1589
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1590 // AES foldable instructions
1591 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1592 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1593 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1594 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1595 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1596 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1597 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1598 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1599
1600 // SHA foldable instructions
1601 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1602 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1603 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1604 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1605 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1606 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1607 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1608 };
1609
1610 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]1611 unsigned RegOp = OpTbl2[i].RegOp;
1612 unsigned MemOp = OpTbl2[i].MemOp;
1613 unsigned Flags = OpTbl2[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1614 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1615 RegOp, MemOp,
1616 // Index 2, folded load
1617 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1618 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1619
1620 static const X86OpTblEntry OpTbl3[] = {
1621 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1622 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1623 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1624 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1625 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1626 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1627 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1628
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1629 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1630 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1631 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1632 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1633 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1634 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1635 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1636 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1637 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1638 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1639 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1640 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1641
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1642 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1643 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1644 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1645 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1646 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1647 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1648
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1649 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1650 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1651 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1652 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1653 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1654 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1655 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1656 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1657 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1658 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1659 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1660 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1661
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1662 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1663 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1664 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1665 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1666 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1667 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1668
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1669 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1670 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1671 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1672 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1673 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1674 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1675 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1676 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1677 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1678 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1679 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1680 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1681
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1682 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1683 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1684 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1685 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1686 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1687 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1688
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1689 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1690 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1691 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1692 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1693 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1694 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1695 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1696 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1697 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1698 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1699 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1700 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1701
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1702 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1703 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1704 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1705 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1706 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1707 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1708 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1709 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1710 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1711 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1712 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1713 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1714
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1715 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1716 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1717 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1718 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1719 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1720 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1721 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1722 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1723 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1724 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1725 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1726 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1727
1728 // FMA4 foldable patterns
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1729 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1730 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1731 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1732 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1733 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1734 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1735 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1736 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1737 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1738 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1739 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1740 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1741 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1742 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1743 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1744 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1745 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1746 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1747 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1748 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1749 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1750 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1751 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1752 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1753 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1754 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1755 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1756 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1757 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1758 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1759 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1760 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1761
1762 // XOP foldable instructions
1763 { X86::VPCMOVrr, X86::VPCMOVrm, 0 },
1764 { X86::VPCMOVrrY, X86::VPCMOVrmY, 0 },
1765 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1766 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1767 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1768 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
1769 { X86::VPPERMrr, X86::VPPERMrm, 0 },
1770
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1771 // AVX-512 VPERMI instructions with 3 source operands.
1772 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1773 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1774 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1775 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1776 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1777 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1778 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1779 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1780 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1781 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1782 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1783 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1784 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1785 // AVX-512 arithmetic instructions
1786 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1787 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1788 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1789 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1790 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1791 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1792 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1793 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1794 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1795 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1796 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1797 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1798 // AVX-512{F,VL} arithmetic instructions 256-bit
1799 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1800 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1801 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1802 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1803 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1804 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1805 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1806 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1807 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1808 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1809 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1810 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1811 // AVX-512{F,VL} arithmetic instructions 128-bit
1812 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1813 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1814 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1815 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1816 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1817 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1818 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1819 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1820 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1821 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1822 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1823 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1824 };
1825
1826 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1827 unsigned RegOp = OpTbl3[i].RegOp;
1828 unsigned MemOp = OpTbl3[i].MemOp;
1829 unsigned Flags = OpTbl3[i].Flags;
1830 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1831 RegOp, MemOp,
1832 // Index 3, folded load
1833 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1834 }
1835
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1836 static const X86OpTblEntry OpTbl4[] = {
1837 // AVX-512 foldable instructions
1838 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1839 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1840 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
1841 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
1842 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
1843 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
1844 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
1845 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
1846 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
1847 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
1848 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
1849 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
1850 // AVX-512{F,VL} foldable instructions 256-bit
1851 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
1852 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
1853 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
1854 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
1855 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
1856 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
1857 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
1858 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
1859 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
1860 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
1861 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
1862 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
1863 // AVX-512{F,VL} foldable instructions 128-bit
1864 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
1865 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
1866 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
1867 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
1868 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
1869 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
1870 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
1871 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
1872 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
1873 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
1874 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
1875 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
1876 };
1877
1878 for (unsigned i = 0, e = array_lengthof(OpTbl4); i != e; ++i) {
1879 unsigned RegOp = OpTbl4[i].RegOp;
1880 unsigned MemOp = OpTbl4[i].MemOp;
1881 unsigned Flags = OpTbl4[i].Flags;
1882 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1883 RegOp, MemOp,
1884 // Index 4, folded load
1885 Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
1886 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]1887}
1888
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1889void
1890X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1891 MemOp2RegOpTableType &M2RTable,
1892 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1893 if ((Flags & TB_NO_FORWARD) == 0) {
1894 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1895 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1896 }
1897 if ((Flags & TB_NO_REVERSE) == 0) {
1898 assert(!M2RTable.count(MemOp) &&
1899 "Duplicated entries in unfolding maps?");
1900 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1901 }
1902}
1903
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1904bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1905X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1906 unsigned &SrcReg, unsigned &DstReg,
1907 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1908 switch (MI.getOpcode()) {
1909 default: break;
1910 case X86::MOVSX16rr8:
1911 case X86::MOVZX16rr8:
1912 case X86::MOVSX32rr8:
1913 case X86::MOVZX32rr8:
1914 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]1915 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]1916 // It's not always legal to reference the low 8-bit of the larger
1917 // register in 32-bit mode.
1918 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1919 case X86::MOVSX32rr16:
1920 case X86::MOVZX32rr16:
1921 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]1922 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1923 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1924 // Be conservative.
1925 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1926 SrcReg = MI.getOperand(1).getReg();
1927 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1928 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]1929 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1930 case X86::MOVSX16rr8:
1931 case X86::MOVZX16rr8:
1932 case X86::MOVSX32rr8:
1933 case X86::MOVZX32rr8:
1934 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1935 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1936 break;
1937 case X86::MOVSX32rr16:
1938 case X86::MOVZX32rr16:
1939 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1940 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1941 break;
1942 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1943 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1944 break;
1945 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1946 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1947 }
1948 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1949 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1950}
1951
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]1952int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
1953 const MachineFunction *MF = MI->getParent()->getParent();
1954 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
1955
1956 if (MI->getOpcode() == getCallFrameSetupOpcode() ||
1957 MI->getOpcode() == getCallFrameDestroyOpcode()) {
1958 unsigned StackAlign = TFI->getStackAlignment();
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1959 int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]1960 StackAlign;
1961
1962 SPAdj -= MI->getOperand(1).getImm();
1963
1964 if (MI->getOpcode() == getCallFrameSetupOpcode())
1965 return SPAdj;
1966 else
1967 return -SPAdj;
1968 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1969
1970 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]1971 // that is bound to the following ADJCALLSTACKUP pseudo.
1972 // Look for the next ADJCALLSTACKUP that follows the call.
1973 if (MI->isCall()) {
1974 const MachineBasicBlock* MBB = MI->getParent();
1975 auto I = ++MachineBasicBlock::const_iterator(MI);
1976 for (auto E = MBB->end(); I != E; ++I) {
1977 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
1978 I->isCall())
1979 break;
1980 }
1981
1982 // If we could not find a frame destroy opcode, then it has already
1983 // been simplified, so we don't care.
1984 if (I->getOpcode() != getCallFrameDestroyOpcode())
1985 return 0;
1986
1987 return -(I->getOperand(1).getImm());
1988 }
1989
1990 // Currently handle only PUSHes we can reasonably expect to see
1991 // in call sequences
1992 switch (MI->getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1993 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]1994 return 0;
1995 case X86::PUSH32i8:
1996 case X86::PUSH32r:
1997 case X86::PUSH32rmm:
1998 case X86::PUSH32rmr:
1999 case X86::PUSHi32:
2000 return 4;
2001 }
2002}
2003
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2004/// isFrameOperand - Return true and the FrameIndex if the specified
2005/// operand and follow operands form a reference to the stack frame.
2006bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2007 int &FrameIndex) const {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2008 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2009 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2010 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2011 MI->getOperand(Op+X86::AddrDisp).isImm() &&
2012 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2013 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2014 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2015 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2016 return true;
2017 }
2018 return false;
2019}
2020
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2021static bool isFrameLoadOpcode(int Opcode) {
2022 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2023 default:
2024 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2025 case X86::MOV8rm:
2026 case X86::MOV16rm:
2027 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2028 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2029 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2030 case X86::MOVSSrm:
2031 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2032 case X86::MOVAPSrm:
2033 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2034 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2035 case X86::VMOVSSrm:
2036 case X86::VMOVSDrm:
2037 case X86::VMOVAPSrm:
2038 case X86::VMOVAPDrm:
2039 case X86::VMOVDQArm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2040 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2041 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2042 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2043 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2044 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2045 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2046 case X86::MMX_MOVD64rm:
2047 case X86::MMX_MOVQ64rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2048 case X86::VMOVAPSZrm:
2049 case X86::VMOVUPSZrm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2050 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2051 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2052}
2053
2054static bool isFrameStoreOpcode(int Opcode) {
2055 switch (Opcode) {
2056 default: break;
2057 case X86::MOV8mr:
2058 case X86::MOV16mr:
2059 case X86::MOV32mr:
2060 case X86::MOV64mr:
2061 case X86::ST_FpP64m:
2062 case X86::MOVSSmr:
2063 case X86::MOVSDmr:
2064 case X86::MOVAPSmr:
2065 case X86::MOVAPDmr:
2066 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2067 case X86::VMOVSSmr:
2068 case X86::VMOVSDmr:
2069 case X86::VMOVAPSmr:
2070 case X86::VMOVAPDmr:
2071 case X86::VMOVDQAmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2072 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2073 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2074 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2075 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2076 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2077 case X86::VMOVDQAYmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2078 case X86::VMOVUPSZmr:
2079 case X86::VMOVAPSZmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2080 case X86::MMX_MOVD64mr:
2081 case X86::MMX_MOVQ64mr:
2082 case X86::MMX_MOVNTQmr:
2083 return true;
2084 }
2085 return false;
2086}
2087
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2088unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2089 int &FrameIndex) const {
2090 if (isFrameLoadOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2091 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2092 return MI->getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2093 return 0;
2094}
2095
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2096unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2097 int &FrameIndex) const {
2098 if (isFrameLoadOpcode(MI->getOpcode())) {
2099 unsigned Reg;
2100 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2101 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2102 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2103 const MachineMemOperand *Dummy;
2104 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2105 }
2106 return 0;
2107}
2108
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]2109unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2110 int &FrameIndex) const {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2111 if (isFrameStoreOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2112 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2113 isFrameOperand(MI, 0, FrameIndex))
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]2114 return MI->getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2115 return 0;
2116}
2117
2118unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2119 int &FrameIndex) const {
2120 if (isFrameStoreOpcode(MI->getOpcode())) {
2121 unsigned Reg;
2122 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2123 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2124 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2125 const MachineMemOperand *Dummy;
2126 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2127 }
2128 return 0;
2129}
2130
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2131/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
2132/// X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2133static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2134 // Don't waste compile time scanning use-def chains of physregs.
2135 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2136 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2137 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2138 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2139 E = MRI.def_instr_end(); I != E; ++I) {
2140 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2141 if (DefMI->getOpcode() != X86::MOVPC32r)
2142 return false;
2143 assert(!isPICBase && "More than one PIC base?");
2144 isPICBase = true;
2145 }
2146 return isPICBase;
2147}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2148
Bill Wendling1e117682008-05-12 20:54:26 +0000[diff] [blame]2149bool
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]2150X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2151 AliasAnalysis *AA) const {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2152 switch (MI->getOpcode()) {
2153 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2154 case X86::MOV8rm:
2155 case X86::MOV16rm:
2156 case X86::MOV32rm:
2157 case X86::MOV64rm:
2158 case X86::LD_Fp64m:
2159 case X86::MOVSSrm:
2160 case X86::MOVSDrm:
2161 case X86::MOVAPSrm:
2162 case X86::MOVUPSrm:
2163 case X86::MOVAPDrm:
2164 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2165 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2166 case X86::VMOVSSrm:
2167 case X86::VMOVSDrm:
2168 case X86::VMOVAPSrm:
2169 case X86::VMOVUPSrm:
2170 case X86::VMOVAPDrm:
2171 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2172 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2173 case X86::VMOVAPSYrm:
2174 case X86::VMOVUPSYrm:
2175 case X86::VMOVAPDYrm:
2176 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2177 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2178 case X86::MMX_MOVD64rm:
2179 case X86::MMX_MOVQ64rm:
2180 case X86::FsVMOVAPSrm:
2181 case X86::FsVMOVAPDrm:
2182 case X86::FsMOVAPSrm:
2183 case X86::FsMOVAPDrm: {
2184 // Loads from constant pools are trivially rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2185 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2186 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2187 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2188 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2189 MI->isInvariantLoad(AA)) {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2190 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2191 if (BaseReg == 0 || BaseReg == X86::RIP)
2192 return true;
2193 // Allow re-materialization of PIC load.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2194 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2195 return false;
2196 const MachineFunction &MF = *MI->getParent()->getParent();
2197 const MachineRegisterInfo &MRI = MF.getRegInfo();
2198 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2199 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2200 return false;
2201 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2202
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2203 case X86::LEA32r:
2204 case X86::LEA64r: {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2205 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2206 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2207 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2208 !MI->getOperand(1+X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2209 // lea fi#, lea GV, etc. are all rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2210 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2211 return true;
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2212 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2213 if (BaseReg == 0)
2214 return true;
2215 // Allow re-materialization of lea PICBase + x.
2216 const MachineFunction &MF = *MI->getParent()->getParent();
2217 const MachineRegisterInfo &MRI = MF.getRegInfo();
2218 return regIsPICBase(BaseReg, MRI);
2219 }
2220 return false;
2221 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2222 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2223
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2224 // All other instructions marked M_REMATERIALIZABLE are always trivially
2225 // rematerializable.
2226 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2227}
2228
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2229bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2230 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2231 MachineBasicBlock::iterator E = MBB.end();
2232
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2233 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2234 // safety after visiting 4 instructions in each direction, we will assume
2235 // it's not safe.
2236 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2237 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2238 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2239 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2240 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2241 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2242 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2243 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2244 continue;
2245 if (MO.getReg() == X86::EFLAGS) {
2246 if (MO.isUse())
2247 return false;
2248 SeenDef = true;
2249 }
2250 }
2251
2252 if (SeenDef)
2253 // This instruction defines EFLAGS, no need to look any further.
2254 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2255 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2256 // Skip over DBG_VALUE.
2257 while (Iter != E && Iter->isDebugValue())
2258 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2259 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2260
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2261 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2262 // live in.
2263 if (Iter == E) {
2264 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2265 SE = MBB.succ_end(); SI != SE; ++SI)
2266 if ((*SI)->isLiveIn(X86::EFLAGS))
2267 return false;
2268 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2269 }
2270
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2271 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2272 Iter = I;
2273 for (unsigned i = 0; i < 4; ++i) {
2274 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2275 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2276 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2277 return !MBB.isLiveIn(X86::EFLAGS);
2278
2279 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2280 // Skip over DBG_VALUE.
2281 while (Iter != B && Iter->isDebugValue())
2282 --Iter;
2283
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2284 bool SawKill = false;
2285 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2286 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2287 // A register mask may clobber EFLAGS, but we should still look for a
2288 // live EFLAGS def.
2289 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2290 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2291 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2292 if (MO.isDef()) return MO.isDead();
2293 if (MO.isKill()) SawKill = true;
2294 }
2295 }
2296
2297 if (SawKill)
2298 // This instruction kills EFLAGS and doesn't redefine it, so
2299 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2300 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2301 }
2302
2303 // Conservative answer.
2304 return false;
2305}
2306
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2307void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2308 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2309 unsigned DestReg, unsigned SubIdx,
Evan Cheng6ad7da92009-11-14 02:55:43 +0000[diff] [blame]2310 const MachineInstr *Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2311 const TargetRegisterInfo &TRI) const {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2312 // MOV32r0 is implemented with a xor which clobbers condition code.
2313 // Re-materialize it as movri instructions to avoid side effects.
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2314 unsigned Opc = Orig->getOpcode();
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2315 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2316 DebugLoc DL = Orig->getDebugLoc();
2317 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2318 .addImm(0);
2319 } else {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2320 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2321 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2322 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2323
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2324 MachineInstr *NewMI = std::prev(I);
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2325 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2326}
2327
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2328/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
2329/// is not marked dead.
2330static bool hasLiveCondCodeDef(MachineInstr *MI) {
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2331 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2332 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2333 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2334 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2335 return true;
2336 }
2337 }
2338 return false;
2339}
2340
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2341/// getTruncatedShiftCount - check whether the shift count for a machine operand
2342/// is non-zero.
2343inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2344 unsigned ShiftAmtOperandIdx) {
2345 // The shift count is six bits with the REX.W prefix and five bits without.
2346 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2347 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2348 return Imm & ShiftCountMask;
2349}
2350
2351/// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
2352/// can be represented by a LEA instruction.
2353inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2354 // Left shift instructions can be transformed into load-effective-address
2355 // instructions if we can encode them appropriately.
2356 // A LEA instruction utilizes a SIB byte to encode it's scale factor.
2357 // The SIB.scale field is two bits wide which means that we can encode any
2358 // shift amount less than 4.
2359 return ShAmt < 4 && ShAmt > 0;
2360}
2361
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2362bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2363 unsigned Opc, bool AllowSP,
2364 unsigned &NewSrc, bool &isKill, bool &isUndef,
2365 MachineOperand &ImplicitOp) const {
2366 MachineFunction &MF = *MI->getParent()->getParent();
2367 const TargetRegisterClass *RC;
2368 if (AllowSP) {
2369 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2370 } else {
2371 RC = Opc != X86::LEA32r ?
2372 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2373 }
2374 unsigned SrcReg = Src.getReg();
2375
2376 // For both LEA64 and LEA32 the register already has essentially the right
2377 // type (32-bit or 64-bit) we may just need to forbid SP.
2378 if (Opc != X86::LEA64_32r) {
2379 NewSrc = SrcReg;
2380 isKill = Src.isKill();
2381 isUndef = Src.isUndef();
2382
2383 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2384 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2385 return false;
2386
2387 return true;
2388 }
2389
2390 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2391 // another we need to add 64-bit registers to the final MI.
2392 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2393 ImplicitOp = Src;
2394 ImplicitOp.setImplicit();
2395
2396 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2397 MachineBasicBlock::LivenessQueryResult LQR =
2398 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2399
2400 switch (LQR) {
2401 case MachineBasicBlock::LQR_Unknown:
2402 // We can't give sane liveness flags to the instruction, abandon LEA
2403 // formation.
2404 return false;
2405 case MachineBasicBlock::LQR_Live:
2406 isKill = MI->killsRegister(SrcReg);
2407 isUndef = false;
2408 break;
2409 default:
2410 // The physreg itself is dead, so we have to use it as an <undef>.
2411 isKill = false;
2412 isUndef = true;
2413 break;
2414 }
2415 } else {
2416 // Virtual register of the wrong class, we have to create a temporary 64-bit
2417 // vreg to feed into the LEA.
2418 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2419 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2420 get(TargetOpcode::COPY))
2421 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2422 .addOperand(Src);
2423
2424 // Which is obviously going to be dead after we're done with it.
2425 isKill = true;
2426 isUndef = false;
2427 }
2428
2429 // We've set all the parameters without issue.
2430 return true;
2431}
2432
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2433/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2434/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
2435/// to a 32-bit superregister and then truncating back down to a 16-bit
2436/// subregister.
2437MachineInstr *
2438X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2439 MachineFunction::iterator &MFI,
2440 MachineBasicBlock::iterator &MBBI,
2441 LiveVariables *LV) const {
2442 MachineInstr *MI = MBBI;
2443 unsigned Dest = MI->getOperand(0).getReg();
2444 unsigned Src = MI->getOperand(1).getReg();
2445 bool isDead = MI->getOperand(0).isDead();
2446 bool isKill = MI->getOperand(1).isKill();
2447
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2448 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2449 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2450 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2451 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2452 Opc = X86::LEA64_32r;
2453 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2454 } else {
2455 Opc = X86::LEA32r;
2456 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2457 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2458
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2459 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2460 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2461 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2462 // movw (%rbp,%rcx,2), %dx
2463 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2464 // But testing has shown this *does* help performance in 64-bit mode (at
2465 // least on modern x86 machines).
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2466 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2467 MachineInstr *InsMI =
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2468 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2469 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2470 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2471
2472 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2473 get(Opc), leaOutReg);
2474 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2475 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2476 case X86::SHL16ri: {
2477 unsigned ShAmt = MI->getOperand(2).getImm();
2478 MIB.addReg(0).addImm(1 << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2479 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2480 break;
2481 }
2482 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2483 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2484 break;
2485 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2486 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2487 break;
2488 case X86::ADD16ri:
2489 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2490 case X86::ADD16ri_DB:
2491 case X86::ADD16ri8_DB:
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2492 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2493 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2494 case X86::ADD16rr:
2495 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2496 unsigned Src2 = MI->getOperand(2).getReg();
2497 bool isKill2 = MI->getOperand(2).isKill();
2498 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2499 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2500 if (Src == Src2) {
2501 // ADD16rr %reg1028<kill>, %reg1028
2502 // just a single insert_subreg.
2503 addRegReg(MIB, leaInReg, true, leaInReg, false);
2504 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2505 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2506 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2507 else
2508 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2509 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2510 // well be shifting and then extracting the lower 16-bits.
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2511 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2512 InsMI2 =
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2513 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2514 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2515 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2516 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2517 }
2518 if (LV && isKill2 && InsMI2)
2519 LV->replaceKillInstruction(Src2, MI, InsMI2);
2520 break;
2521 }
2522 }
2523
2524 MachineInstr *NewMI = MIB;
2525 MachineInstr *ExtMI =
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2526 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2527 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2528 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2529
2530 if (LV) {
2531 // Update live variables
2532 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2533 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2534 if (isKill)
2535 LV->replaceKillInstruction(Src, MI, InsMI);
2536 if (isDead)
2537 LV->replaceKillInstruction(Dest, MI, ExtMI);
2538 }
2539
2540 return ExtMI;
2541}
2542
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2543/// convertToThreeAddress - This method must be implemented by targets that
2544/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2545/// may be able to convert a two-address instruction into a true
2546/// three-address instruction on demand. This allows the X86 target (for
2547/// example) to convert ADD and SHL instructions into LEA instructions if they
2548/// would require register copies due to two-addressness.
2549///
2550/// This method returns a null pointer if the transformation cannot be
2551/// performed, otherwise it returns the new instruction.
2552///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2553MachineInstr *
2554X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2555 MachineBasicBlock::iterator &MBBI,
Owen Anderson30cc0282008-07-02 23:41:07 +0000[diff] [blame]2556 LiveVariables *LV) const {
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2557 MachineInstr *MI = MBBI;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2558
2559 // The following opcodes also sets the condition code register(s). Only
2560 // convert them to equivalent lea if the condition code register def's
2561 // are dead!
2562 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2563 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2564
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2565 MachineFunction &MF = *MI->getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2566 // All instructions input are two-addr instructions. Get the known operands.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2567 const MachineOperand &Dest = MI->getOperand(0);
2568 const MachineOperand &Src = MI->getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2569
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2570 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2571 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2572 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2573 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2574 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2575 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2576
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2577 unsigned MIOpc = MI->getOpcode();
2578 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2579 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2580 case X86::SHL64ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2581 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2582 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2583 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2584
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2585 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2586 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2587 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2588 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2589 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2590
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2591 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2592 .addOperand(Dest)
2593 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2594 break;
2595 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2596 case X86::SHL32ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2597 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2598 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2599 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2600
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2601 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2602
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2603 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2604 bool isKill, isUndef;
2605 unsigned SrcReg;
2606 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2607 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2608 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2609 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2610
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2611 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2612 .addOperand(Dest)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2613 .addReg(0).addImm(1 << ShAmt)
2614 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2615 .addImm(0).addReg(0);
2616 if (ImplicitOp.getReg() != 0)
2617 MIB.addOperand(ImplicitOp);
2618 NewMI = MIB;
2619
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2620 break;
2621 }
2622 case X86::SHL16ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2623 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2624 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2625 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2626
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2627 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2628 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2629 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2630 .addOperand(Dest)
2631 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2632 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2633 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2634 case X86::INC64r:
2635 case X86::INC32r: {
2636 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2637 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2638 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2639 bool isKill, isUndef;
2640 unsigned SrcReg;
2641 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2642 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2643 SrcReg, isKill, isUndef, ImplicitOp))
2644 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2645
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2646 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2647 .addOperand(Dest)
2648 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2649 if (ImplicitOp.getReg() != 0)
2650 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2651
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2652 NewMI = addOffset(MIB, 1);
2653 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2654 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2655 case X86::INC16r:
2656 if (DisableLEA16)
2657 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2658 : nullptr;
2659 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2660 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2661 .addOperand(Dest).addOperand(Src), 1);
2662 break;
2663 case X86::DEC64r:
2664 case X86::DEC32r: {
2665 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2666 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2667 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2668
2669 bool isKill, isUndef;
2670 unsigned SrcReg;
2671 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2672 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2673 SrcReg, isKill, isUndef, ImplicitOp))
2674 return nullptr;
2675
2676 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2677 .addOperand(Dest)
2678 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2679 if (ImplicitOp.getReg() != 0)
2680 MIB.addOperand(ImplicitOp);
2681
2682 NewMI = addOffset(MIB, -1);
2683
2684 break;
2685 }
2686 case X86::DEC16r:
2687 if (DisableLEA16)
2688 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2689 : nullptr;
2690 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2691 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2692 .addOperand(Dest).addOperand(Src), -1);
2693 break;
2694 case X86::ADD64rr:
2695 case X86::ADD64rr_DB:
2696 case X86::ADD32rr:
2697 case X86::ADD32rr_DB: {
2698 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2699 unsigned Opc;
2700 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2701 Opc = X86::LEA64r;
2702 else
2703 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2704
2705 bool isKill, isUndef;
2706 unsigned SrcReg;
2707 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2708 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2709 SrcReg, isKill, isUndef, ImplicitOp))
2710 return nullptr;
2711
2712 const MachineOperand &Src2 = MI->getOperand(2);
2713 bool isKill2, isUndef2;
2714 unsigned SrcReg2;
2715 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2716 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2717 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2718 return nullptr;
2719
2720 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2721 .addOperand(Dest);
2722 if (ImplicitOp.getReg() != 0)
2723 MIB.addOperand(ImplicitOp);
2724 if (ImplicitOp2.getReg() != 0)
2725 MIB.addOperand(ImplicitOp2);
2726
2727 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2728
2729 // Preserve undefness of the operands.
2730 NewMI->getOperand(1).setIsUndef(isUndef);
2731 NewMI->getOperand(3).setIsUndef(isUndef2);
2732
2733 if (LV && Src2.isKill())
2734 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2735 break;
2736 }
2737 case X86::ADD16rr:
2738 case X86::ADD16rr_DB: {
2739 if (DisableLEA16)
2740 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2741 : nullptr;
2742 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2743 unsigned Src2 = MI->getOperand(2).getReg();
2744 bool isKill2 = MI->getOperand(2).isKill();
2745 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2746 .addOperand(Dest),
2747 Src.getReg(), Src.isKill(), Src2, isKill2);
2748
2749 // Preserve undefness of the operands.
2750 bool isUndef = MI->getOperand(1).isUndef();
2751 bool isUndef2 = MI->getOperand(2).isUndef();
2752 NewMI->getOperand(1).setIsUndef(isUndef);
2753 NewMI->getOperand(3).setIsUndef(isUndef2);
2754
2755 if (LV && isKill2)
2756 LV->replaceKillInstruction(Src2, MI, NewMI);
2757 break;
2758 }
2759 case X86::ADD64ri32:
2760 case X86::ADD64ri8:
2761 case X86::ADD64ri32_DB:
2762 case X86::ADD64ri8_DB:
2763 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2764 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2765 .addOperand(Dest).addOperand(Src),
2766 MI->getOperand(2).getImm());
2767 break;
2768 case X86::ADD32ri:
2769 case X86::ADD32ri8:
2770 case X86::ADD32ri_DB:
2771 case X86::ADD32ri8_DB: {
2772 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2773 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2774
2775 bool isKill, isUndef;
2776 unsigned SrcReg;
2777 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2778 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2779 SrcReg, isKill, isUndef, ImplicitOp))
2780 return nullptr;
2781
2782 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2783 .addOperand(Dest)
2784 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2785 if (ImplicitOp.getReg() != 0)
2786 MIB.addOperand(ImplicitOp);
2787
2788 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2789 break;
2790 }
2791 case X86::ADD16ri:
2792 case X86::ADD16ri8:
2793 case X86::ADD16ri_DB:
2794 case X86::ADD16ri8_DB:
2795 if (DisableLEA16)
2796 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2797 : nullptr;
2798 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2799 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2800 .addOperand(Dest).addOperand(Src),
2801 MI->getOperand(2).getImm());
2802 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2803 }
2804
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2805 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]2806
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2807 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2808 if (Src.isKill())
2809 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2810 if (Dest.isDead())
2811 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2812 }
2813
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2814 MFI->insert(MBBI, NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]2815 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2816}
2817
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2818/// commuteInstruction - We have a few instructions that must be hacked on to
2819/// commute them.
2820///
Evan Cheng03553bb2008-06-16 07:33:11 +0000[diff] [blame]2821MachineInstr *
2822X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2823 switch (MI->getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2824 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2825 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2826 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2827 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2828 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2829 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2830 unsigned Opc;
2831 unsigned Size;
2832 switch (MI->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2833 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2834 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2835 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2836 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2837 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2838 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2839 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2840 }
Chris Lattner5c463782007-12-30 20:49:49 +0000[diff] [blame]2841 unsigned Amt = MI->getOperand(3).getImm();
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2842 if (NewMI) {
2843 MachineFunction &MF = *MI->getParent()->getParent();
2844 MI = MF.CloneMachineInstr(MI);
2845 NewMI = false;
Evan Cheng244183e2008-02-13 02:46:49 +0000[diff] [blame]2846 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2847 MI->setDesc(get(Opc));
2848 MI->getOperand(3).setImm(Size-Amt);
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2849 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2850 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2851 case X86::BLENDPDrri:
2852 case X86::BLENDPSrri:
2853 case X86::PBLENDWrri:
2854 case X86::VBLENDPDrri:
2855 case X86::VBLENDPSrri:
2856 case X86::VBLENDPDYrri:
2857 case X86::VBLENDPSYrri:
2858 case X86::VPBLENDDrri:
2859 case X86::VPBLENDWrri:
2860 case X86::VPBLENDDYrri:
2861 case X86::VPBLENDWYrri:{
2862 unsigned Mask;
2863 switch (MI->getOpcode()) {
2864 default: llvm_unreachable("Unreachable!");
2865 case X86::BLENDPDrri: Mask = 0x03; break;
2866 case X86::BLENDPSrri: Mask = 0x0F; break;
2867 case X86::PBLENDWrri: Mask = 0xFF; break;
2868 case X86::VBLENDPDrri: Mask = 0x03; break;
2869 case X86::VBLENDPSrri: Mask = 0x0F; break;
2870 case X86::VBLENDPDYrri: Mask = 0x0F; break;
2871 case X86::VBLENDPSYrri: Mask = 0xFF; break;
2872 case X86::VPBLENDDrri: Mask = 0x0F; break;
2873 case X86::VPBLENDWrri: Mask = 0xFF; break;
2874 case X86::VPBLENDDYrri: Mask = 0xFF; break;
2875 case X86::VPBLENDWYrri: Mask = 0xFF; break;
2876 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]2877 // Only the least significant bits of Imm are used.
2878 unsigned Imm = MI->getOperand(3).getImm() & Mask;
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2879 if (NewMI) {
2880 MachineFunction &MF = *MI->getParent()->getParent();
2881 MI = MF.CloneMachineInstr(MI);
2882 NewMI = false;
2883 }
2884 MI->getOperand(3).setImm(Mask ^ Imm);
2885 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2886 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]2887 case X86::PCLMULQDQrr:
2888 case X86::VPCLMULQDQrr:{
2889 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2890 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2891 unsigned Imm = MI->getOperand(3).getImm();
2892 unsigned Src1Hi = Imm & 0x01;
2893 unsigned Src2Hi = Imm & 0x10;
2894 if (NewMI) {
2895 MachineFunction &MF = *MI->getParent()->getParent();
2896 MI = MF.CloneMachineInstr(MI);
2897 NewMI = false;
2898 }
2899 MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2900 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2901 }
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]2902 case X86::CMPPDrri:
2903 case X86::CMPPSrri:
2904 case X86::VCMPPDrri:
2905 case X86::VCMPPSrri:
2906 case X86::VCMPPDYrri:
2907 case X86::VCMPPSYrri: {
2908 // Float comparison can be safely commuted for
2909 // Ordered/Unordered/Equal/NotEqual tests
2910 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
2911 switch (Imm) {
2912 case 0x00: // EQUAL
2913 case 0x03: // UNORDERED
2914 case 0x04: // NOT EQUAL
2915 case 0x07: // ORDERED
2916 if (NewMI) {
2917 MachineFunction &MF = *MI->getParent()->getParent();
2918 MI = MF.CloneMachineInstr(MI);
2919 NewMI = false;
2920 }
2921 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2922 default:
2923 return nullptr;
2924 }
2925 }
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]2926 case X86::VPCOMBri: case X86::VPCOMUBri:
2927 case X86::VPCOMDri: case X86::VPCOMUDri:
2928 case X86::VPCOMQri: case X86::VPCOMUQri:
2929 case X86::VPCOMWri: case X86::VPCOMUWri: {
2930 // Flip comparison mode immediate (if necessary).
2931 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
2932 switch (Imm) {
2933 case 0x00: Imm = 0x02; break; // LT -> GT
2934 case 0x01: Imm = 0x03; break; // LE -> GE
2935 case 0x02: Imm = 0x00; break; // GT -> LT
2936 case 0x03: Imm = 0x01; break; // GE -> LE
2937 case 0x04: // EQ
2938 case 0x05: // NE
2939 case 0x06: // FALSE
2940 case 0x07: // TRUE
2941 default:
2942 break;
2943 }
2944 if (NewMI) {
2945 MachineFunction &MF = *MI->getParent()->getParent();
2946 MI = MF.CloneMachineInstr(MI);
2947 NewMI = false;
2948 }
2949 MI->getOperand(3).setImm(Imm);
2950 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2951 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2952 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
2953 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2954 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
2955 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2956 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2957 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
2958 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
2959 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2960 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2961 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
2962 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
2963 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2964 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
2965 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2966 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
2967 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2968 unsigned Opc;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2969 switch (MI->getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2970 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2971 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2972 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2973 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2974 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2975 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2976 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2977 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2978 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2979 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2980 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2981 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2982 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]2983 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2984 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2985 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2986 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2987 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2988 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2989 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2990 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2991 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2992 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2993 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2994 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2995 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2996 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2997 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2998 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2999 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3000 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3001 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3002 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3003 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3004 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3005 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3006 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3007 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3008 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3009 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3010 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3011 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3012 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3013 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3014 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3015 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3016 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3017 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3018 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3019 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]3020 if (NewMI) {
3021 MachineFunction &MF = *MI->getParent()->getParent();
3022 MI = MF.CloneMachineInstr(MI);
3023 NewMI = false;
3024 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]3025 MI->setDesc(get(Opc));
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3026 // Fallthrough intended.
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3027 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3028 default:
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]3029 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3030 }
3031}
3032
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3033bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
3034 unsigned &SrcOpIdx2) const {
3035 switch (MI->getOpcode()) {
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3036 case X86::CMPPDrri:
3037 case X86::CMPPSrri:
3038 case X86::VCMPPDrri:
3039 case X86::VCMPPSrri:
3040 case X86::VCMPPDYrri:
3041 case X86::VCMPPSYrri: {
3042 // Float comparison can be safely commuted for
3043 // Ordered/Unordered/Equal/NotEqual tests
3044 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3045 switch (Imm) {
3046 case 0x00: // EQUAL
3047 case 0x03: // UNORDERED
3048 case 0x04: // NOT EQUAL
3049 case 0x07: // ORDERED
3050 SrcOpIdx1 = 1;
3051 SrcOpIdx2 = 2;
3052 return true;
3053 }
3054 return false;
3055 }
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3056 case X86::VFMADDPDr231r:
3057 case X86::VFMADDPSr231r:
3058 case X86::VFMADDSDr231r:
3059 case X86::VFMADDSSr231r:
3060 case X86::VFMSUBPDr231r:
3061 case X86::VFMSUBPSr231r:
3062 case X86::VFMSUBSDr231r:
3063 case X86::VFMSUBSSr231r:
3064 case X86::VFNMADDPDr231r:
3065 case X86::VFNMADDPSr231r:
3066 case X86::VFNMADDSDr231r:
3067 case X86::VFNMADDSSr231r:
3068 case X86::VFNMSUBPDr231r:
3069 case X86::VFNMSUBPSr231r:
3070 case X86::VFNMSUBSDr231r:
3071 case X86::VFNMSUBSSr231r:
3072 case X86::VFMADDPDr231rY:
3073 case X86::VFMADDPSr231rY:
3074 case X86::VFMSUBPDr231rY:
3075 case X86::VFMSUBPSr231rY:
3076 case X86::VFNMADDPDr231rY:
3077 case X86::VFNMADDPSr231rY:
3078 case X86::VFNMSUBPDr231rY:
3079 case X86::VFNMSUBPSr231rY:
3080 SrcOpIdx1 = 2;
3081 SrcOpIdx2 = 3;
3082 return true;
3083 default:
3084 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3085 }
3086}
3087
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3088static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3089 switch (BrOpc) {
3090 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3091 case X86::JE_1: return X86::COND_E;
3092 case X86::JNE_1: return X86::COND_NE;
3093 case X86::JL_1: return X86::COND_L;
3094 case X86::JLE_1: return X86::COND_LE;
3095 case X86::JG_1: return X86::COND_G;
3096 case X86::JGE_1: return X86::COND_GE;
3097 case X86::JB_1: return X86::COND_B;
3098 case X86::JBE_1: return X86::COND_BE;
3099 case X86::JA_1: return X86::COND_A;
3100 case X86::JAE_1: return X86::COND_AE;
3101 case X86::JS_1: return X86::COND_S;
3102 case X86::JNS_1: return X86::COND_NS;
3103 case X86::JP_1: return X86::COND_P;
3104 case X86::JNP_1: return X86::COND_NP;
3105 case X86::JO_1: return X86::COND_O;
3106 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3107 }
3108}
3109
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3110/// getCondFromSETOpc - return condition code of a SET opcode.
3111static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3112 switch (Opc) {
3113 default: return X86::COND_INVALID;
3114 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3115 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3116 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3117 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3118 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3119 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3120 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3121 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3122 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3123 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3124 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3125 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3126 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3127 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3128 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3129 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3130 }
3131}
3132
3133/// getCondFromCmovOpc - return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3134X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3135 switch (Opc) {
3136 default: return X86::COND_INVALID;
3137 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3138 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3139 return X86::COND_A;
3140 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3141 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3142 return X86::COND_AE;
3143 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3144 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3145 return X86::COND_B;
3146 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3147 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3148 return X86::COND_BE;
3149 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3150 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3151 return X86::COND_E;
3152 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3153 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3154 return X86::COND_G;
3155 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3156 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3157 return X86::COND_GE;
3158 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3159 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3160 return X86::COND_L;
3161 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3162 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3163 return X86::COND_LE;
3164 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3165 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3166 return X86::COND_NE;
3167 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3168 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3169 return X86::COND_NO;
3170 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3171 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3172 return X86::COND_NP;
3173 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3174 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3175 return X86::COND_NS;
3176 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3177 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3178 return X86::COND_O;
3179 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3180 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3181 return X86::COND_P;
3182 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3183 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3184 return X86::COND_S;
3185 }
3186}
3187
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3188unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3189 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3190 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3191 case X86::COND_E: return X86::JE_1;
3192 case X86::COND_NE: return X86::JNE_1;
3193 case X86::COND_L: return X86::JL_1;
3194 case X86::COND_LE: return X86::JLE_1;
3195 case X86::COND_G: return X86::JG_1;
3196 case X86::COND_GE: return X86::JGE_1;
3197 case X86::COND_B: return X86::JB_1;
3198 case X86::COND_BE: return X86::JBE_1;
3199 case X86::COND_A: return X86::JA_1;
3200 case X86::COND_AE: return X86::JAE_1;
3201 case X86::COND_S: return X86::JS_1;
3202 case X86::COND_NS: return X86::JNS_1;
3203 case X86::COND_P: return X86::JP_1;
3204 case X86::COND_NP: return X86::JNP_1;
3205 case X86::COND_O: return X86::JO_1;
3206 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3207 }
3208}
3209
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3210/// GetOppositeBranchCondition - Return the inverse of the specified condition,
3211/// e.g. turning COND_E to COND_NE.
3212X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3213 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3214 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3215 case X86::COND_E: return X86::COND_NE;
3216 case X86::COND_NE: return X86::COND_E;
3217 case X86::COND_L: return X86::COND_GE;
3218 case X86::COND_LE: return X86::COND_G;
3219 case X86::COND_G: return X86::COND_LE;
3220 case X86::COND_GE: return X86::COND_L;
3221 case X86::COND_B: return X86::COND_AE;
3222 case X86::COND_BE: return X86::COND_A;
3223 case X86::COND_A: return X86::COND_BE;
3224 case X86::COND_AE: return X86::COND_B;
3225 case X86::COND_S: return X86::COND_NS;
3226 case X86::COND_NS: return X86::COND_S;
3227 case X86::COND_P: return X86::COND_NP;
3228 case X86::COND_NP: return X86::COND_P;
3229 case X86::COND_O: return X86::COND_NO;
3230 case X86::COND_NO: return X86::COND_O;
3231 }
3232}
3233
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3234/// getSwappedCondition - assume the flags are set by MI(a,b), return
3235/// the condition code if we modify the instructions such that flags are
3236/// set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]3237static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3238 switch (CC) {
3239 default: return X86::COND_INVALID;
3240 case X86::COND_E: return X86::COND_E;
3241 case X86::COND_NE: return X86::COND_NE;
3242 case X86::COND_L: return X86::COND_G;
3243 case X86::COND_LE: return X86::COND_GE;
3244 case X86::COND_G: return X86::COND_L;
3245 case X86::COND_GE: return X86::COND_LE;
3246 case X86::COND_B: return X86::COND_A;
3247 case X86::COND_BE: return X86::COND_AE;
3248 case X86::COND_A: return X86::COND_B;
3249 case X86::COND_AE: return X86::COND_BE;
3250 }
3251}
3252
3253/// getSETFromCond - Return a set opcode for the given condition and
3254/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3255unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3256 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3257 { X86::SETAr, X86::SETAm },
3258 { X86::SETAEr, X86::SETAEm },
3259 { X86::SETBr, X86::SETBm },
3260 { X86::SETBEr, X86::SETBEm },
3261 { X86::SETEr, X86::SETEm },
3262 { X86::SETGr, X86::SETGm },
3263 { X86::SETGEr, X86::SETGEm },
3264 { X86::SETLr, X86::SETLm },
3265 { X86::SETLEr, X86::SETLEm },
3266 { X86::SETNEr, X86::SETNEm },
3267 { X86::SETNOr, X86::SETNOm },
3268 { X86::SETNPr, X86::SETNPm },
3269 { X86::SETNSr, X86::SETNSm },
3270 { X86::SETOr, X86::SETOm },
3271 { X86::SETPr, X86::SETPm },
3272 { X86::SETSr, X86::SETSm }
3273 };
3274
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3275 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3276 return Opc[CC][HasMemoryOperand ? 1 : 0];
3277}
3278
3279/// getCMovFromCond - Return a cmov opcode for the given condition,
3280/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]3281unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3282 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3283 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3284 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3285 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3286 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3287 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3288 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3289 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3290 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3291 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3292 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3293 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3294 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3295 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3296 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3297 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3298 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3299 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3300 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3301 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3302 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3303 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3304 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3305 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3306 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3307 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3308 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3309 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3310 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3311 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3312 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3313 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3314 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3315 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3316 };
3317
3318 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3319 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3320 switch(RegBytes) {
3321 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3322 case 2: return Opc[Idx][0];
3323 case 4: return Opc[Idx][1];
3324 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3325 }
3326}
3327
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3328bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3329 if (!MI->isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3330
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3331 // Conditional branch is a special case.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3332 if (MI->isBranch() && !MI->isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3333 return true;
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3334 if (!MI->isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3335 return true;
3336 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3337}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3338
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3339bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3340 MachineBasicBlock *&TBB,
3341 MachineBasicBlock *&FBB,
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3342 SmallVectorImpl<MachineOperand> &Cond,
3343 bool AllowModify) const {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3344 // Start from the bottom of the block and work up, examining the
3345 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3346 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3347 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3348 while (I != MBB.begin()) {
3349 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3350 if (I->isDebugValue())
3351 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3352
3353 // Working from the bottom, when we see a non-terminator instruction, we're
3354 // done.
Jakob Stoklund Olesenc30b4dd2010-07-16 17:41:44 +0000[diff] [blame]3355 if (!isUnpredicatedTerminator(I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3356 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3357
3358 // A terminator that isn't a branch can't easily be handled by this
3359 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3360 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3361 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3362
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3363 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3364 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3365 UnCondBrIter = I;
3366
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3367 if (!AllowModify) {
3368 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]3369 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3370 }
3371
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3372 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3373 while (std::next(I) != MBB.end())
3374 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3375
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3376 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3377 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3378
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3379 // Delete the JMP if it's equivalent to a fall-through.
3380 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3381 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3382 I->eraseFromParent();
3383 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3384 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3385 continue;
3386 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3387
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3388 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3389 TBB = I->getOperand(0).getMBB();
3390 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3391 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3392
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3393 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3394 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3395 if (BranchCode == X86::COND_INVALID)
3396 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3397
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3398 // Working from the bottom, handle the first conditional branch.
3399 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3400 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3401 if (AllowModify && UnCondBrIter != MBB.end() &&
3402 MBB.isLayoutSuccessor(TargetBB)) {
3403 // If we can modify the code and it ends in something like:
3404 //
3405 // jCC L1
3406 // jmp L2
3407 // L1:
3408 // ...
3409 // L2:
3410 //
3411 // Then we can change this to:
3412 //
3413 // jnCC L2
3414 // L1:
3415 // ...
3416 // L2:
3417 //
3418 // Which is a bit more efficient.
3419 // We conditionally jump to the fall-through block.
3420 BranchCode = GetOppositeBranchCondition(BranchCode);
3421 unsigned JNCC = GetCondBranchFromCond(BranchCode);
3422 MachineBasicBlock::iterator OldInst = I;
3423
3424 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3425 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3426 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3427 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3428
3429 OldInst->eraseFromParent();
3430 UnCondBrIter->eraseFromParent();
3431
3432 // Restart the analysis.
3433 UnCondBrIter = MBB.end();
3434 I = MBB.end();
3435 continue;
3436 }
3437
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3438 FBB = TBB;
3439 TBB = I->getOperand(0).getMBB();
3440 Cond.push_back(MachineOperand::CreateImm(BranchCode));
3441 continue;
3442 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3443
3444 // Handle subsequent conditional branches. Only handle the case where all
3445 // conditional branches branch to the same destination and their condition
3446 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3447 assert(Cond.size() == 1);
3448 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3449
3450 // Only handle the case where all conditional branches branch to the same
3451 // destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3452 if (TBB != I->getOperand(0).getMBB())
3453 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3454
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3455 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3456 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3457 if (OldBranchCode == BranchCode)
3458 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3459
3460 // If they differ, see if they fit one of the known patterns. Theoretically,
3461 // we could handle more patterns here, but we shouldn't expect to see them
3462 // if instruction selection has done a reasonable job.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3463 if ((OldBranchCode == X86::COND_NP &&
3464 BranchCode == X86::COND_E) ||
3465 (OldBranchCode == X86::COND_E &&
3466 BranchCode == X86::COND_NP))
3467 BranchCode = X86::COND_NP_OR_E;
3468 else if ((OldBranchCode == X86::COND_P &&
3469 BranchCode == X86::COND_NE) ||
3470 (OldBranchCode == X86::COND_NE &&
3471 BranchCode == X86::COND_P))
3472 BranchCode = X86::COND_NE_OR_P;
3473 else
3474 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3475
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3476 // Update the MachineOperand.
3477 Cond[0].setImm(BranchCode);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]3478 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3479
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3480 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3481}
3482
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3483unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3484 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3485 unsigned Count = 0;
3486
3487 while (I != MBB.begin()) {
3488 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3489 if (I->isDebugValue())
3490 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3491 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3492 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3493 break;
3494 // Remove the branch.
3495 I->eraseFromParent();
3496 I = MBB.end();
3497 ++Count;
3498 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3499
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3500 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3501}
3502
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3503unsigned
3504X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3505 MachineBasicBlock *FBB,
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3506 const SmallVectorImpl<MachineOperand> &Cond,
3507 DebugLoc DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3508 // Shouldn't be a fall through.
3509 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]3510 assert((Cond.size() == 1 || Cond.size() == 0) &&
3511 "X86 branch conditions have one component!");
3512
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3513 if (Cond.empty()) {
3514 // Unconditional branch?
3515 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3516 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3517 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3518 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3519
3520 // Conditional branch.
3521 unsigned Count = 0;
3522 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3523 switch (CC) {
3524 case X86::COND_NP_OR_E:
3525 // Synthesize NP_OR_E with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3526 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3527 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3528 BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3529 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3530 break;
3531 case X86::COND_NE_OR_P:
3532 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3533 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3534 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3535 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3536 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3537 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3538 default: {
3539 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3540 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3541 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3542 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3543 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3544 if (FBB) {
3545 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3546 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3547 ++Count;
3548 }
3549 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3550}
3551
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3552bool X86InstrInfo::
3553canInsertSelect(const MachineBasicBlock &MBB,
3554 const SmallVectorImpl<MachineOperand> &Cond,
3555 unsigned TrueReg, unsigned FalseReg,
3556 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3557 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3558 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3559 return false;
3560 if (Cond.size() != 1)
3561 return false;
3562 // We cannot do the composite conditions, at least not in SSA form.
3563 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3564 return false;
3565
3566 // Check register classes.
3567 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3568 const TargetRegisterClass *RC =
3569 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3570 if (!RC)
3571 return false;
3572
3573 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3574 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3575 X86::GR32RegClass.hasSubClassEq(RC) ||
3576 X86::GR64RegClass.hasSubClassEq(RC)) {
3577 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3578 // Bridge. Probably Ivy Bridge as well.
3579 CondCycles = 2;
3580 TrueCycles = 2;
3581 FalseCycles = 2;
3582 return true;
3583 }
3584
3585 // Can't do vectors.
3586 return false;
3587}
3588
3589void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3590 MachineBasicBlock::iterator I, DebugLoc DL,
3591 unsigned DstReg,
3592 const SmallVectorImpl<MachineOperand> &Cond,
3593 unsigned TrueReg, unsigned FalseReg) const {
3594 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3595 assert(Cond.size() == 1 && "Invalid Cond array");
3596 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3597 MRI.getRegClass(DstReg)->getSize(),
3598 false/*HasMemoryOperand*/);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3599 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3600}
3601
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3602/// isHReg - Test if the given register is a physical h register.
3603static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3604 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3605}
3606
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3607// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3608static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3609 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3610
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3611 // SrcReg(VR128) -> DestReg(GR64)
3612 // SrcReg(VR64) -> DestReg(GR64)
3613 // SrcReg(GR64) -> DestReg(VR128)
3614 // SrcReg(GR64) -> DestReg(VR64)
3615
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3616 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3617 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3618 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3619 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3620 // Copy from a VR128 register to a GR64 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3621 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3622 X86::MOVPQIto64rr);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3623 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3624 // Copy from a VR64 register to a GR64 register.
3625 return X86::MOVSDto64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3626 } else if (X86::GR64RegClass.contains(SrcReg)) {
3627 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3628 if (X86::VR128XRegClass.contains(DestReg))
3629 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3630 X86::MOV64toPQIrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3631 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3632 if (X86::VR64RegClass.contains(DestReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3633 return X86::MOV64toSDrr;
3634 }
3635
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3636 // SrcReg(FR32) -> DestReg(GR32)
3637 // SrcReg(GR32) -> DestReg(FR32)
3638
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3639 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3640 // Copy from a FR32 register to a GR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3641 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3642
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3643 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3644 // Copy from a GR32 register to a FR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3645 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3646 return 0;
3647}
3648
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3649inline static bool MaskRegClassContains(unsigned Reg) {
3650 return X86::VK8RegClass.contains(Reg) ||
3651 X86::VK16RegClass.contains(Reg) ||
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]3652 X86::VK32RegClass.contains(Reg) ||
3653 X86::VK64RegClass.contains(Reg) ||
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3654 X86::VK1RegClass.contains(Reg);
3655}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3656static
3657unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3658 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3659 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3660 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3661 DestReg = get512BitSuperRegister(DestReg);
3662 SrcReg = get512BitSuperRegister(SrcReg);
3663 return X86::VMOVAPSZrr;
3664 }
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3665 if (MaskRegClassContains(DestReg) &&
3666 MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3667 return X86::KMOVWkk;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3668 if (MaskRegClassContains(DestReg) &&
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3669 (X86::GR32RegClass.contains(SrcReg) ||
3670 X86::GR16RegClass.contains(SrcReg) ||
3671 X86::GR8RegClass.contains(SrcReg))) {
3672 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3673 return X86::KMOVWkr;
3674 }
3675 if ((X86::GR32RegClass.contains(DestReg) ||
3676 X86::GR16RegClass.contains(DestReg) ||
3677 X86::GR8RegClass.contains(DestReg)) &&
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3678 MaskRegClassContains(SrcReg)) {
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3679 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3680 return X86::KMOVWrk;
3681 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3682 return 0;
3683}
3684
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3685void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3686 MachineBasicBlock::iterator MI, DebugLoc DL,
3687 unsigned DestReg, unsigned SrcReg,
3688 bool KillSrc) const {
3689 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3690 bool HasAVX = Subtarget.hasAVX();
3691 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3692 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3693 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3694 Opc = X86::MOV64rr;
3695 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3696 Opc = X86::MOV32rr;
3697 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3698 Opc = X86::MOV16rr;
3699 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3700 // Copying to or from a physical H register on x86-64 requires a NOREX
3701 // move. Otherwise use a normal move.
3702 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3703 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3704 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]3705 // Both operands must be encodable without an REX prefix.
3706 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3707 "8-bit H register can not be copied outside GR8_NOREX");
3708 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3709 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3710 }
3711 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3712 Opc = X86::MMX_MOVQ64rr;
3713 else if (HasAVX512)
3714 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3715 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3716 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3717 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3718 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3719 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3720 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3721
3722 if (Opc) {
3723 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3724 .addReg(SrcReg, getKillRegState(KillSrc));
3725 return;
3726 }
3727
3728 // Moving EFLAGS to / from another register requires a push and a pop.
Nadav Rotemd5aae982012-12-21 23:48:49 +0000[diff] [blame]3729 // Notice that we have to adjust the stack if we don't want to clobber the
JF Bastienac8b66b2014-08-05 23:27:34 +0000[diff] [blame]3730 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3731 if (SrcReg == X86::EFLAGS) {
3732 if (X86::GR64RegClass.contains(DestReg)) {
3733 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3734 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3735 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3736 }
3737 if (X86::GR32RegClass.contains(DestReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3738 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3739 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3740 return;
3741 }
3742 }
3743 if (DestReg == X86::EFLAGS) {
3744 if (X86::GR64RegClass.contains(SrcReg)) {
3745 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3746 .addReg(SrcReg, getKillRegState(KillSrc));
3747 BuildMI(MBB, MI, DL, get(X86::POPF64));
3748 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3749 }
3750 if (X86::GR32RegClass.contains(SrcReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3751 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3752 .addReg(SrcReg, getKillRegState(KillSrc));
3753 BuildMI(MBB, MI, DL, get(X86::POPF32));
3754 return;
3755 }
3756 }
3757
3758 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3759 << " to " << RI.getName(DestReg) << '\n');
3760 llvm_unreachable("Cannot emit physreg copy instruction");
3761}
3762
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3763static unsigned getLoadStoreRegOpcode(unsigned Reg,
3764 const TargetRegisterClass *RC,
3765 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3766 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3767 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3768 if (STI.hasAVX512()) {
Andrew Trick8460a3b2013-10-14 22:18:56 +0000[diff] [blame]3769 if (X86::VK8RegClass.hasSubClassEq(RC) ||
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3770 X86::VK16RegClass.hasSubClassEq(RC))
3771 return load ? X86::KMOVWkm : X86::KMOVWmk;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3772 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3773 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3774 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3775 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3776 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3777 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3778 }
3779
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3780 bool HasAVX = STI.hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3781 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]3782 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3783 llvm_unreachable("Unknown spill size");
3784 case 1:
3785 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3786 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3787 // Copying to or from a physical H register on x86-64 requires a NOREX
3788 // move. Otherwise use a normal move.
3789 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3790 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3791 return load ? X86::MOV8rm : X86::MOV8mr;
3792 case 2:
3793 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3794 return load ? X86::MOV16rm : X86::MOV16mr;
3795 case 4:
3796 if (X86::GR32RegClass.hasSubClassEq(RC))
3797 return load ? X86::MOV32rm : X86::MOV32mr;
3798 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3799 return load ?
3800 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3801 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3802 if (X86::RFP32RegClass.hasSubClassEq(RC))
3803 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3804 llvm_unreachable("Unknown 4-byte regclass");
3805 case 8:
3806 if (X86::GR64RegClass.hasSubClassEq(RC))
3807 return load ? X86::MOV64rm : X86::MOV64mr;
3808 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3809 return load ?
3810 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3811 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3812 if (X86::VR64RegClass.hasSubClassEq(RC))
3813 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3814 if (X86::RFP64RegClass.hasSubClassEq(RC))
3815 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3816 llvm_unreachable("Unknown 8-byte regclass");
3817 case 10:
3818 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3819 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3820 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3821 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3822 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3823 // If stack is realigned we can use aligned stores.
3824 if (isStackAligned)
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3825 return load ?
3826 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3827 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3828 else
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3829 return load ?
3830 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3831 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3832 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3833 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3834 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3835 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3836 // If stack is realigned we can use aligned stores.
3837 if (isStackAligned)
3838 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3839 else
3840 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3841 case 64:
3842 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3843 if (isStackAligned)
3844 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3845 else
3846 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3847 }
3848}
3849
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3850static unsigned getStoreRegOpcode(unsigned SrcReg,
3851 const TargetRegisterClass *RC,
3852 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3853 const X86Subtarget &STI) {
3854 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3855}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3856
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3857
3858static unsigned getLoadRegOpcode(unsigned DestReg,
3859 const TargetRegisterClass *RC,
3860 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3861 const X86Subtarget &STI) {
3862 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3863}
3864
3865void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3866 MachineBasicBlock::iterator MI,
3867 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]3868 const TargetRegisterClass *RC,
3869 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3870 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]3871 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3872 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3873 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]3874 bool isAligned =
3875 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3876 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3877 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3878 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3879 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3880 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3881}
3882
3883void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3884 bool isKill,
3885 SmallVectorImpl<MachineOperand> &Addr,
3886 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3887 MachineInstr::mmo_iterator MMOBegin,
3888 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3889 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3890 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3891 bool isAligned = MMOBegin != MMOEnd &&
3892 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3893 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3894 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3895 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3896 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3897 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3898 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3899 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3900 NewMIs.push_back(MIB);
3901}
3902
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3903
3904void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3905 MachineBasicBlock::iterator MI,
3906 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]3907 const TargetRegisterClass *RC,
3908 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3909 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3910 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]3911 bool isAligned =
3912 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3913 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3914 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3915 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3916 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3917}
3918
3919void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3920 SmallVectorImpl<MachineOperand> &Addr,
3921 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3922 MachineInstr::mmo_iterator MMOBegin,
3923 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3924 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3925 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3926 bool isAligned = MMOBegin != MMOEnd &&
3927 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3928 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3929 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3930 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3931 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3932 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3933 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3934 NewMIs.push_back(MIB);
3935}
3936
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3937bool X86InstrInfo::
3938analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3939 int &CmpMask, int &CmpValue) const {
3940 switch (MI->getOpcode()) {
3941 default: break;
3942 case X86::CMP64ri32:
3943 case X86::CMP64ri8:
3944 case X86::CMP32ri:
3945 case X86::CMP32ri8:
3946 case X86::CMP16ri:
3947 case X86::CMP16ri8:
3948 case X86::CMP8ri:
3949 SrcReg = MI->getOperand(0).getReg();
3950 SrcReg2 = 0;
3951 CmpMask = ~0;
3952 CmpValue = MI->getOperand(1).getImm();
3953 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3954 // A SUB can be used to perform comparison.
3955 case X86::SUB64rm:
3956 case X86::SUB32rm:
3957 case X86::SUB16rm:
3958 case X86::SUB8rm:
3959 SrcReg = MI->getOperand(1).getReg();
3960 SrcReg2 = 0;
3961 CmpMask = ~0;
3962 CmpValue = 0;
3963 return true;
3964 case X86::SUB64rr:
3965 case X86::SUB32rr:
3966 case X86::SUB16rr:
3967 case X86::SUB8rr:
3968 SrcReg = MI->getOperand(1).getReg();
3969 SrcReg2 = MI->getOperand(2).getReg();
3970 CmpMask = ~0;
3971 CmpValue = 0;
3972 return true;
3973 case X86::SUB64ri32:
3974 case X86::SUB64ri8:
3975 case X86::SUB32ri:
3976 case X86::SUB32ri8:
3977 case X86::SUB16ri:
3978 case X86::SUB16ri8:
3979 case X86::SUB8ri:
3980 SrcReg = MI->getOperand(1).getReg();
3981 SrcReg2 = 0;
3982 CmpMask = ~0;
3983 CmpValue = MI->getOperand(2).getImm();
3984 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3985 case X86::CMP64rr:
3986 case X86::CMP32rr:
3987 case X86::CMP16rr:
3988 case X86::CMP8rr:
3989 SrcReg = MI->getOperand(0).getReg();
3990 SrcReg2 = MI->getOperand(1).getReg();
3991 CmpMask = ~0;
3992 CmpValue = 0;
3993 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3994 case X86::TEST8rr:
3995 case X86::TEST16rr:
3996 case X86::TEST32rr:
3997 case X86::TEST64rr:
3998 SrcReg = MI->getOperand(0).getReg();
3999 if (MI->getOperand(1).getReg() != SrcReg) return false;
4000 // Compare against zero.
4001 SrcReg2 = 0;
4002 CmpMask = ~0;
4003 CmpValue = 0;
4004 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4005 }
4006 return false;
4007}
4008
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4009/// isRedundantFlagInstr - check whether the first instruction, whose only
4010/// purpose is to update flags, can be made redundant.
4011/// CMPrr can be made redundant by SUBrr if the operands are the same.
4012/// This function can be extended later on.
4013/// SrcReg, SrcRegs: register operands for FlagI.
4014/// ImmValue: immediate for FlagI if it takes an immediate.
4015inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4016 unsigned SrcReg2, int ImmValue,
4017 MachineInstr *OI) {
4018 if (((FlagI->getOpcode() == X86::CMP64rr &&
4019 OI->getOpcode() == X86::SUB64rr) ||
4020 (FlagI->getOpcode() == X86::CMP32rr &&
4021 OI->getOpcode() == X86::SUB32rr)||
4022 (FlagI->getOpcode() == X86::CMP16rr &&
4023 OI->getOpcode() == X86::SUB16rr)||
4024 (FlagI->getOpcode() == X86::CMP8rr &&
4025 OI->getOpcode() == X86::SUB8rr)) &&
4026 ((OI->getOperand(1).getReg() == SrcReg &&
4027 OI->getOperand(2).getReg() == SrcReg2) ||
4028 (OI->getOperand(1).getReg() == SrcReg2 &&
4029 OI->getOperand(2).getReg() == SrcReg)))
4030 return true;
4031
4032 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4033 OI->getOpcode() == X86::SUB64ri32) ||
4034 (FlagI->getOpcode() == X86::CMP64ri8 &&
4035 OI->getOpcode() == X86::SUB64ri8) ||
4036 (FlagI->getOpcode() == X86::CMP32ri &&
4037 OI->getOpcode() == X86::SUB32ri) ||
4038 (FlagI->getOpcode() == X86::CMP32ri8 &&
4039 OI->getOpcode() == X86::SUB32ri8) ||
4040 (FlagI->getOpcode() == X86::CMP16ri &&
4041 OI->getOpcode() == X86::SUB16ri) ||
4042 (FlagI->getOpcode() == X86::CMP16ri8 &&
4043 OI->getOpcode() == X86::SUB16ri8) ||
4044 (FlagI->getOpcode() == X86::CMP8ri &&
4045 OI->getOpcode() == X86::SUB8ri)) &&
4046 OI->getOperand(1).getReg() == SrcReg &&
4047 OI->getOperand(2).getImm() == ImmValue)
4048 return true;
4049 return false;
4050}
4051
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4052/// isDefConvertible - check whether the definition can be converted
4053/// to remove a comparison against zero.
4054inline static bool isDefConvertible(MachineInstr *MI) {
4055 switch (MI->getOpcode()) {
4056 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]4057
4058 // The shift instructions only modify ZF if their shift count is non-zero.
4059 // N.B.: The processor truncates the shift count depending on the encoding.
4060 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4061 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4062 return getTruncatedShiftCount(MI, 2) != 0;
4063
4064 // Some left shift instructions can be turned into LEA instructions but only
4065 // if their flags aren't used. Avoid transforming such instructions.
4066 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4067 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4068 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4069 return ShAmt != 0;
4070 }
4071
4072 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4073 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4074 return getTruncatedShiftCount(MI, 3) != 0;
4075
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4076 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4077 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4078 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4079 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4080 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4081 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4082 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4083 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4084 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4085 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4086 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4087 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4088 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4089 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4090 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4091 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4092 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4093 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4094 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4095 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4096 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4097 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4098 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4099 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4100 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4101 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4102 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4103 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4104 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4105 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4106 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4107 case X86::ADC32ri: case X86::ADC32ri8:
4108 case X86::ADC32rr: case X86::ADC64ri32:
4109 case X86::ADC64ri8: case X86::ADC64rr:
4110 case X86::SBB32ri: case X86::SBB32ri8:
4111 case X86::SBB32rr: case X86::SBB64ri32:
4112 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]4113 case X86::ANDN32rr: case X86::ANDN32rm:
4114 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4115 case X86::BEXTR32rr: case X86::BEXTR64rr:
4116 case X86::BEXTR32rm: case X86::BEXTR64rm:
4117 case X86::BLSI32rr: case X86::BLSI32rm:
4118 case X86::BLSI64rr: case X86::BLSI64rm:
4119 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4120 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4121 case X86::BLSR32rr: case X86::BLSR32rm:
4122 case X86::BLSR64rr: case X86::BLSR64rm:
4123 case X86::BZHI32rr: case X86::BZHI32rm:
4124 case X86::BZHI64rr: case X86::BZHI64rm:
4125 case X86::LZCNT16rr: case X86::LZCNT16rm:
4126 case X86::LZCNT32rr: case X86::LZCNT32rm:
4127 case X86::LZCNT64rr: case X86::LZCNT64rm:
4128 case X86::POPCNT16rr:case X86::POPCNT16rm:
4129 case X86::POPCNT32rr:case X86::POPCNT32rm:
4130 case X86::POPCNT64rr:case X86::POPCNT64rm:
4131 case X86::TZCNT16rr: case X86::TZCNT16rm:
4132 case X86::TZCNT32rr: case X86::TZCNT32rm:
4133 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4134 return true;
4135 }
4136}
4137
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4138/// isUseDefConvertible - check whether the use can be converted
4139/// to remove a comparison against zero.
4140static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4141 switch (MI->getOpcode()) {
4142 default: return X86::COND_INVALID;
4143 case X86::LZCNT16rr: case X86::LZCNT16rm:
4144 case X86::LZCNT32rr: case X86::LZCNT32rm:
4145 case X86::LZCNT64rr: case X86::LZCNT64rm:
4146 return X86::COND_B;
4147 case X86::POPCNT16rr:case X86::POPCNT16rm:
4148 case X86::POPCNT32rr:case X86::POPCNT32rm:
4149 case X86::POPCNT64rr:case X86::POPCNT64rm:
4150 return X86::COND_E;
4151 case X86::TZCNT16rr: case X86::TZCNT16rm:
4152 case X86::TZCNT32rr: case X86::TZCNT32rm:
4153 case X86::TZCNT64rr: case X86::TZCNT64rm:
4154 return X86::COND_B;
4155 }
4156}
4157
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4158/// optimizeCompareInstr - Check if there exists an earlier instruction that
4159/// operates on the same source operands and sets flags in the same way as
4160/// Compare; remove Compare if possible.
4161bool X86InstrInfo::
4162optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4163 int CmpMask, int CmpValue,
4164 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4165 // Check whether we can replace SUB with CMP.
4166 unsigned NewOpcode = 0;
4167 switch (CmpInstr->getOpcode()) {
4168 default: break;
4169 case X86::SUB64ri32:
4170 case X86::SUB64ri8:
4171 case X86::SUB32ri:
4172 case X86::SUB32ri8:
4173 case X86::SUB16ri:
4174 case X86::SUB16ri8:
4175 case X86::SUB8ri:
4176 case X86::SUB64rm:
4177 case X86::SUB32rm:
4178 case X86::SUB16rm:
4179 case X86::SUB8rm:
4180 case X86::SUB64rr:
4181 case X86::SUB32rr:
4182 case X86::SUB16rr:
4183 case X86::SUB8rr: {
4184 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
4185 return false;
4186 // There is no use of the destination register, we can replace SUB with CMP.
4187 switch (CmpInstr->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]4188 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4189 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
4190 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
4191 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
4192 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
4193 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
4194 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
4195 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
4196 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
4197 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4198 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
4199 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
4200 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
4201 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
4202 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
4203 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
4204 }
4205 CmpInstr->setDesc(get(NewOpcode));
4206 CmpInstr->RemoveOperand(0);
4207 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4208 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4209 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4210 return false;
4211 }
4212 }
4213
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4214 // Get the unique definition of SrcReg.
4215 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4216 if (!MI) return false;
4217
4218 // CmpInstr is the first instruction of the BB.
4219 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4220
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4221 // If we are comparing against zero, check whether we can use MI to update
4222 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4223 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4224 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4225 return false;
4226
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4227 // If we have a use of the source register between the def and our compare
4228 // instruction we can eliminate the compare iff the use sets EFLAGS in the
4229 // right way.
4230 bool ShouldUpdateCC = false;
4231 X86::CondCode NewCC = X86::COND_INVALID;
4232 if (IsCmpZero && !isDefConvertible(MI)) {
4233 // Scan forward from the use until we hit the use we're looking for or the
4234 // compare instruction.
4235 for (MachineBasicBlock::iterator J = MI;; ++J) {
4236 // Do we have a convertible instruction?
4237 NewCC = isUseDefConvertible(J);
4238 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4239 J->getOperand(1).getReg() == SrcReg) {
4240 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4241 ShouldUpdateCC = true; // Update CC later on.
4242 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4243 // with the new def.
4244 MI = Def = J;
4245 break;
4246 }
4247
4248 if (J == I)
4249 return false;
4250 }
4251 }
4252
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4253 // We are searching for an earlier instruction that can make CmpInstr
4254 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4255 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4256 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4257
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4258 // We iterate backward, starting from the instruction before CmpInstr and
4259 // stop when reaching the definition of a source register or done with the BB.
4260 // RI points to the instruction before CmpInstr.
4261 // If the definition is in this basic block, RE points to the definition;
4262 // otherwise, RE is the rend of the basic block.
4263 MachineBasicBlock::reverse_iterator
4264 RI = MachineBasicBlock::reverse_iterator(I),
4265 RE = CmpInstr->getParent() == MI->getParent() ?
4266 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
4267 CmpInstr->getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4268 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4269 for (; RI != RE; ++RI) {
4270 MachineInstr *Instr = &*RI;
4271 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4272 if (!IsCmpZero &&
4273 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4274 Sub = Instr;
4275 break;
4276 }
4277
4278 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4279 Instr->readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4280 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4281
4282 // MOV32r0 etc. are implemented with xor which clobbers condition code.
4283 // They are safe to move up, if the definition to EFLAGS is dead and
4284 // earlier instructions do not read or write EFLAGS.
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4285 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4286 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
4287 Movr0Inst = Instr;
4288 continue;
4289 }
4290
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4291 // We can't remove CmpInstr.
4292 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4293 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4294 }
4295
4296 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4297 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4298 return false;
4299
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4300 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
4301 Sub->getOperand(2).getReg() == SrcReg);
4302
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4303 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4304 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4305 // If we are done with the basic block, we need to check whether EFLAGS is
4306 // live-out.
4307 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4308 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
4309 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
4310 for (++I; I != E; ++I) {
4311 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4312 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4313 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4314 // We should check the usage if this instruction uses and updates EFLAGS.
4315 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4316 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4317 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4318 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4319 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4320 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4321 continue;
4322
4323 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]4324 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4325 bool OpcIsSET = false;
4326 if (IsCmpZero || IsSwapped) {
4327 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4328 if (Instr.isBranch())
4329 OldCC = getCondFromBranchOpc(Instr.getOpcode());
4330 else {
4331 OldCC = getCondFromSETOpc(Instr.getOpcode());
4332 if (OldCC != X86::COND_INVALID)
4333 OpcIsSET = true;
4334 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]4335 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4336 }
4337 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4338 }
4339 if (IsCmpZero) {
4340 switch (OldCC) {
4341 default: break;
4342 case X86::COND_A: case X86::COND_AE:
4343 case X86::COND_B: case X86::COND_BE:
4344 case X86::COND_G: case X86::COND_GE:
4345 case X86::COND_L: case X86::COND_LE:
4346 case X86::COND_O: case X86::COND_NO:
4347 // CF and OF are used, we can't perform this optimization.
4348 return false;
4349 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4350
4351 // If we're updating the condition code check if we have to reverse the
4352 // condition.
4353 if (ShouldUpdateCC)
4354 switch (OldCC) {
4355 default:
4356 return false;
4357 case X86::COND_E:
4358 break;
4359 case X86::COND_NE:
4360 NewCC = GetOppositeBranchCondition(NewCC);
4361 break;
4362 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4363 } else if (IsSwapped) {
4364 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4365 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4366 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4367 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4368 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4369 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4370
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4371 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4372 // Synthesize the new opcode.
4373 bool HasMemoryOperand = Instr.hasOneMemOperand();
4374 unsigned NewOpc;
4375 if (Instr.isBranch())
4376 NewOpc = GetCondBranchFromCond(NewCC);
4377 else if(OpcIsSET)
4378 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4379 else {
4380 unsigned DstReg = Instr.getOperand(0).getReg();
4381 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4382 HasMemoryOperand);
4383 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4384
4385 // Push the MachineInstr to OpsToUpdate.
4386 // If it is safe to remove CmpInstr, the condition code of these
4387 // instructions will be modified.
4388 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4389 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4390 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4391 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4392 IsSafe = true;
4393 break;
4394 }
4395 }
4396
4397 // If EFLAGS is not killed nor re-defined, we should check whether it is
4398 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4399 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4400 MachineBasicBlock *MBB = CmpInstr->getParent();
4401 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4402 SE = MBB->succ_end(); SI != SE; ++SI)
4403 if ((*SI)->isLiveIn(X86::EFLAGS))
4404 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4405 }
4406
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4407 // The instruction to be updated is either Sub or MI.
4408 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]4409 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4410 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]4411 // Look backwards until we find a def that doesn't use the current EFLAGS.
4412 Def = Sub;
4413 MachineBasicBlock::reverse_iterator
4414 InsertI = MachineBasicBlock::reverse_iterator(++Def),
4415 InsertE = Sub->getParent()->rend();
4416 for (; InsertI != InsertE; ++InsertI) {
4417 MachineInstr *Instr = &*InsertI;
4418 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4419 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4420 Sub->getParent()->remove(Movr0Inst);
4421 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4422 Movr0Inst);
4423 break;
4424 }
4425 }
4426 if (InsertI == InsertE)
4427 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4428 }
4429
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]4430 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4431 unsigned i = 0, e = Sub->getNumOperands();
4432 for (; i != e; ++i) {
4433 MachineOperand &MO = Sub->getOperand(i);
4434 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4435 MO.setIsDead(false);
4436 break;
4437 }
4438 }
4439 assert(i != e && "Unable to locate a def EFLAGS operand");
4440
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4441 CmpInstr->eraseFromParent();
4442
4443 // Modify the condition code of instructions in OpsToUpdate.
4444 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4445 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
4446 return true;
4447}
4448
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4449/// optimizeLoadInstr - Try to remove the load by folding it to a register
4450/// operand at the use. We fold the load instructions if load defines a virtual
4451/// register, the virtual register is used once in the same BB, and the
4452/// instructions in-between do not load or store, and have no side effects.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4453MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
4454 const MachineRegisterInfo *MRI,
4455 unsigned &FoldAsLoadDefReg,
4456 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4457 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4458 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4459 // To be conservative, if there exists another load, clear the load candidate.
4460 if (MI->mayLoad()) {
4461 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4462 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4463 }
4464
4465 // Check whether we can move DefMI here.
4466 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4467 assert(DefMI);
4468 bool SawStore = false;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4469 if (!DefMI->isSafeToMove(this, nullptr, SawStore))
4470 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4471
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4472 // Collect information about virtual register operands of MI.
4473 unsigned SrcOperandId = 0;
4474 bool FoundSrcOperand = false;
4475 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4476 MachineOperand &MO = MI->getOperand(i);
4477 if (!MO.isReg())
4478 continue;
4479 unsigned Reg = MO.getReg();
4480 if (Reg != FoldAsLoadDefReg)
4481 continue;
4482 // Do not fold if we have a subreg use or a def or multiple uses.
4483 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4484 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4485
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4486 SrcOperandId = i;
4487 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4488 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4489 if (!FoundSrcOperand)
4490 return nullptr;
4491
4492 // Check whether we can fold the def into SrcOperandId.
4493 SmallVector<unsigned, 8> Ops;
4494 Ops.push_back(SrcOperandId);
4495 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
4496 if (FoldMI) {
4497 FoldAsLoadDefReg = 0;
4498 return FoldMI;
4499 }
4500
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4501 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4502}
4503
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4504/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
4505/// instruction with two undef reads of the register being defined. This is
4506/// used for mapping:
4507/// %xmm4 = V_SET0
4508/// to:
4509/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4510///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4511static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4512 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4513 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4514 unsigned Reg = MIB->getOperand(0).getReg();
4515 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4516
4517 // MachineInstr::addOperand() will insert explicit operands before any
4518 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4519 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4520 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4521 assert(MIB->getOperand(1).getReg() == Reg &&
4522 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4523 return true;
4524}
4525
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4526// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4527// code sequence is needed for other targets.
4528static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4529 const TargetInstrInfo &TII) {
4530 MachineBasicBlock &MBB = *MIB->getParent();
4531 DebugLoc DL = MIB->getDebugLoc();
4532 unsigned Reg = MIB->getOperand(0).getReg();
4533 const GlobalValue *GV =
4534 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4535 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4536 MachineMemOperand *MMO = MBB.getParent()->
4537 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]4538 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4539
4540 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4541 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4542 .addMemOperand(MMO);
4543 MIB->setDebugLoc(DL);
4544 MIB->setDesc(TII.get(X86::MOV64rm));
4545 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4546}
4547
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4548bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4549 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4550 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4551 switch (MI->getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]4552 case X86::MOV32r0:
4553 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4554 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4555 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4556 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4557 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4558 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4559 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4560 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4561 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4562 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4563 case X86::FsFLD0SS:
4564 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4565 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4566 case X86::AVX_SET0:
4567 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4568 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4569 case X86::AVX512_512_SET0:
4570 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4571 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4572 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4573 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4574 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]4575 case X86::TEST8ri_NOREX:
4576 MI->setDesc(get(X86::TEST8ri));
4577 return true;
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]4578 case X86::KSET0B:
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4579 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4580 case X86::KSET1B:
4581 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4582 case TargetOpcode::LOAD_STACK_GUARD:
4583 expandLoadStackGuard(MIB, *this);
4584 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4585 }
4586 return false;
4587}
4588
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4589static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4590 const SmallVectorImpl<MachineOperand> &MOs,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4591 MachineInstr *MI,
4592 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4593 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4594 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4595 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4596 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4597 MachineInstrBuilder MIB(MF, NewMI);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4598 unsigned NumAddrOps = MOs.size();
4599 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4600 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4601 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4602 addOffset(MIB, 0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4603
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4604 // Loop over the rest of the ri operands, converting them over.
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4605 unsigned NumOps = MI->getDesc().getNumOperands()-2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4606 for (unsigned i = 0; i != NumOps; ++i) {
4607 MachineOperand &MO = MI->getOperand(i+2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4608 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4609 }
4610 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4611 MachineOperand &MO = MI->getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4612 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4613 }
4614 return MIB;
4615}
4616
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4617static MachineInstr *FuseInst(MachineFunction &MF,
4618 unsigned Opcode, unsigned OpNo,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4619 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4620 MachineInstr *MI, const TargetInstrInfo &TII) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4621 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4622 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4623 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4624 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4625
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4626 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4627 MachineOperand &MO = MI->getOperand(i);
4628 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4629 assert(MO.isReg() && "Expected to fold into reg operand!");
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4630 unsigned NumAddrOps = MOs.size();
4631 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4632 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4633 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4634 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4635 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4636 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4637 }
4638 }
4639 return MIB;
4640}
4641
4642static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4643 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4644 MachineInstr *MI) {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4645 MachineFunction &MF = *MI->getParent()->getParent();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4646 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4647
4648 unsigned NumAddrOps = MOs.size();
4649 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4650 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4651 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4652 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4653 return MIB.addImm(0);
4654}
4655
4656MachineInstr*
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4657X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4658 MachineInstr *MI, unsigned OpNum,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4659 const SmallVectorImpl<MachineOperand> &MOs,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4660 unsigned Size, unsigned Align,
4661 bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4662 const DenseMap<unsigned,
4663 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4664 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4665 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4666
Sanjay Patelfc54c612015-02-09 16:04:52 +0000[diff] [blame]4667 // For CPUs that favor the register form of a call,
4668 // do not fold loads into calls.
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4669 if (isCallRegIndirect &&
Sanjay Patelfc54c612015-02-09 16:04:52 +0000[diff] [blame]4670 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4671 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4672
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4673 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4674 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4675 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4676
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4677 // FIXME: AsmPrinter doesn't know how to handle
4678 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4679 if (MI->getOpcode() == X86::ADD32ri &&
4680 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4681 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4682
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4683 MachineInstr *NewMI = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4684 // Folding a memory location into the two-address part of a two-address
4685 // instruction is different than folding it other places. It requires
4686 // replacing the *two* registers with the memory location.
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4687 if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4688 MI->getOperand(0).isReg() &&
4689 MI->getOperand(1).isReg() &&
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4690 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4691 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4692 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4693 } else if (OpNum == 0) {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4694 if (MI->getOpcode() == X86::MOV32r0) {
4695 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4696 if (NewMI)
4697 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]4698 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4699
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4700 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4701 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4702 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4703 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4704 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4705 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]4706 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4707 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]4708 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4709 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4710
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4711 // If table selected...
4712 if (OpcodeTablePtr) {
4713 // Find the Opcode to fuse
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4714 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4715 OpcodeTablePtr->find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4716 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4717 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4718 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4719 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4720 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4721 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4722 if (Size) {
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4723 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4724 if (Size < RCSize) {
4725 // Check if it's safe to fold the load. If the size of the object is
4726 // narrower than the load width, then it's not.
4727 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4728 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4729 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4730 // a 32-bit load which is implicitly zero-extended. This likely is
4731 // due to live interval analysis remat'ing a load from stack slot.
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4732 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4733 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4734 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4735 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4736 }
4737 }
4738
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4739 if (isTwoAddrFold)
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4740 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4741 else
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4742 NewMI = FuseInst(MF, Opcode, OpNum, MOs, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4743
4744 if (NarrowToMOV32rm) {
4745 // If this is the special case where we use a MOV32rm to load a 32-bit
4746 // value and zero-extend the top bits. Change the destination register
4747 // to a 32-bit one.
4748 unsigned DstReg = NewMI->getOperand(0).getReg();
4749 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4750 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4751 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]4752 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4753 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4754 return NewMI;
4755 }
4756 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4757
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4758 // If the instruction and target operand are commutable, commute the
4759 // instruction and try again.
4760 if (AllowCommute) {
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4761 unsigned OriginalOpIdx = OpNum, CommuteOpIdx1, CommuteOpIdx2;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4762 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4763 bool HasDef = MI->getDesc().getNumDefs();
4764 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4765 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4766 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4767 bool Tied0 =
4768 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4769 bool Tied1 =
4770 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4771
4772 // If either of the commutable operands are tied to the destination
4773 // then we can not commute + fold.
4774 if ((HasDef && Reg0 == Reg1 && Tied0) ||
4775 (HasDef && Reg0 == Reg2 && Tied1))
4776 return nullptr;
4777
4778 if ((CommuteOpIdx1 == OriginalOpIdx) ||
4779 (CommuteOpIdx2 == OriginalOpIdx)) {
4780 MachineInstr *CommutedMI = commuteInstruction(MI, false);
4781 if (!CommutedMI) {
4782 // Unable to commute.
4783 return nullptr;
4784 }
4785 if (CommutedMI != MI) {
4786 // New instruction. We can't fold from this.
4787 CommutedMI->eraseFromParent();
4788 return nullptr;
4789 }
4790
4791 // Attempt to fold with the commuted version of the instruction.
4792 unsigned CommuteOp =
4793 (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4794 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align,
4795 /*AllowCommute=*/false);
4796 if (NewMI)
4797 return NewMI;
4798
4799 // Folding failed again - undo the commute before returning.
4800 MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4801 if (!UncommutedMI) {
4802 // Unable to commute.
4803 return nullptr;
4804 }
4805 if (UncommutedMI != MI) {
4806 // New instruction. It doesn't need to be kept.
4807 UncommutedMI->eraseFromParent();
4808 return nullptr;
4809 }
4810
4811 // Return here to prevent duplicate fuse failure report.
4812 return nullptr;
4813 }
4814 }
4815 }
4816
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4817 // No fusion
Jakob Stoklund Olesen51702ec2010-07-09 20:43:09 +0000[diff] [blame]4818 if (PrintFailedFusing && !MI->isCopy())
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4819 dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4820 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4821}
4822
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4823/// hasPartialRegUpdate - Return true for all instructions that only update
4824/// the first 32 or 64-bits of the destination register and leave the rest
4825/// unmodified. This can be used to avoid folding loads if the instructions
4826/// only update part of the destination register, and the non-updated part is
4827/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4828/// instructions breaks the partial register dependency and it can improve
4829/// performance. e.g.:
4830///
4831/// movss (%rdi), %xmm0
4832/// cvtss2sd %xmm0, %xmm0
4833///
4834/// Instead of
4835/// cvtss2sd (%rdi), %xmm0
4836///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]4837/// FIXME: This should be turned into a TSFlags.
4838///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4839static bool hasPartialRegUpdate(unsigned Opcode) {
4840 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4841 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4842 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4843 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4844 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4845 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4846 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4847 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4848 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4849 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4850 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4851 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4852 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4853 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4854 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4855 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4856 case X86::Int_CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4857 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4858 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4859 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4860 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4861 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4862 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]4863 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4864 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4865 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]4866 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4867 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4868 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4869 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4870 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4871 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4872 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4873 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4874 case X86::SQRTSSm_Int:
4875 case X86::SQRTSDr:
4876 case X86::SQRTSDm:
4877 case X86::SQRTSDr_Int:
4878 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4879 return true;
4880 }
4881
4882 return false;
4883}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4884
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4885/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4886/// instructions we would like before a partial register update.
4887unsigned X86InstrInfo::
4888getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4889 const TargetRegisterInfo *TRI) const {
4890 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4891 return 0;
4892
4893 // If MI is marked as reading Reg, the partial register update is wanted.
4894 const MachineOperand &MO = MI->getOperand(0);
4895 unsigned Reg = MO.getReg();
4896 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4897 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4898 return 0;
4899 } else {
4900 if (MI->readsRegister(Reg, TRI))
4901 return 0;
4902 }
4903
4904 // If any of the preceding 16 instructions are reading Reg, insert a
4905 // dependency breaking instruction. The magic number is based on a few
4906 // Nehalem experiments.
4907 return 16;
4908}
4909
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4910// Return true for any instruction the copies the high bits of the first source
4911// operand into the unused high bits of the destination operand.
4912static bool hasUndefRegUpdate(unsigned Opcode) {
4913 switch (Opcode) {
4914 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4915 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4916 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4917 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4918 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4919 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4920 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4921 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4922 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4923 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4924 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4925 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4926 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4927 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4928 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4929 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4930 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4931 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4932 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4933 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4934 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4935 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4936 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4937 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4938 case X86::VRCPSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4939 case X86::VRCPSSm:
4940 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4941 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4942 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4943 case X86::VROUNDSDr_Int:
4944 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4945 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4946 case X86::VROUNDSSr_Int:
4947 case X86::VRSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4948 case X86::VRSQRTSSm:
4949 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4950 case X86::VSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4951 case X86::VSQRTSSm:
4952 case X86::VSQRTSSm_Int:
4953 case X86::VSQRTSDr:
4954 case X86::VSQRTSDm:
4955 case X86::VSQRTSDm_Int:
4956 // AVX-512
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4957 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4958 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4959 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4960 case X86::VCVTSS2SDZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4961 return true;
4962 }
4963
4964 return false;
4965}
4966
4967/// Inform the ExeDepsFix pass how many idle instructions we would like before
4968/// certain undef register reads.
4969///
4970/// This catches the VCVTSI2SD family of instructions:
4971///
4972/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4973///
4974/// We should to be careful *not* to catch VXOR idioms which are presumably
4975/// handled specially in the pipeline:
4976///
4977/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4978///
4979/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4980/// high bits that are passed-through are not live.
4981unsigned X86InstrInfo::
4982getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4983 const TargetRegisterInfo *TRI) const {
4984 if (!hasUndefRegUpdate(MI->getOpcode()))
4985 return 0;
4986
4987 // Set the OpNum parameter to the first source operand.
4988 OpNum = 1;
4989
4990 const MachineOperand &MO = MI->getOperand(OpNum);
4991 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4992 // Use the same magic number as getPartialRegUpdateClearance.
4993 return 16;
4994 }
4995 return 0;
4996}
4997
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4998void X86InstrInfo::
4999breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
5000 const TargetRegisterInfo *TRI) const {
5001 unsigned Reg = MI->getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5002 // If MI kills this register, the false dependence is already broken.
5003 if (MI->killsRegister(Reg, TRI))
5004 return;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5005 if (X86::VR128RegClass.contains(Reg)) {
5006 // These instructions are all floating point domain, so xorps is the best
5007 // choice.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5008 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5009 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
5010 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
5011 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5012 } else if (X86::VR256RegClass.contains(Reg)) {
5013 // Use vxorps to clear the full ymm register.
5014 // It wants to read and write the xmm sub-register.
5015 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5016 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
5017 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
5018 .addReg(Reg, RegState::ImplicitDefine);
5019 } else
5020 return;
5021 MI->addRegisterKilled(Reg, TRI, true);
5022}
5023
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]5024MachineInstr*
5025X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
5026 const SmallVectorImpl<unsigned> &Ops,
5027 int FrameIndex) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5028 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5029 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5030
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5031 // Unless optimizing for size, don't fold to avoid partial
5032 // register update stalls
Duncan P. N. Exon Smith5975a702015-02-14 01:59:52 +0000[diff] [blame]5033 if (!MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5034 hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5035 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]5036
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]5037 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5038 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]5039 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]5040 // If the function stack isn't realigned we don't want to fold instructions
5041 // that need increased alignment.
5042 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]5043 Alignment =
5044 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5045 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5046 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5047 unsigned RCSize = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5048 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5049 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5050 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]5051 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5052 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5053 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5054 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5055 // Check if it's safe to fold the load. If the size of the object is
5056 // narrower than the load width, then it's not.
5057 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5058 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5059 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5060 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5061 MI->getOperand(1).ChangeToImmediate(0);
5062 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5063 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5064
5065 SmallVector<MachineOperand,4> MOs;
5066 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5067 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
5068 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5069}
5070
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5071static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
5072 const MachineFunction &MF) {
5073 unsigned Opc = LoadMI.getOpcode();
5074 unsigned RegSize =
5075 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
5076
5077 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
5078 // These instructions only load 32 bits, we can't fold them if the
5079 // destination register is wider than 32 bits (4 bytes).
5080 return true;
5081
5082 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
5083 // These instructions only load 64 bits, we can't fold them if the
5084 // destination register is wider than 64 bits (8 bytes).
5085 return true;
5086
5087 return false;
5088}
5089
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]5090MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
5091 MachineInstr *MI,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]5092 const SmallVectorImpl<unsigned> &Ops,
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]5093 MachineInstr *LoadMI) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]5094 // If loading from a FrameIndex, fold directly from the FrameIndex.
5095 unsigned NumOps = LoadMI->getDesc().getNumOperands();
5096 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5097 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5098 if (isPartialRegisterLoad(*LoadMI, MF))
5099 return nullptr;
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]5100 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5101 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]5102
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5103 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5104 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5105
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5106 // Unless optimizing for size, don't fold to avoid partial
5107 // register update stalls
Duncan P. N. Exon Smith5975a702015-02-14 01:59:52 +0000[diff] [blame]5108 if (!MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5109 hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5110 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]5111
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]5112 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]5113 unsigned Alignment = 0;
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]5114 if (LoadMI->hasOneMemOperand())
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]5115 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5116 else
5117 switch (LoadMI->getOpcode()) {
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]5118 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5119 case X86::AVX_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5120 Alignment = 32;
5121 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5122 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5123 case X86::V_SETALLONES:
5124 Alignment = 16;
5125 break;
5126 case X86::FsFLD0SD:
5127 Alignment = 8;
5128 break;
5129 case X86::FsFLD0SS:
5130 Alignment = 4;
5131 break;
5132 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5133 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5134 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5135 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5136 unsigned NewOpc = 0;
5137 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5138 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5139 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5140 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5141 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5142 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5143 }
5144 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5145 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5146 MI->getOperand(1).ChangeToImmediate(0);
5147 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5148 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5149
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]5150 // Make sure the subregisters match.
5151 // Otherwise we risk changing the size of the load.
5152 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5153 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]5154
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5155 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5156 switch (LoadMI->getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5157 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5158 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]5159 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5160 case X86::AVX_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5161 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5162 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5163 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5164 // Create a constant-pool entry and operands to load from it.
5165
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]5166 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5167 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5168 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5169 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]5170
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5171 // x86-32 PIC requires a PIC base register for constant pools.
5172 unsigned PICBase = 0;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5173 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
5174 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]5175 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]5176 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5177 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]5178 // This doesn't work for several reasons.
5179 // 1. GlobalBaseReg may have been spilled.
5180 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5181 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]5182 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5183
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5184 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5185 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]5186 Type *Ty;
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5187 unsigned Opc = LoadMI->getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5188 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5189 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5190 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5191 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5192 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]5193 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5194 else
5195 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]5196
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5197 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]5198 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5199 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5200 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5201
5202 // Create operands to load from the constant pool entry.
5203 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5204 MOs.push_back(MachineOperand::CreateImm(1));
5205 MOs.push_back(MachineOperand::CreateReg(0, false));
5206 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]5207 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5208 break;
5209 }
5210 default: {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5211 if (isPartialRegisterLoad(*LoadMI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5212 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]5213
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5214 // Folding a normal load. Just copy the load's address operands.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5215 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5216 MOs.push_back(LoadMI->getOperand(i));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5217 break;
5218 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5219 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5220 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
5221 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5222}
5223
5224
Dan Gohman33332bc2008-10-16 01:49:15 +0000[diff] [blame]5225bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
5226 const SmallVectorImpl<unsigned> &Ops) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5227 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5228 if (NoFusing) return 0;
5229
5230 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5231 switch (MI->getOpcode()) {
5232 default: return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5233 case X86::TEST8rr:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5234 case X86::TEST16rr:
5235 case X86::TEST32rr:
5236 case X86::TEST64rr:
5237 return true;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5238 case X86::ADD32ri:
5239 // FIXME: AsmPrinter doesn't know how to handle
5240 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5241 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5242 return false;
5243 break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5244 }
5245 }
5246
5247 if (Ops.size() != 1)
5248 return false;
5249
5250 unsigned OpNum = Ops[0];
5251 unsigned Opc = MI->getOpcode();
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]5252 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5253 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5254 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5255
5256 // Folding a memory location into the two-address part of a two-address
5257 // instruction is different than folding it other places. It requires
5258 // replacing the *two* registers with the memory location.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5259 const DenseMap<unsigned,
5260 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5261 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5262 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5263 } else if (OpNum == 0) {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5264 if (Opc == X86::MOV32r0)
5265 return true;
5266
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5267 OpcodeTablePtr = &RegOp2MemOpTable0;
5268 } else if (OpNum == 1) {
5269 OpcodeTablePtr = &RegOp2MemOpTable1;
5270 } else if (OpNum == 2) {
5271 OpcodeTablePtr = &RegOp2MemOpTable2;
Craig Topper7573c8f2012-08-31 22:12:16 +0000[diff] [blame]5272 } else if (OpNum == 3) {
5273 OpcodeTablePtr = &RegOp2MemOpTable3;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5274 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5275
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]5276 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
5277 return true;
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]5278 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5279}
5280
5281bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
5282 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]5283 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5284 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5285 MemOp2RegOpTable.find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5286 if (I == MemOp2RegOpTable.end())
5287 return false;
5288 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5289 unsigned Index = I->second.second & TB_INDEX_MASK;
5290 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5291 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5292 if (UnfoldLoad && !FoldedLoad)
5293 return false;
5294 UnfoldLoad &= FoldedLoad;
5295 if (UnfoldStore && !FoldedStore)
5296 return false;
5297 UnfoldStore &= FoldedStore;
5298
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5299 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5300 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5301 if (!MI->hasOneMemOperand() &&
5302 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5303 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5304 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5305 // conservatively assume the address is unaligned. That's bad for
5306 // performance.
5307 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5308 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5309 SmallVector<MachineOperand,2> BeforeOps;
5310 SmallVector<MachineOperand,2> AfterOps;
5311 SmallVector<MachineOperand,4> ImpOps;
5312 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5313 MachineOperand &Op = MI->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5314 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5315 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5316 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5317 ImpOps.push_back(Op);
5318 else if (i < Index)
5319 BeforeOps.push_back(Op);
5320 else if (i > Index)
5321 AfterOps.push_back(Op);
5322 }
5323
5324 // Emit the load instruction.
5325 if (UnfoldLoad) {
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5326 std::pair<MachineInstr::mmo_iterator,
5327 MachineInstr::mmo_iterator> MMOs =
5328 MF.extractLoadMemRefs(MI->memoperands_begin(),
5329 MI->memoperands_end());
5330 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5331 if (UnfoldStore) {
5332 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5333 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5334 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5335 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5336 MO.setIsKill(false);
5337 }
5338 }
5339 }
5340
5341 // Emit the data processing instruction.
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5342 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5343 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5344
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5345 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]5346 MIB.addReg(Reg, RegState::Define);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5347 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5348 MIB.addOperand(BeforeOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5349 if (FoldedLoad)
5350 MIB.addReg(Reg);
5351 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5352 MIB.addOperand(AfterOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5353 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
5354 MachineOperand &MO = ImpOps[i];
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]5355 MIB.addReg(MO.getReg(),
5356 getDefRegState(MO.isDef()) |
5357 RegState::Implicit |
5358 getKillRegState(MO.isKill()) |
Evan Cheng0dc101b2009-06-30 08:49:04 +0000[diff] [blame]5359 getDeadRegState(MO.isDead()) |
5360 getUndefRegState(MO.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5361 }
5362 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5363 switch (DataMI->getOpcode()) {
5364 default: break;
5365 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5366 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5367 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5368 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5369 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5370 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5371 case X86::CMP8ri: {
5372 MachineOperand &MO0 = DataMI->getOperand(0);
5373 MachineOperand &MO1 = DataMI->getOperand(1);
5374 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5375 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5376 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5377 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5378 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5379 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5380 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5381 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5382 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5383 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5384 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5385 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5386 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5387 MO1.ChangeToRegister(MO0.getReg(), false);
5388 }
5389 }
5390 }
5391 NewMIs.push_back(DataMI);
5392
5393 // Emit the store instruction.
5394 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5395 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5396 std::pair<MachineInstr::mmo_iterator,
5397 MachineInstr::mmo_iterator> MMOs =
5398 MF.extractStoreMemRefs(MI->memoperands_begin(),
5399 MI->memoperands_end());
5400 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5401 }
5402
5403 return true;
5404}
5405
5406bool
5407X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]5408 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]5409 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5410 return false;
5411
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5412 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5413 MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5414 if (I == MemOp2RegOpTable.end())
5415 return false;
5416 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5417 unsigned Index = I->second.second & TB_INDEX_MASK;
5418 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5419 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5420 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5421 MachineFunction &MF = DAG.getMachineFunction();
5422 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5423 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5424 std::vector<SDValue> AddrOps;
5425 std::vector<SDValue> BeforeOps;
5426 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]5427 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5428 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]5429 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5430 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5431 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5432 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]5433 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5434 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]5435 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5436 AfterOps.push_back(Op);
5437 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5438 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5439 AddrOps.push_back(Chain);
5440
5441 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5442 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5443 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5444 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]5445 std::pair<MachineInstr::mmo_iterator,
5446 MachineInstr::mmo_iterator> MMOs =
5447 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5448 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5449 if (!(*MMOs.first) &&
5450 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5451 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5452 // Do not introduce a slow unaligned load.
5453 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5454 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5455 bool isAligned = (*MMOs.first) &&
5456 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5457 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]5458 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5459 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5460
5461 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5462 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5463 }
5464
5465 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5466 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5467 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5468 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5469 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5470 VTs.push_back(*DstRC->vt_begin());
5471 }
5472 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5473 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5474 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5475 VTs.push_back(VT);
5476 }
5477 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5478 BeforeOps.push_back(SDValue(Load, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5479 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]5480 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5481 NewNodes.push_back(NewNode);
5482
5483 // Emit the store instruction.
5484 if (FoldedStore) {
5485 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5486 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5487 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]5488 std::pair<MachineInstr::mmo_iterator,
5489 MachineInstr::mmo_iterator> MMOs =
5490 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5491 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5492 if (!(*MMOs.first) &&
5493 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5494 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5495 // Do not introduce a slow unaligned store.
5496 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5497 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5498 bool isAligned = (*MMOs.first) &&
5499 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5500 SDNode *Store =
5501 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5502 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5503 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5504
5505 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]5506 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5507 }
5508
5509 return true;
5510}
5511
5512unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]5513 bool UnfoldLoad, bool UnfoldStore,
5514 unsigned *LoadRegIndex) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5515 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5516 MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5517 if (I == MemOp2RegOpTable.end())
5518 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5519 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5520 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5521 if (UnfoldLoad && !FoldedLoad)
5522 return 0;
5523 if (UnfoldStore && !FoldedStore)
5524 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]5525 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5526 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5527 return I->second.first;
5528}
5529
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5530bool
5531X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5532 int64_t &Offset1, int64_t &Offset2) const {
5533 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5534 return false;
5535 unsigned Opc1 = Load1->getMachineOpcode();
5536 unsigned Opc2 = Load2->getMachineOpcode();
5537 switch (Opc1) {
5538 default: return false;
5539 case X86::MOV8rm:
5540 case X86::MOV16rm:
5541 case X86::MOV32rm:
5542 case X86::MOV64rm:
5543 case X86::LD_Fp32m:
5544 case X86::LD_Fp64m:
5545 case X86::LD_Fp80m:
5546 case X86::MOVSSrm:
5547 case X86::MOVSDrm:
5548 case X86::MMX_MOVD64rm:
5549 case X86::MMX_MOVQ64rm:
5550 case X86::FsMOVAPSrm:
5551 case X86::FsMOVAPDrm:
5552 case X86::MOVAPSrm:
5553 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5554 case X86::MOVAPDrm:
5555 case X86::MOVDQArm:
5556 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5557 // AVX load instructions
5558 case X86::VMOVSSrm:
5559 case X86::VMOVSDrm:
5560 case X86::FsVMOVAPSrm:
5561 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5562 case X86::VMOVAPSrm:
5563 case X86::VMOVUPSrm:
5564 case X86::VMOVAPDrm:
5565 case X86::VMOVDQArm:
5566 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5567 case X86::VMOVAPSYrm:
5568 case X86::VMOVUPSYrm:
5569 case X86::VMOVAPDYrm:
5570 case X86::VMOVDQAYrm:
5571 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5572 break;
5573 }
5574 switch (Opc2) {
5575 default: return false;
5576 case X86::MOV8rm:
5577 case X86::MOV16rm:
5578 case X86::MOV32rm:
5579 case X86::MOV64rm:
5580 case X86::LD_Fp32m:
5581 case X86::LD_Fp64m:
5582 case X86::LD_Fp80m:
5583 case X86::MOVSSrm:
5584 case X86::MOVSDrm:
5585 case X86::MMX_MOVD64rm:
5586 case X86::MMX_MOVQ64rm:
5587 case X86::FsMOVAPSrm:
5588 case X86::FsMOVAPDrm:
5589 case X86::MOVAPSrm:
5590 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5591 case X86::MOVAPDrm:
5592 case X86::MOVDQArm:
5593 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5594 // AVX load instructions
5595 case X86::VMOVSSrm:
5596 case X86::VMOVSDrm:
5597 case X86::FsVMOVAPSrm:
5598 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5599 case X86::VMOVAPSrm:
5600 case X86::VMOVUPSrm:
5601 case X86::VMOVAPDrm:
5602 case X86::VMOVDQArm:
5603 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5604 case X86::VMOVAPSYrm:
5605 case X86::VMOVUPSYrm:
5606 case X86::VMOVAPDYrm:
5607 case X86::VMOVDQAYrm:
5608 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5609 break;
5610 }
5611
5612 // Check if chain operands and base addresses match.
5613 if (Load1->getOperand(0) != Load2->getOperand(0) ||
5614 Load1->getOperand(5) != Load2->getOperand(5))
5615 return false;
5616 // Segment operands should match as well.
5617 if (Load1->getOperand(4) != Load2->getOperand(4))
5618 return false;
5619 // Scale should be 1, Index should be Reg0.
5620 if (Load1->getOperand(1) == Load2->getOperand(1) &&
5621 Load1->getOperand(2) == Load2->getOperand(2)) {
5622 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5623 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5624
5625 // Now let's examine the displacements.
5626 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5627 isa<ConstantSDNode>(Load2->getOperand(3))) {
5628 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5629 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5630 return true;
5631 }
5632 }
5633 return false;
5634}
5635
5636bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5637 int64_t Offset1, int64_t Offset2,
5638 unsigned NumLoads) const {
5639 assert(Offset2 > Offset1);
5640 if ((Offset2 - Offset1) / 8 > 64)
5641 return false;
5642
5643 unsigned Opc1 = Load1->getMachineOpcode();
5644 unsigned Opc2 = Load2->getMachineOpcode();
5645 if (Opc1 != Opc2)
5646 return false; // FIXME: overly conservative?
5647
5648 switch (Opc1) {
5649 default: break;
5650 case X86::LD_Fp32m:
5651 case X86::LD_Fp64m:
5652 case X86::LD_Fp80m:
5653 case X86::MMX_MOVD64rm:
5654 case X86::MMX_MOVQ64rm:
5655 return false;
5656 }
5657
5658 EVT VT = Load1->getValueType(0);
5659 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5660 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5661 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5662 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5663 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5664 if (NumLoads >= 3)
5665 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5666 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5667 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5668 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5669 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5670 case MVT::i8:
5671 case MVT::i16:
5672 case MVT::i32:
5673 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]5674 case MVT::f32:
5675 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5676 if (NumLoads)
5677 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5678 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5679 }
5680
5681 return true;
5682}
5683
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5684bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5685 MachineInstr *Second) const {
5686 // Check if this processor supports macro-fusion. Since this is a minor
5687 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5688 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5689 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5690 return false;
5691
5692 enum {
5693 FuseTest,
5694 FuseCmp,
5695 FuseInc
5696 } FuseKind;
5697
5698 switch(Second->getOpcode()) {
5699 default:
5700 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5701 case X86::JE_1:
5702 case X86::JNE_1:
5703 case X86::JL_1:
5704 case X86::JLE_1:
5705 case X86::JG_1:
5706 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5707 FuseKind = FuseInc;
5708 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5709 case X86::JB_1:
5710 case X86::JBE_1:
5711 case X86::JA_1:
5712 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5713 FuseKind = FuseCmp;
5714 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5715 case X86::JS_1:
5716 case X86::JNS_1:
5717 case X86::JP_1:
5718 case X86::JNP_1:
5719 case X86::JO_1:
5720 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5721 FuseKind = FuseTest;
5722 break;
5723 }
5724 switch (First->getOpcode()) {
5725 default:
5726 return false;
5727 case X86::TEST8rr:
5728 case X86::TEST16rr:
5729 case X86::TEST32rr:
5730 case X86::TEST64rr:
5731 case X86::TEST8ri:
5732 case X86::TEST16ri:
5733 case X86::TEST32ri:
5734 case X86::TEST32i32:
5735 case X86::TEST64i32:
5736 case X86::TEST64ri32:
5737 case X86::TEST8rm:
5738 case X86::TEST16rm:
5739 case X86::TEST32rm:
5740 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]5741 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5742 case X86::AND16i16:
5743 case X86::AND16ri:
5744 case X86::AND16ri8:
5745 case X86::AND16rm:
5746 case X86::AND16rr:
5747 case X86::AND32i32:
5748 case X86::AND32ri:
5749 case X86::AND32ri8:
5750 case X86::AND32rm:
5751 case X86::AND32rr:
5752 case X86::AND64i32:
5753 case X86::AND64ri32:
5754 case X86::AND64ri8:
5755 case X86::AND64rm:
5756 case X86::AND64rr:
5757 case X86::AND8i8:
5758 case X86::AND8ri:
5759 case X86::AND8rm:
5760 case X86::AND8rr:
5761 return true;
5762 case X86::CMP16i16:
5763 case X86::CMP16ri:
5764 case X86::CMP16ri8:
5765 case X86::CMP16rm:
5766 case X86::CMP16rr:
5767 case X86::CMP32i32:
5768 case X86::CMP32ri:
5769 case X86::CMP32ri8:
5770 case X86::CMP32rm:
5771 case X86::CMP32rr:
5772 case X86::CMP64i32:
5773 case X86::CMP64ri32:
5774 case X86::CMP64ri8:
5775 case X86::CMP64rm:
5776 case X86::CMP64rr:
5777 case X86::CMP8i8:
5778 case X86::CMP8ri:
5779 case X86::CMP8rm:
5780 case X86::CMP8rr:
5781 case X86::ADD16i16:
5782 case X86::ADD16ri:
5783 case X86::ADD16ri8:
5784 case X86::ADD16ri8_DB:
5785 case X86::ADD16ri_DB:
5786 case X86::ADD16rm:
5787 case X86::ADD16rr:
5788 case X86::ADD16rr_DB:
5789 case X86::ADD32i32:
5790 case X86::ADD32ri:
5791 case X86::ADD32ri8:
5792 case X86::ADD32ri8_DB:
5793 case X86::ADD32ri_DB:
5794 case X86::ADD32rm:
5795 case X86::ADD32rr:
5796 case X86::ADD32rr_DB:
5797 case X86::ADD64i32:
5798 case X86::ADD64ri32:
5799 case X86::ADD64ri32_DB:
5800 case X86::ADD64ri8:
5801 case X86::ADD64ri8_DB:
5802 case X86::ADD64rm:
5803 case X86::ADD64rr:
5804 case X86::ADD64rr_DB:
5805 case X86::ADD8i8:
5806 case X86::ADD8mi:
5807 case X86::ADD8mr:
5808 case X86::ADD8ri:
5809 case X86::ADD8rm:
5810 case X86::ADD8rr:
5811 case X86::SUB16i16:
5812 case X86::SUB16ri:
5813 case X86::SUB16ri8:
5814 case X86::SUB16rm:
5815 case X86::SUB16rr:
5816 case X86::SUB32i32:
5817 case X86::SUB32ri:
5818 case X86::SUB32ri8:
5819 case X86::SUB32rm:
5820 case X86::SUB32rr:
5821 case X86::SUB64i32:
5822 case X86::SUB64ri32:
5823 case X86::SUB64ri8:
5824 case X86::SUB64rm:
5825 case X86::SUB64rr:
5826 case X86::SUB8i8:
5827 case X86::SUB8ri:
5828 case X86::SUB8rm:
5829 case X86::SUB8rr:
5830 return FuseKind == FuseCmp || FuseKind == FuseInc;
5831 case X86::INC16r:
5832 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5833 case X86::INC64r:
5834 case X86::INC8r:
5835 case X86::DEC16r:
5836 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5837 case X86::DEC64r:
5838 case X86::DEC8r:
5839 return FuseKind == FuseInc;
5840 }
5841}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5842
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]5843bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]5844ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]5845 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]5846 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]5847 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5848 return true;
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]5849 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]5850 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]5851}
5852
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5853bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]5854isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5855 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5856 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]5857 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5858 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5859}
5860
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5861/// getGlobalBaseReg - Return a virtual register initialized with the
5862/// the global base register value. Output instructions required to
5863/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5864///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5865/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5866///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5867unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5868 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5869 "X86-64 PIC uses RIP relative addressing");
5870
5871 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5872 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5873 if (GlobalBaseReg != 0)
5874 return GlobalBaseReg;
5875
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5876 // Create the register. The code to initialize it is inserted
5877 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5878 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]5879 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5880 X86FI->setGlobalBaseReg(GlobalBaseReg);
5881 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5882}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5883
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5884// These are the replaceable SSE instructions. Some of these have Int variants
5885// that we don't include here. We don't want to replace instructions selected
5886// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5887static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]5888 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]5889 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5890 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5891 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5892 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5893 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5894 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5895 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5896 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5897 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5898 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5899 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5900 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5901 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5902 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5903 // AVX 128-bit support
5904 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5905 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5906 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5907 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5908 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5909 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5910 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5911 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5912 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5913 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5914 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5915 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5916 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5917 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5918 // AVX 256-bit support
5919 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5920 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5921 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5922 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5923 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5924 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
5925};
5926
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5927static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5928 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]5929 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
5930 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
5931 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
5932 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
5933 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
5934 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
5935 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]5936 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
5937 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5938 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5939 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
5940 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
5941 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]5942 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
5943 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5944 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5945 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5946 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5947 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5948 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5949};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5950
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5951// FIXME: Some shuffle and unpack instructions have equivalents in different
5952// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5953
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5954static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5955 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5956 if (ReplaceableInstrs[i][domain-1] == opcode)
5957 return ReplaceableInstrs[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5958 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5959}
5960
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5961static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5962 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5963 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5964 return ReplaceableInstrsAVX2[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5965 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5966}
5967
5968std::pair<uint16_t, uint16_t>
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]5969X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5970 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5971 bool hasAVX2 = Subtarget.hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5972 uint16_t validDomains = 0;
5973 if (domain && lookup(MI->getOpcode(), domain))
5974 validDomains = 0xe;
5975 else if (domain && lookupAVX2(MI->getOpcode(), domain))
5976 validDomains = hasAVX2 ? 0xe : 0x6;
5977 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5978}
5979
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]5980void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5981 assert(Domain>0 && Domain<4 && "Invalid execution domain");
5982 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5983 assert(dom && "Not an SSE instruction");
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5984 const uint16_t *table = lookup(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5985 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5986 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5987 "256-bit vector operations only available in AVX2");
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5988 table = lookupAVX2(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5989 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5990 assert(table && "Cannot change domain");
5991 MI->setDesc(get(table[Domain-1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5992}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]5993
5994/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5995void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5996 NopInst.setOpcode(X86::NOOP);
5997}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5998
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]5999// This code must remain in sync with getJumpInstrTableEntryBound in this class!
6000// In particular, getJumpInstrTableEntryBound must always return an upper bound
6001// on the encoding lengths of the instructions generated by
6002// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]6003void X86InstrInfo::getUnconditionalBranch(
6004 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6005 Branch.setOpcode(X86::JMP_1);
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]6006 Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
6007}
6008
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]6009// This code must remain in sync with getJumpInstrTableEntryBound in this class!
6010// In particular, getJumpInstrTableEntryBound must always return an upper bound
6011// on the encoding lengths of the instructions generated by
6012// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]6013void X86InstrInfo::getTrap(MCInst &MI) const {
6014 MI.setOpcode(X86::TRAP);
6015}
6016
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]6017// See getTrap and getUnconditionalBranch for conditions on the value returned
6018// by this function.
6019unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
6020 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
6021 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
6022 return 5;
6023}
6024
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]6025bool X86InstrInfo::isHighLatencyDef(int opc) const {
6026 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6027 default: return false;
6028 case X86::DIVSDrm:
6029 case X86::DIVSDrm_Int:
6030 case X86::DIVSDrr:
6031 case X86::DIVSDrr_Int:
6032 case X86::DIVSSrm:
6033 case X86::DIVSSrm_Int:
6034 case X86::DIVSSrr:
6035 case X86::DIVSSrr_Int:
6036 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6037 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6038 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6039 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6040 case X86::SQRTSDm:
6041 case X86::SQRTSDm_Int:
6042 case X86::SQRTSDr:
6043 case X86::SQRTSDr_Int:
6044 case X86::SQRTSSm:
6045 case X86::SQRTSSm_Int:
6046 case X86::SQRTSSr:
6047 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6048 // AVX instructions with high latency
6049 case X86::VDIVSDrm:
6050 case X86::VDIVSDrm_Int:
6051 case X86::VDIVSDrr:
6052 case X86::VDIVSDrr_Int:
6053 case X86::VDIVSSrm:
6054 case X86::VDIVSSrm_Int:
6055 case X86::VDIVSSrr:
6056 case X86::VDIVSSrr_Int:
6057 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6058 case X86::VSQRTPDr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6059 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6060 case X86::VSQRTPSr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6061 case X86::VSQRTSDm:
6062 case X86::VSQRTSDm_Int:
6063 case X86::VSQRTSDr:
6064 case X86::VSQRTSSm:
6065 case X86::VSQRTSSm_Int:
6066 case X86::VSQRTSSr:
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]6067 case X86::VSQRTPDZm:
6068 case X86::VSQRTPDZr:
6069 case X86::VSQRTPSZm:
6070 case X86::VSQRTPSZr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]6071 case X86::VSQRTSDZm:
6072 case X86::VSQRTSDZm_Int:
6073 case X86::VSQRTSDZr:
6074 case X86::VSQRTSSZm_Int:
6075 case X86::VSQRTSSZr:
6076 case X86::VSQRTSSZm:
6077 case X86::VDIVSDZrm:
6078 case X86::VDIVSDZrr:
6079 case X86::VDIVSSZrm:
6080 case X86::VDIVSSZrr:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]6081
6082 case X86::VGATHERQPSZrm:
6083 case X86::VGATHERQPDZrm:
6084 case X86::VGATHERDPDZrm:
6085 case X86::VGATHERDPSZrm:
6086 case X86::VPGATHERQDZrm:
6087 case X86::VPGATHERQQZrm:
6088 case X86::VPGATHERDDZrm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]6089 case X86::VPGATHERDQZrm:
6090 case X86::VSCATTERQPDZmr:
6091 case X86::VSCATTERQPSZmr:
6092 case X86::VSCATTERDPDZmr:
6093 case X86::VSCATTERDPSZmr:
6094 case X86::VPSCATTERQDZmr:
6095 case X86::VPSCATTERQQZmr:
6096 case X86::VPSCATTERDDZmr:
6097 case X86::VPSCATTERDQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6098 return true;
6099 }
6100}
6101
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]6102bool X86InstrInfo::
6103hasHighOperandLatency(const InstrItineraryData *ItinData,
6104 const MachineRegisterInfo *MRI,
6105 const MachineInstr *DefMI, unsigned DefIdx,
6106 const MachineInstr *UseMI, unsigned UseIdx) const {
6107 return isHighLatencyDef(DefMI->getOpcode());
6108}
6109
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6110namespace {
6111 /// CGBR - Create Global Base Reg pass. This initializes the PIC
6112 /// global base register for x86-32.
6113 struct CGBR : public MachineFunctionPass {
6114 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]6115 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6116
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6117 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6118 const X86TargetMachine *TM =
6119 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6120 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6121
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]6122 // Don't do anything if this is 64-bit as 64-bit PIC
6123 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6124 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]6125 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6126
6127 // Only emit a global base reg in PIC mode.
6128 if (TM->getRelocationModel() != Reloc::PIC_)
6129 return false;
6130
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]6131 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
6132 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6133
6134 // If we didn't need a GlobalBaseReg, don't insert code.
6135 if (GlobalBaseReg == 0)
6136 return false;
6137
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6138 // Insert the set of GlobalBaseReg into the first MBB of the function
6139 MachineBasicBlock &FirstMBB = MF.front();
6140 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
6141 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
6142 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6143 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6144
6145 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6146 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]6147 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6148 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]6149 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6150
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6151 // Operand of MovePCtoStack is completely ignored by asm printer. It's
6152 // only used in JIT code emission as displacement to pc.
6153 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6154
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6155 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
6156 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6157 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6158 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
6159 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
6160 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
6161 X86II::MO_GOT_ABSOLUTE_ADDRESS);
6162 }
6163
6164 return true;
6165 }
6166
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6167 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6168 return "X86 PIC Global Base Reg Initialization";
6169 }
6170
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6171 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6172 AU.setPreservesCFG();
6173 MachineFunctionPass::getAnalysisUsage(AU);
6174 }
6175 };
6176}
6177
6178char CGBR::ID = 0;
6179FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]6180llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6181
6182namespace {
6183 struct LDTLSCleanup : public MachineFunctionPass {
6184 static char ID;
6185 LDTLSCleanup() : MachineFunctionPass(ID) {}
6186
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6187 bool runOnMachineFunction(MachineFunction &MF) override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6188 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
6189 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
6190 // No point folding accesses if there isn't at least two.
6191 return false;
6192 }
6193
6194 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
6195 return VisitNode(DT->getRootNode(), 0);
6196 }
6197
6198 // Visit the dominator subtree rooted at Node in pre-order.
6199 // If TLSBaseAddrReg is non-null, then use that to replace any
6200 // TLS_base_addr instructions. Otherwise, create the register
6201 // when the first such instruction is seen, and then use it
6202 // as we encounter more instructions.
6203 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
6204 MachineBasicBlock *BB = Node->getBlock();
6205 bool Changed = false;
6206
6207 // Traverse the current block.
6208 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
6209 ++I) {
6210 switch (I->getOpcode()) {
6211 case X86::TLS_base_addr32:
6212 case X86::TLS_base_addr64:
6213 if (TLSBaseAddrReg)
6214 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
6215 else
6216 I = SetRegister(I, &TLSBaseAddrReg);
6217 Changed = true;
6218 break;
6219 default:
6220 break;
6221 }
6222 }
6223
6224 // Visit the children of this block in the dominator tree.
6225 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
6226 I != E; ++I) {
6227 Changed |= VisitNode(*I, TLSBaseAddrReg);
6228 }
6229
6230 return Changed;
6231 }
6232
6233 // Replace the TLS_base_addr instruction I with a copy from
6234 // TLSBaseAddrReg, returning the new instruction.
6235 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
6236 unsigned TLSBaseAddrReg) {
6237 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6238 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6239 const bool is64Bit = STI.is64Bit();
6240 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6241
6242 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
6243 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
6244 TII->get(TargetOpcode::COPY),
6245 is64Bit ? X86::RAX : X86::EAX)
6246 .addReg(TLSBaseAddrReg);
6247
6248 // Erase the TLS_base_addr instruction.
6249 I->eraseFromParent();
6250
6251 return Copy;
6252 }
6253
6254 // Create a virtal register in *TLSBaseAddrReg, and populate it by
6255 // inserting a copy instruction after I. Returns the new instruction.
6256 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
6257 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6258 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6259 const bool is64Bit = STI.is64Bit();
6260 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6261
6262 // Create a virtual register for the TLS base address.
6263 MachineRegisterInfo &RegInfo = MF->getRegInfo();
6264 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
6265 ? &X86::GR64RegClass
6266 : &X86::GR32RegClass);
6267
6268 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
6269 MachineInstr *Next = I->getNextNode();
6270 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
6271 TII->get(TargetOpcode::COPY),
6272 *TLSBaseAddrReg)
6273 .addReg(is64Bit ? X86::RAX : X86::EAX);
6274
6275 return Copy;
6276 }
6277
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6278 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6279 return "Local Dynamic TLS Access Clean-up";
6280 }
6281
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6282 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6283 AU.setPreservesCFG();
6284 AU.addRequired<MachineDominatorTree>();
6285 MachineFunctionPass::getAnalysisUsage(AU);
6286 }
6287 };
6288}
6289
6290char LDTLSCleanup::ID = 0;
6291FunctionPass*
6292llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }