Javed Absar | 2cb0c95 | 2017-07-19 12:57:16 +0000 | [diff] [blame] | 1 | //===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains small standalone helper functions and enum definitions for |
| 11 | // the ARM target useful for the compiler back-end and the MC libraries. |
| 12 | // As such, it deliberately does not include references to LLVM core |
| 13 | // code gen types, passes, etc.. |
| 14 | // |
| 15 | //===----------------------------------------------------------------------===// |
| 16 | |
| 17 | #ifndef LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H |
| 18 | #define LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H |
| 19 | |
| 20 | #include "llvm/ADT/StringSwitch.h" |
| 21 | #include "llvm/Support/ErrorHandling.h" |
| 22 | #include "llvm/MC/SubtargetFeature.h" |
| 23 | #include "MCTargetDesc/ARMMCTargetDesc.h" |
| 24 | |
| 25 | namespace llvm { |
| 26 | |
Javed Absar | 054d1ae | 2017-08-03 01:24:12 +0000 | [diff] [blame] | 27 | // System Registers |
Javed Absar | 2cb0c95 | 2017-07-19 12:57:16 +0000 | [diff] [blame] | 28 | namespace ARMSysReg { |
| 29 | struct MClassSysReg { |
| 30 | const char *Name; |
| 31 | uint16_t M1Encoding12; |
| 32 | uint16_t M2M3Encoding8; |
| 33 | uint16_t Encoding; |
| 34 | FeatureBitset FeaturesRequired; |
| 35 | |
| 36 | // return true if FeaturesRequired are all present in ActiveFeatures |
| 37 | bool hasRequiredFeatures(FeatureBitset ActiveFeatures) const { |
| 38 | return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; |
| 39 | } |
| 40 | |
| 41 | // returns true if TestFeatures are all present in FeaturesRequired |
| 42 | bool isInRequiredFeatures(FeatureBitset TestFeatures) const { |
| 43 | return (FeaturesRequired & TestFeatures) == TestFeatures; |
| 44 | } |
| 45 | }; |
| 46 | |
| 47 | #define GET_MCLASSSYSREG_DECL |
| 48 | #include "ARMGenSystemRegister.inc" |
| 49 | |
| 50 | // lookup system register using 12-bit SYSm value. |
| 51 | // Note: the search is uniqued using M1 mask |
| 52 | const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm); |
| 53 | |
| 54 | // returns APSR with _<bits> qualifier. |
| 55 | // Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier |
| 56 | const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm); |
| 57 | |
| 58 | // lookup system registers using 8-bit SYSm value |
| 59 | const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm); |
| 60 | |
| 61 | } // end namespace ARMSysReg |
| 62 | |
Javed Absar | 054d1ae | 2017-08-03 01:24:12 +0000 | [diff] [blame] | 63 | // Banked Registers |
| 64 | namespace ARMBankedReg { |
| 65 | struct BankedReg { |
| 66 | const char *Name; |
| 67 | uint16_t Encoding; |
| 68 | }; |
| 69 | #define GET_BANKEDREG_DECL |
| 70 | #include "ARMGenSystemRegister.inc" |
| 71 | } // end namespace ARMBankedReg |
| 72 | |
Javed Absar | 2cb0c95 | 2017-07-19 12:57:16 +0000 | [diff] [blame] | 73 | } // end namespace llvm |
| 74 | |
| 75 | #endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H |