Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / b9e35fbc1ef10d4fd1ab8f174933e5501e952184 / . / llvm / docs / CodeGenerator.html
blob: 32a3a971a32e088cc89c883362b6b01ba701f236 [file] [log] [blame]
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]1<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
2 "http://www.w3.org/TR/html4/strict.dtd">
3<html>
4<head>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]5 <meta http-equiv="content-type" content="text/html; charset=utf-8">
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]6 <title>The LLVM Target-Independent Code Generator</title>
7 <link rel="stylesheet" href="llvm.css" type="text/css">
Benjamin Kramerc940bcf2010-10-30 21:07:28 +0000[diff] [blame]8
9 <style type="text/css">
10 .unknown { background-color: #C0C0C0; text-align: center; }
11 .unknown:before { content: "?" }
12 .no { background-color: #C11B17 }
13 .no:before { content: "N" }
14 .partial { background-color: #F88017 }
15 .yes { background-color: #0F0; }
16 .yes:before { content: "Y" }
17 </style>
18
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]19</head>
20<body>
21
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]22<h1>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]23 The LLVM Target-Independent Code Generator
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]24</h1>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]25
26<ol>
27 <li><a href="#introduction">Introduction</a>
28 <ul>
29 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]30 <li><a href="#high-level-design">The high-level design of the code
31 generator</a></li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#tablegen">Using TableGen for target description</a></li>
33 </ul>
34 </li>
35 <li><a href="#targetdesc">Target description classes</a>
36 <ul>
37 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
38 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]39 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Dan Gohman3a4be0f2008-02-10 18:45:23 +0000[diff] [blame]40 <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]41 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
42 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattnerc9afa282005-10-16 17:06:07 +0000[diff] [blame]43 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]44 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
45 </ul>
46 </li>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]47 <li><a href="#codegendesc">The "Machine" Code Generator classes</a>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]48 <ul>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]49 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]50 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
51 class</a></li>
52 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Evan Chengc984bf82011-12-14 21:32:14 +0000[diff] [blame]53 <li><a href="#machineinstrbundle"><tt>MachineInstr Bundles</tt></a></li>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]54 </ul>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]55 </li>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]56 <li><a href="#mc">The "MC" Layer</a>
57 <ul>
58 <li><a href="#mcstreamer">The <tt>MCStreamer</tt> API</a></li>
59 <li><a href="#mccontext">The <tt>MCContext</tt> class</a>
60 <li><a href="#mcsymbol">The <tt>MCSymbol</tt> class</a></li>
61 <li><a href="#mcsection">The <tt>MCSection</tt> class</a></li>
62 <li><a href="#mcinst">The <tt>MCInst</tt> class</a></li>
63 </ul>
64 </li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]65 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]66 <ul>
67 <li><a href="#instselect">Instruction Selection</a>
68 <ul>
69 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
70 <li><a href="#selectiondag_process">SelectionDAG Code Generation
71 Process</a></li>
72 <li><a href="#selectiondag_build">Initial SelectionDAG
73 Construction</a></li>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]74 <li><a href="#selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a></li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]75 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
76 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]77 Phase: the DAG Combiner</a></li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]78 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]79 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]80 Phase</a></li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]81 <li><a href="#selectiondag_future">Future directions for the
82 SelectionDAG</a></li>
83 </ul></li>
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]84 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]85 <ul>
86 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]87 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]88 </ul></li>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]89 <li><a href="#regalloc">Register Allocation</a>
90 <ul>
91 <li><a href="#regAlloc_represent">How registers are represented in
92 LLVM</a></li>
93 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
94 registers</a></li>
95 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
96 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
97 <li><a href="#regAlloc_fold">Instruction folding</a></li>
98 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
99 </ul></li>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]100 <li><a href="#codeemit">Code Emission</a></li>
Anshuman Dasguptabcfa2f82011-12-06 23:12:42 +0000[diff] [blame]101 <li><a href="#vliw_packetizer">VLIW Packetizer</a>
102 <ul>
103 <li><a href="#vliw_mapping">Mapping from instructions to functional
104 units</a></li>
105 <li><a href="#vliw_repr">How the packetization tables are
106 generated and used</a></li>
107 </ul>
108 </li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]109 </ul>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]110 </li>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]111 <li><a href="#nativeassembler">Implementing a Native Assembler</a></li>
112
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]113 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]114 <ul>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]115 <li><a href="#targetfeatures">Target Feature Matrix</a></li>
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]116 <li><a href="#tailcallopt">Tail call optimization</a></li>
Evan Cheng59676492010-03-08 21:05:02 +0000[diff] [blame]117 <li><a href="#sibcallopt">Sibling call optimization</a></li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]118 <li><a href="#x86">The X86 backend</a></li>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]119 <li><a href="#ppc">The PowerPC backend</a>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]120 <ul>
121 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
122 <li><a href="#ppc_frame">Frame Layout</a></li>
123 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
124 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]125 </ul></li>
Justin Holewinski6c6a7fd2011-08-11 17:34:16 +0000[diff] [blame]126 <li><a href="#ptx">The PTX backend</a></li>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]127 </ul></li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]128
129</ol>
130
131<div class="doc_author">
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]132 <p>Written by the LLVM Team.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]133</div>
134
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]135<div class="doc_warning">
136 <p>Warning: This is a work in progress.</p>
137</div>
138
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]139<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]140<h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]141 <a name="introduction">Introduction</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]142</h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]143<!-- *********************************************************************** -->
144
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]145<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]146
147<p>The LLVM target-independent code generator is a framework that provides a
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]148 suite of reusable components for translating the LLVM internal representation
149 to the machine code for a specified target&mdash;either in assembly form
150 (suitable for a static compiler) or in binary machine code format (usable for
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]151 a JIT compiler). The LLVM target-independent code generator consists of six
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]152 main components:</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]153
154<ol>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]155 <li><a href="#targetdesc">Abstract target description</a> interfaces which
156 capture important properties about various aspects of the machine,
157 independently of how they will be used. These interfaces are defined in
158 <tt>include/llvm/Target/</tt>.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]159
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]160 <li>Classes used to represent the <a href="#codegendesc">code being
161 generated</a> for a target. These classes are intended to be abstract
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]162 enough to represent the machine code for <i>any</i> target machine. These
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]163 classes are defined in <tt>include/llvm/CodeGen/</tt>. At this level,
164 concepts like "constant pool entries" and "jump tables" are explicitly
165 exposed.</li>
166
167 <li>Classes and algorithms used to represent code as the object file level,
168 the <a href="#mc">MC Layer</a>. These classes represent assembly level
169 constructs like labels, sections, and instructions. At this level,
170 concepts like "constant pool entries" and "jump tables" don't exist.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]171
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]172 <li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
173 various phases of native code generation (register allocation, scheduling,
174 stack frame representation, etc). This code lives
175 in <tt>lib/CodeGen/</tt>.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]176
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]177 <li><a href="#targetimpls">Implementations of the abstract target description
178 interfaces</a> for particular targets. These machine descriptions make
179 use of the components provided by LLVM, and can optionally provide custom
180 target-specific passes, to build complete code generators for a specific
181 target. Target descriptions live in <tt>lib/Target/</tt>.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]182
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]183 <li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
184 completely target independent (it uses the <tt>TargetJITInfo</tt>
185 structure to interface for target-specific issues. The code for the
186 target-independent JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]187</ol>
188
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]189<p>Depending on which part of the code generator you are interested in working
190 on, different pieces of this will be useful to you. In any case, you should
191 be familiar with the <a href="#targetdesc">target description</a>
192 and <a href="#codegendesc">machine code representation</a> classes. If you
193 want to add a backend for a new target, you will need
194 to <a href="#targetimpls">implement the target description</a> classes for
195 your new target and understand the <a href="LangRef.html">LLVM code
196 representation</a>. If you are interested in implementing a
197 new <a href="#codegenalgs">code generation algorithm</a>, it should only
198 depend on the target-description and machine code representation classes,
199 ensuring that it is portable.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]200
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]201<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]202<h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]203 <a name="required">Required components in the code generator</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]204</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]205
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]206<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]207
208<p>The two pieces of the LLVM code generator are the high-level interface to the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]209 code generator and the set of reusable components that can be used to build
210 target-specific backends. The two most important interfaces
211 (<a href="#targetmachine"><tt>TargetMachine</tt></a>
212 and <a href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
213 required to be defined for a backend to fit into the LLVM system, but the
214 others must be defined if the reusable code generator components are going to
215 be used.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]216
217<p>This design has two important implications. The first is that LLVM can
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]218 support completely non-traditional code generation targets. For example, the
219 C backend does not require register allocation, instruction selection, or any
220 of the other standard components provided by the system. As such, it only
221 implements these two interfaces, and does its own thing. Another example of
222 a code generator like this is a (purely hypothetical) backend that converts
223 LLVM to the GCC RTL form and uses GCC to emit machine code for a target.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]224
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]225<p>This design also implies that it is possible to design and implement
226 radically different code generators in the LLVM system that do not make use
227 of any of the built-in components. Doing so is not recommended at all, but
228 could be required for radically different targets that do not fit into the
229 LLVM machine description model: FPGAs for example.</p>
Chris Lattnere6cad6c2004-06-02 07:06:06 +0000[diff] [blame]230
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]231</div>
232
233<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]234<h3>
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]235 <a name="high-level-design">The high-level design of the code generator</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]236</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]237
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]238<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]239
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]240<p>The LLVM target-independent code generator is designed to support efficient
241 and quality code generation for standard register-based microprocessors.
242 Code generation in this model is divided into the following stages:</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]243
244<ol>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]245 <li><b><a href="#instselect">Instruction Selection</a></b> &mdash; This phase
246 determines an efficient way to express the input LLVM code in the target
247 instruction set. This stage produces the initial code for the program in
248 the target instruction set, then makes use of virtual registers in SSA
249 form and physical registers that represent any required register
250 assignments due to target constraints or calling conventions. This step
251 turns the LLVM code into a DAG of target instructions.</li>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]252
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]253 <li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> &mdash;
254 This phase takes the DAG of target instructions produced by the
255 instruction selection phase, determines an ordering of the instructions,
256 then emits the instructions
257 as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering.
258 Note that we describe this in the <a href="#instselect">instruction
259 selection section</a> because it operates on
260 a <a href="#selectiondag_intro">SelectionDAG</a>.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]261
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]262 <li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> &mdash;
263 This optional stage consists of a series of machine-code optimizations
264 that operate on the SSA-form produced by the instruction selector.
265 Optimizations like modulo-scheduling or peephole optimization work
266 here.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]267
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]268 <li><b><a href="#regalloc">Register Allocation</a></b> &mdash; The target code
269 is transformed from an infinite virtual register file in SSA form to the
270 concrete register file used by the target. This phase introduces spill
271 code and eliminates all virtual register references from the program.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]272
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]273 <li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> &mdash; Once
274 the machine code has been generated for the function and the amount of
275 stack space required is known (used for LLVM alloca's and spill slots),
276 the prolog and epilog code for the function can be inserted and "abstract
277 stack location references" can be eliminated. This stage is responsible
278 for implementing optimizations like frame-pointer elimination and stack
279 packing.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]280
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]281 <li><b><a href="#latemco">Late Machine Code Optimizations</a></b> &mdash;
282 Optimizations that operate on "final" machine code can go here, such as
283 spill code scheduling and peephole optimizations.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]284
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]285 <li><b><a href="#codeemit">Code Emission</a></b> &mdash; The final stage
286 actually puts out the code for the current function, either in the target
287 assembler format or in machine code.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]288</ol>
289
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]290<p>The code generator is based on the assumption that the instruction selector
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]291 will use an optimal pattern matching selector to create high-quality
292 sequences of native instructions. Alternative code generator designs based
293 on pattern expansion and aggressive iterative peephole optimization are much
294 slower. This design permits efficient compilation (important for JIT
295 environments) and aggressive optimization (used when generating code offline)
296 by allowing components of varying levels of sophistication to be used for any
297 step of compilation.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]298
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]299<p>In addition to these stages, target implementations can insert arbitrary
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]300 target-specific passes into the flow. For example, the X86 target uses a
301 special pass to handle the 80x87 floating point stack architecture. Other
302 targets with unusual requirements can be supported with custom passes as
303 needed.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]304
305</div>
306
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]307<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]308<h3>
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]309 <a name="tablegen">Using TableGen for target description</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]310</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]311
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]312<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]313
Chris Lattnerd9be5fa2004-06-01 18:35:00 +0000[diff] [blame]314<p>The target description classes require a detailed description of the target
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]315 architecture. These target descriptions often have a large amount of common
316 information (e.g., an <tt>add</tt> instruction is almost identical to a
317 <tt>sub</tt> instruction). In order to allow the maximum amount of
318 commonality to be factored out, the LLVM code generator uses
319 the <a href="TableGenFundamentals.html">TableGen</a> tool to describe big
320 chunks of the target machine, which allows the use of domain-specific and
321 target-specific abstractions to reduce the amount of repetition.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]322
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]323<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]324 of the target description to the <tt>.td</tt> form. Doing so gives us a
325 number of advantages. The most important is that it makes it easier to port
326 LLVM because it reduces the amount of C++ code that has to be written, and
327 the surface area of the code generator that needs to be understood before
328 someone can get something working. Second, it makes it easier to change
329 things. In particular, if tables and other things are all emitted
330 by <tt>tblgen</tt>, we only need a change in one place (<tt>tblgen</tt>) to
331 update all of the targets to a new interface.</p>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]332
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]333</div>
334
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]335</div>
336
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]337<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]338<h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]339 <a name="targetdesc">Target description classes</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]340</h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]341<!-- *********************************************************************** -->
342
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]343<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]344
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]345<p>The LLVM target description classes (located in the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]346 <tt>include/llvm/Target</tt> directory) provide an abstract description of
347 the target machine independent of any particular client. These classes are
348 designed to capture the <i>abstract</i> properties of the target (such as the
349 instructions and registers it has), and do not incorporate any particular
350 pieces of code generation algorithms.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]351
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]352<p>All of the target description classes (except the
353 <tt><a href="#targetdata">TargetData</a></tt> class) are designed to be
354 subclassed by the concrete target implementation, and have virtual methods
355 implemented. To get to these implementations, the
356 <tt><a href="#targetmachine">TargetMachine</a></tt> class provides accessors
357 that should be implemented by the target.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]358
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]359<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]360<h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]361 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]362</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]363
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]364<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]365
366<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]367 access the target-specific implementations of the various target description
368 classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
369 <tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
370 designed to be specialized by a concrete target implementation
371 (e.g., <tt>X86TargetMachine</tt>) which implements the various virtual
372 methods. The only required target description class is
373 the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the code
374 generator components are to be used, the other interfaces should be
375 implemented as well.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]376
377</div>
378
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]379<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]380<h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]381 <a name="targetdata">The <tt>TargetData</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]382</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]383
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]384<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]385
386<p>The <tt>TargetData</tt> class is the only required target description class,
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]387 and it is the only class that is not extensible (you cannot derived a new
388 class from it). <tt>TargetData</tt> specifies information about how the
389 target lays out memory for structures, the alignment requirements for various
390 data types, the size of pointers in the target, and whether the target is
391 little-endian or big-endian.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]392
393</div>
394
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]395<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]396<h3>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]397 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]398</h3>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]399
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]400<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]401
402<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]403 selectors primarily to describe how LLVM code should be lowered to
404 SelectionDAG operations. Among other things, this class indicates:</p>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]405
406<ul>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]407 <li>an initial register class to use for various <tt>ValueType</tt>s,</li>
408
409 <li>which operations are natively supported by the target machine,</li>
410
411 <li>the return type of <tt>setcc</tt> operations,</li>
412
413 <li>the type to use for shift amounts, and</li>
414
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]415 <li>various high-level characteristics, like whether it is profitable to turn
416 division by a constant into a multiplication sequence</li>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]417</ul>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]418
419</div>
420
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]421<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]422<h3>
Dan Gohman3a4be0f2008-02-10 18:45:23 +0000[diff] [blame]423 <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]424</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]425
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]426<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]427
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]428<p>The <tt>TargetRegisterInfo</tt> class is used to describe the register file
429 of the target and any interactions between the registers.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]430
431<p>Registers in the code generator are represented in the code generator by
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]432 unsigned integers. Physical registers (those that actually exist in the
433 target description) are unique small numbers, and virtual registers are
434 generally large. Note that register #0 is reserved as a flag value.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]435
436<p>Each register in the processor description has an associated
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]437 <tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
438 register (used for assembly output and debugging dumps) and a set of aliases
439 (used to indicate whether one register overlaps with another).</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]440
Dan Gohman3a4be0f2008-02-10 18:45:23 +0000[diff] [blame]441<p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]442 class exposes a set of processor specific register classes (instances of the
443 <tt>TargetRegisterClass</tt> class). Each register class contains sets of
444 registers that have the same properties (for example, they are all 32-bit
445 integer registers). Each SSA virtual register created by the instruction
446 selector has an associated register class. When the register allocator runs,
447 it replaces virtual registers with a physical register in the set.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]448
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]449<p>The target-specific implementations of these classes is auto-generated from
450 a <a href="TableGenFundamentals.html">TableGen</a> description of the
451 register file.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]452
453</div>
454
455<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]456<h3>
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]457 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]458</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]459
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]460<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]461
462<p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
463 instructions supported by the target. It is essentially an array of
464 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
465 instruction the target supports. Descriptors define things like the mnemonic
466 for the opcode, the number of operands, the list of implicit register uses
467 and defs, whether the instruction has certain target-independent properties
468 (accesses memory, is commutable, etc), and holds any target-specific
469 flags.</p>
470
Reid Spencere5dc84b2005-07-19 01:36:35 +0000[diff] [blame]471</div>
472
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]473<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]474<h3>
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]475 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]476</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]477
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]478<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]479
480<p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
481 stack frame layout of the target. It holds the direction of stack growth, the
482 known stack alignment on entry to each function, and the offset to the local
483 area. The offset to the local area is the offset from the stack pointer on
484 function entry to the first location where function data (local variables,
485 spill locations) can be stored.</p>
486
Reid Spencere5dc84b2005-07-19 01:36:35 +0000[diff] [blame]487</div>
Chris Lattnerc9afa282005-10-16 17:06:07 +0000[diff] [blame]488
489<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]490<h3>
Chris Lattnerc9afa282005-10-16 17:06:07 +0000[diff] [blame]491 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]492</h3>
Chris Lattnerc9afa282005-10-16 17:06:07 +0000[diff] [blame]493
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]494<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]495
496<p>The <tt>TargetSubtarget</tt> class is used to provide information about the
497 specific chip set being targeted. A sub-target informs code generation of
498 which instructions are supported, instruction latencies and instruction
499 execution itinerary; i.e., which processing units are used, in what order,
500 and for how long.</p>
501
Chris Lattnerc9afa282005-10-16 17:06:07 +0000[diff] [blame]502</div>
503
504
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]505<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]506<h3>
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]507 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]508</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]509
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]510<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]511
512<p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
513 Just-In-Time code generator to perform target-specific activities, such as
514 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
515 should provide one of these objects through the <tt>getJITInfo</tt>
516 method.</p>
517
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]518</div>
519
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]520</div>
521
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]522<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]523<h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]524 <a name="codegendesc">Machine code description classes</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]525</h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]526<!-- *********************************************************************** -->
527
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]528<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]529
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]530<p>At the high-level, LLVM code is translated to a machine specific
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]531 representation formed out of
532 <a href="#machinefunction"><tt>MachineFunction</tt></a>,
533 <a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>,
534 and <a href="#machineinstr"><tt>MachineInstr</tt></a> instances (defined
535 in <tt>include/llvm/CodeGen</tt>). This representation is completely target
536 agnostic, representing instructions in their most abstract form: an opcode
537 and a series of operands. This representation is designed to support both an
538 SSA representation for machine code, as well as a register allocated, non-SSA
539 form.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]540
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]541<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]542<h3>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]543 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]544</h3>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]545
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]546<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]547
548<p>Target machine instructions are represented as instances of the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]549 <tt>MachineInstr</tt> class. This class is an extremely abstract way of
550 representing machine instructions. In particular, it only keeps track of an
551 opcode number and a set of operands.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]552
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]553<p>The opcode number is a simple unsigned integer that only has meaning to a
554 specific backend. All of the instructions for a target should be defined in
555 the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values are
556 auto-generated from this description. The <tt>MachineInstr</tt> class does
557 not have any information about how to interpret the instruction (i.e., what
558 the semantics of the instruction are); for that you must refer to the
559 <tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]560
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]561<p>The operands of a machine instruction can be of several different types: a
562 register reference, a constant integer, a basic block reference, etc. In
563 addition, a machine operand should be marked as a def or a use of the value
564 (though only registers are allowed to be defs).</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]565
566<p>By convention, the LLVM code generator orders instruction operands so that
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]567 all register definitions come before the register uses, even on architectures
568 that are normally printed in other orders. For example, the SPARC add
569 instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
570 and stores the result into the "%i3" register. In the LLVM code generator,
571 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the
572 destination first.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]573
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]574<p>Keeping destination (definition) operands at the beginning of the operand
575 list has several advantages. In particular, the debugging printer will print
576 the instruction like this:</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]577
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]578<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]579<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]580%r3 = add %i1, %i2
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]581</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]582</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]583
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]584<p>Also if the first operand is a def, it is easier to <a href="#buildmi">create
585 instructions</a> whose only def is the first operand.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]586
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]587<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]588<h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]589 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]590</h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]591
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]592<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]593
594<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]595 located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
596 <tt>BuildMI</tt> functions make it easy to build arbitrary machine
597 instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]598
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]599<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]600<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]601// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
602// instruction. The '1' specifies how many operands will be added.
603MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]604
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]605// Create the same instr, but insert it at the end of a basic block.
606MachineBasicBlock &amp;MBB = ...
607BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]608
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]609// Create the same instr, but insert it before a specified iterator point.
610MachineBasicBlock::iterator MBBI = ...
611BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]612
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]613// Create a 'cmp Reg, 0' instruction, no destination reg.
614MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
615// Create an 'sahf' instruction which takes no operands and stores nothing.
616MI = BuildMI(X86::SAHF, 0);
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]617
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]618// Create a self looping branch instruction.
619BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]620</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]621</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]622
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]623<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]624 have to specify the number of operands that the machine instruction will
625 take. This allows for efficient memory allocation. You also need to specify
626 if operands default to be uses of values, not definitions. If you need to
627 add a definition operand (other than the optional destination register), you
628 must explicitly mark it as such:</p>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]629
630<div class="doc_code">
631<pre>
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]632MI.addReg(Reg, RegState::Define);
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]633</pre>
634</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]635
636</div>
637
638<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]639<h4>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]640 <a name="fixedregs">Fixed (preassigned) registers</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]641</h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]642
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]643<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]644
645<p>One important issue that the code generator needs to be aware of is the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]646 presence of fixed registers. In particular, there are often places in the
647 instruction stream where the register allocator <em>must</em> arrange for a
648 particular value to be in a particular register. This can occur due to
649 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
650 with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like
651 calling conventions. In any case, the instruction selector should emit code
652 that copies a virtual register into or out of a physical register when
653 needed.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]654
655<p>For example, consider this simple LLVM example:</p>
656
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]657<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]658<pre>
Matthijs Kooijmana6bb22e2008-06-04 15:46:35 +0000[diff] [blame]659define i32 @test(i32 %X, i32 %Y) {
660 %Z = udiv i32 %X, %Y
661 ret i32 %Z
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]662}
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]663</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]664</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]665
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]666<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]667 and <tt>ret</tt> (use "<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to
668 get this):</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]669
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]670<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]671<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]672;; Start of div
673%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
674%reg1027 = sar %reg1024, 31
675%EDX = mov %reg1027 ;; Sign extend X into EDX
676idiv %reg1025 ;; Divide by Y (in reg1025)
677%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]678
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]679;; Start of ret
680%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
681ret
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]682</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]683</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]684
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]685<p>By the end of code generation, the register allocator has coalesced the
686 registers and deleted the resultant identity moves producing the following
687 code:</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]688
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]689<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]690<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]691;; X is in EAX, Y is in ECX
692mov %EAX, %EDX
693sar %EDX, 31
694idiv %ECX
695ret
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]696</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]697</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]698
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]699<p>This approach is extremely general (if it can handle the X86 architecture, it
700 can handle anything!) and allows all of the target specific knowledge about
701 the instruction stream to be isolated in the instruction selector. Note that
702 physical registers should have a short lifetime for good code generation, and
703 all physical registers are assumed dead on entry to and exit from basic
704 blocks (before register allocation). Thus, if you need a value to be live
705 across basic block boundaries, it <em>must</em> live in a virtual
706 register.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]707
708</div>
709
710<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]711<h4>
Jakob Stoklund Olesen374ed322012-01-16 19:22:00 +0000[diff] [blame]712 <a name="callclobber">Call-clobbered registers</a>
713</h4>
714
715<div>
716
717<p>Some machine instructions, like calls, clobber a large number of physical
718 registers. Rather than adding <code>&lt;def,dead&gt;</code> operands for
719 all of them, it is possible to use an <code>MO_RegisterMask</code> operand
720 instead. The register mask operand holds a bit mask of preserved registers,
721 and everything else is considered to be clobbered by the instruction. </p>
722
723</div>
724
725<!-- _______________________________________________________________________ -->
726<h4>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]727 <a name="ssa">Machine code in SSA form</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]728</h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]729
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]730<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]731
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]732<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and are
733 maintained in SSA-form until register allocation happens. For the most part,
734 this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
735 become machine code PHI nodes, and virtual registers are only allowed to have
736 a single definition.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]737
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]738<p>After register allocation, machine code is no longer in SSA-form because
739 there are no virtual registers left in the code.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]740
741</div>
742
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]743</div>
744
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]745<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]746<h3>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]747 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]748</h3>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]749
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]750<div>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]751
752<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]753 (<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
754 corresponds to the LLVM code input to the instruction selector, but there can
755 be a one-to-many mapping (i.e. one LLVM basic block can map to multiple
756 machine basic blocks). The <tt>MachineBasicBlock</tt> class has a
757 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
758 comes from.</p>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]759
760</div>
761
762<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]763<h3>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]764 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]765</h3>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]766
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]767<div>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]768
769<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]770 (<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
771 corresponds one-to-one with the LLVM function input to the instruction
772 selector. In addition to a list of basic blocks,
773 the <tt>MachineFunction</tt> contains a a <tt>MachineConstantPool</tt>,
774 a <tt>MachineFrameInfo</tt>, a <tt>MachineFunctionInfo</tt>, and a
775 <tt>MachineRegisterInfo</tt>. See
776 <tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]777
778</div>
779
Evan Chengc984bf82011-12-14 21:32:14 +0000[diff] [blame]780<!-- ======================================================================= -->
781<h3>
782 <a name="machineinstrbundle"><tt>MachineInstr Bundles</tt></a>
783</h3>
784
785<div>
786
787<p>LLVM code generator can model sequences of instructions as MachineInstr
788 bundles. A MI bundle can model a VLIW group / pack which contains an
789 arbitrary number of parallel instructions. It can also be used to model
790 a sequential list of instructions (potentially with data dependencies) that
791 cannot be legally separated (e.g. ARM Thumb2 IT blocks).</p>
792
793<p>Conceptually a MI bundle is a MI with a number of other MIs nested within:
794</p>
795
796<div class="doc_code">
797<pre>
798--------------
799| Bundle | ---------
800-------------- \
801 | ----------------
802 | | MI |
803 | ----------------
804 | |
805 | ----------------
806 | | MI |
807 | ----------------
808 | |
809 | ----------------
810 | | MI |
811 | ----------------
812 |
813--------------
814| Bundle | --------
815-------------- \
816 | ----------------
817 | | MI |
818 | ----------------
819 | |
820 | ----------------
821 | | MI |
822 | ----------------
823 | |
824 | ...
825 |
826--------------
827| Bundle | --------
828-------------- \
829 |
830 ...
831</pre>
832</div>
833
834<p> MI bundle support does not change the physical representations of
835 MachineBasicBlock and MachineInstr. All the MIs (including top level and
836 nested ones) are stored as sequential list of MIs. The "bundled" MIs are
837 marked with the 'InsideBundle' flag. A top level MI with the special BUNDLE
838 opcode is used to represent the start of a bundle. It's legal to mix BUNDLE
839 MIs with indiviual MIs that are not inside bundles nor represent bundles.
840</p>
841
842<p> MachineInstr passes should operate on a MI bundle as a single unit. Member
843 methods have been taught to correctly handle bundles and MIs inside bundles.
844 The MachineBasicBlock iterator has been modified to skip over bundled MIs to
845 enforce the bundle-as-a-single-unit concept. An alternative iterator
846 instr_iterator has been added to MachineBasicBlock to allow passes to
847 iterate over all of the MIs in a MachineBasicBlock, including those which
848 are nested inside bundles. The top level BUNDLE instruction must have the
849 correct set of register MachineOperand's that represent the cumulative
850 inputs and outputs of the bundled MIs.</p>
851
852<p> Packing / bundling of MachineInstr's should be done as part of the register
853 allocation super-pass. More specifically, the pass which determines what
854 MIs should be bundled together must be done after code generator exits SSA
855 form (i.e. after two-address pass, PHI elimination, and copy coalescing).
856 Bundles should only be finalized (i.e. adding BUNDLE MIs and input and
857 output register MachineOperands) after virtual registers have been
858 rewritten into physical registers. This requirement eliminates the need to
859 add virtual register operands to BUNDLE instructions which would effectively
860 double the virtual register def and use lists.</p>
861
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]862</div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]863
864<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]865<h2>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]866 <a name="mc">The "MC" Layer</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]867</h2>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]868<!-- *********************************************************************** -->
869
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]870<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]871
872<p>
873The MC Layer is used to represent and process code at the raw machine code
874level, devoid of "high level" information like "constant pools", "jump tables",
875"global variables" or anything like that. At this level, LLVM handles things
876like label names, machine instructions, and sections in the object file. The
877code in this layer is used for a number of important purposes: the tail end of
878the code generator uses it to write a .s or .o file, and it is also used by the
Jay Foadfdb9f6a2011-04-13 13:03:56 +0000[diff] [blame]879llvm-mc tool to implement standalone machine code assemblers and disassemblers.
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]880</p>
881
882<p>
883This section describes some of the important classes. There are also a number
884of important subsystems that interact at this layer, they are described later
885in this manual.
886</p>
887
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]888<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]889<h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]890 <a name="mcstreamer">The <tt>MCStreamer</tt> API</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]891</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]892
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]893<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]894
895<p>
896MCStreamer is best thought of as an assembler API. It is an abstract API which
897is <em>implemented</em> in different ways (e.g. to output a .s file, output an
898ELF .o file, etc) but whose API correspond directly to what you see in a .s
899file. MCStreamer has one method per directive, such as EmitLabel,
900EmitSymbolAttribute, SwitchSection, EmitValue (for .byte, .word), etc, which
901directly correspond to assembly level directives. It also has an
902EmitInstruction method, which is used to output an MCInst to the streamer.
903</p>
904
905<p>
906This API is most important for two clients: the llvm-mc stand-alone assembler is
907effectively a parser that parses a line, then invokes a method on MCStreamer. In
908the code generator, the <a href="#codeemit">Code Emission</a> phase of the code
909generator lowers higher level LLVM IR and Machine* constructs down to the MC
910layer, emitting directives through MCStreamer.</p>
911
912<p>
913On the implementation side of MCStreamer, there are two major implementations:
914one for writing out a .s file (MCAsmStreamer), and one for writing out a .o
915file (MCObjectStreamer). MCAsmStreamer is a straight-forward implementation
916that prints out a directive for each method (e.g. EmitValue -&gt; .byte), but
917MCObjectStreamer implements a full assembler.
918</p>
919
920</div>
921
922<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]923<h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]924 <a name="mccontext">The <tt>MCContext</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]925</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]926
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]927<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]928
929<p>
930The MCContext class is the owner of a variety of uniqued data structures at the
931MC layer, including symbols, sections, etc. As such, this is the class that you
932interact with to create symbols and sections. This class can not be subclassed.
933</p>
934
935</div>
936
937<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]938<h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]939 <a name="mcsymbol">The <tt>MCSymbol</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]940</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]941
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]942<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]943
944<p>
945The MCSymbol class represents a symbol (aka label) in the assembly file. There
946are two interesting kinds of symbols: assembler temporary symbols, and normal
947symbols. Assembler temporary symbols are used and processed by the assembler
948but are discarded when the object file is produced. The distinction is usually
949represented by adding a prefix to the label, for example "L" labels are
950assembler temporary labels in MachO.
951</p>
952
953<p>MCSymbols are created by MCContext and uniqued there. This means that
954MCSymbols can be compared for pointer equivalence to find out if they are the
955same symbol. Note that pointer inequality does not guarantee the labels will
956end up at different addresses though. It's perfectly legal to output something
957like this to the .s file:<p>
958
959<pre>
960 foo:
961 bar:
962 .byte 4
963</pre>
964
965<p>In this case, both the foo and bar symbols will have the same address.</p>
966
967</div>
968
969<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]970<h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]971 <a name="mcsection">The <tt>MCSection</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]972</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]973
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]974<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]975
976<p>
977The MCSection class represents an object-file specific section. It is subclassed
978by object file specific implementations (e.g. <tt>MCSectionMachO</tt>,
979<tt>MCSectionCOFF</tt>, <tt>MCSectionELF</tt>) and these are created and uniqued
980by MCContext. The MCStreamer has a notion of the current section, which can be
981changed with the SwitchToSection method (which corresponds to a ".section"
982directive in a .s file).
983</p>
984
985</div>
986
987<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]988<h3>
Benjamin Kramerc940bcf2010-10-30 21:07:28 +0000[diff] [blame]989 <a name="mcinst">The <tt>MCInst</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]990</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]991
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]992<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]993
994<p>
995The MCInst class is a target-independent representation of an instruction. It
996is a simple class (much more so than <a href="#machineinstr">MachineInstr</a>)
997that holds a target-specific opcode and a vector of MCOperands. MCOperand, in
998turn, is a simple discriminated union of three cases: 1) a simple immediate,
9992) a target register ID, 3) a symbolic expression (e.g. "Lfoo-Lbar+42") as an
1000MCExpr.
1001</p>
1002
1003<p>MCInst is the common currency used to represent machine instructions at the
1004MC layer. It is the type used by the instruction encoder, the instruction
1005printer, and the type generated by the assembly parser and disassembler.
1006</p>
1007
1008</div>
1009
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1010</div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]1011
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]1012<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1013<h2>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1014 <a name="codegenalgs">Target-independent code generation algorithms</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1015</h2>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1016<!-- *********************************************************************** -->
1017
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1018<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1019
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1020<p>This section documents the phases described in the
1021 <a href="#high-level-design">high-level design of the code generator</a>.
1022 It explains how they work and some of the rationale behind their design.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1023
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1024<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1025<h3>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1026 <a name="instselect">Instruction Selection</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1027</h3>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1028
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1029<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1030
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1031<p>Instruction Selection is the process of translating LLVM code presented to
1032 the code generator into target-specific machine instructions. There are
1033 several well-known ways to do this in the literature. LLVM uses a
1034 SelectionDAG based instruction selector.</p>
1035
1036<p>Portions of the DAG instruction selector are generated from the target
1037 description (<tt>*.td</tt>) files. Our goal is for the entire instruction
1038 selector to be generated from these <tt>.td</tt> files, though currently
1039 there are still things that require custom C++ code.</p>
1040
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1041<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1042<h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1043 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1044</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1045
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1046<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1047
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1048<p>The SelectionDAG provides an abstraction for code representation in a way
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1049 that is amenable to instruction selection using automatic techniques
1050 (e.g. dynamic-programming based optimal pattern matching selectors). It is
1051 also well-suited to other phases of code generation; in particular,
1052 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
1053 post-selection). Additionally, the SelectionDAG provides a host
1054 representation where a large variety of very-low-level (but
1055 target-independent) <a href="#selectiondag_optimize">optimizations</a> may be
1056 performed; ones which require extensive information about the instructions
1057 efficiently supported by the target.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1058
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1059<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1060 <tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
1061 operation code (Opcode) that indicates what operation the node performs and
1062 the operands to the operation. The various operation node types are
1063 described at the top of the <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>
1064 file.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1065
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1066<p>Although most operations define a single value, each node in the graph may
1067 define multiple values. For example, a combined div/rem operation will
1068 define both the dividend and the remainder. Many other situations require
1069 multiple values as well. Each node also has some number of operands, which
1070 are edges to the node defining the used value. Because nodes may define
1071 multiple values, edges are represented by instances of the <tt>SDValue</tt>
1072 class, which is a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node
1073 and result value being used, respectively. Each value produced by
1074 an <tt>SDNode</tt> has an associated <tt>MVT</tt> (Machine Value Type)
1075 indicating what the type of the value is.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1076
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1077<p>SelectionDAGs contain two different kinds of values: those that represent
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1078 data flow and those that represent control flow dependencies. Data values
1079 are simple edges with an integer or floating point value type. Control edges
1080 are represented as "chain" edges which are of type <tt>MVT::Other</tt>.
1081 These edges provide an ordering between nodes that have side effects (such as
1082 loads, stores, calls, returns, etc). All nodes that have side effects should
1083 take a token chain as input and produce a new one as output. By convention,
1084 token chain inputs are always operand #0, and chain results are always the
1085 last value produced by an operation.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1086
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1087<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1088 always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root
1089 node is the final side-effecting node in the token chain. For example, in a
1090 single basic block function it would be the return node.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1091
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1092<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1093 "illegal" DAG. A legal DAG for a target is one that only uses supported
1094 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
1095 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that
1096 uses a SREM or UREM operation. The
1097 <a href="#selectinodag_legalize_types">legalize types</a> and
1098 <a href="#selectiondag_legalize">legalize operations</a> phases are
1099 responsible for turning an illegal DAG into a legal DAG.</p>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1100
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1101</div>
1102
1103<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1104<h4>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1105 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1106</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1107
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1108<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1109
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1110<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1111
1112<ol>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1113 <li><a href="#selectiondag_build">Build initial DAG</a> &mdash; This stage
1114 performs a simple translation from the input LLVM code to an illegal
1115 SelectionDAG.</li>
1116
1117 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; This
1118 stage performs simple optimizations on the SelectionDAG to simplify it,
1119 and recognize meta instructions (like rotates
1120 and <tt>div</tt>/<tt>rem</tt> pairs) for targets that support these meta
1121 operations. This makes the resultant code more efficient and
1122 the <a href="#selectiondag_select">select instructions from DAG</a> phase
1123 (below) simpler.</li>
1124
1125 <li><a href="#selectiondag_legalize_types">Legalize SelectionDAG Types</a>
1126 &mdash; This stage transforms SelectionDAG nodes to eliminate any types
1127 that are unsupported on the target.</li>
1128
1129 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
1130 SelectionDAG optimizer is run to clean up redundancies exposed by type
1131 legalization.</li>
1132
Chris Lattner053a0252010-12-12 02:42:57 +0000[diff] [blame]1133 <li><a href="#selectiondag_legalize">Legalize SelectionDAG Ops</a> &mdash;
Chris Lattnerbd614442010-12-13 00:17:12 +0000[diff] [blame]1134 This stage transforms SelectionDAG nodes to eliminate any operations
1135 that are unsupported on the target.</li>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1136
1137 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
1138 SelectionDAG optimizer is run to eliminate inefficiencies introduced by
1139 operation legalization.</li>
1140
1141 <li><a href="#selectiondag_select">Select instructions from DAG</a> &mdash;
1142 Finally, the target instruction selector matches the DAG operations to
1143 target instructions. This process translates the target-independent input
1144 DAG into another DAG of target instructions.</li>
1145
1146 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
1147 &mdash; The last phase assigns a linear order to the instructions in the
1148 target-instruction DAG and emits them into the MachineFunction being
1149 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1150</ol>
1151
1152<p>After all of these steps are complete, the SelectionDAG is destroyed and the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1153 rest of the code generation passes are run.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1154
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1155<p>One great way to visualize what is going on here is to take advantage of a
1156 few LLC command line options. The following options pop up a window
1157 displaying the SelectionDAG at specific times (if you only get errors printed
1158 to the console while using this, you probably
1159 <a href="ProgrammersManual.html#ViewGraph">need to configure your system</a>
1160 to add support for it).</p>
Dan Gohmandd51d522008-09-10 22:23:41 +0000[diff] [blame]1161
1162<ul>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1163 <li><tt>-view-dag-combine1-dags</tt> displays the DAG after being built,
1164 before the first optimization pass.</li>
1165
1166 <li><tt>-view-legalize-dags</tt> displays the DAG before Legalization.</li>
1167
1168 <li><tt>-view-dag-combine2-dags</tt> displays the DAG before the second
1169 optimization pass.</li>
1170
1171 <li><tt>-view-isel-dags</tt> displays the DAG before the Select phase.</li>
1172
1173 <li><tt>-view-sched-dags</tt> displays the DAG before Scheduling.</li>
Dan Gohmandd51d522008-09-10 22:23:41 +0000[diff] [blame]1174</ul>
1175
1176<p>The <tt>-view-sunit-dags</tt> displays the Scheduler's dependency graph.
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1177 This graph is based on the final SelectionDAG, with nodes that must be
1178 scheduled together bundled into a single scheduling-unit node, and with
1179 immediate operands and other nodes that aren't relevant for scheduling
1180 omitted.</p>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1181
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1182</div>
1183
1184<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1185<h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1186 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1187</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1188
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1189<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1190
Bill Wendling6737f5d2006-08-28 03:04:05 +0000[diff] [blame]1191<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1192 input by the <tt>SelectionDAGLowering</tt> class in the
1193 <tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of
1194 this pass is to expose as much low-level, target-specific details to the
1195 SelectionDAG as possible. This pass is mostly hard-coded (e.g. an
1196 LLVM <tt>add</tt> turns into an <tt>SDNode add</tt> while a
1197 <tt>getelementptr</tt> is expanded into the obvious arithmetic). This pass
1198 requires target-specific hooks to lower calls, returns, varargs, etc. For
1199 these features, the <tt><a href="#targetlowering">TargetLowering</a></tt>
1200 interface is used.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1201
1202</div>
1203
1204<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1205<h4>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1206 <a name="selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1207</h4>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1208
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1209<div>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1210
1211<p>The Legalize phase is in charge of converting a DAG to only use the types
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1212 that are natively supported by the target.</p>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1213
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1214<p>There are two main ways of converting values of unsupported scalar types to
1215 values of supported types: converting small types to larger types
1216 ("promoting"), and breaking up large integer types into smaller ones
1217 ("expanding"). For example, a target might require that all f32 values are
1218 promoted to f64 and that all i1/i8/i16 values are promoted to i32. The same
1219 target might require that all i64 values be expanded into pairs of i32
1220 values. These changes can insert sign and zero extensions as needed to make
1221 sure that the final code has the same behavior as the input.</p>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1222
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1223<p>There are two main ways of converting values of unsupported vector types to
1224 value of supported types: splitting vector types, multiple times if
1225 necessary, until a legal type is found, and extending vector types by adding
1226 elements to the end to round them out to legal types ("widening"). If a
1227 vector gets split all the way down to single-element parts with no supported
1228 vector type being found, the elements are converted to scalars
1229 ("scalarizing").</p>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1230
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1231<p>A target implementation tells the legalizer which types are supported (and
1232 which register class to use for them) by calling the
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1233 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
1234
1235</div>
1236
1237<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1238<h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1239 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1240</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1241
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1242<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1243
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1244<p>The Legalize phase is in charge of converting a DAG to only use the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1245 operations that are natively supported by the target.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1246
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1247<p>Targets often have weird constraints, such as not supporting every operation
1248 on every supported datatype (e.g. X86 does not support byte conditional moves
1249 and PowerPC does not support sign-extending loads from a 16-bit memory
1250 location). Legalize takes care of this by open-coding another sequence of
1251 operations to emulate the operation ("expansion"), by promoting one type to a
1252 larger type that supports the operation ("promotion"), or by using a
1253 target-specific hook to implement the legalization ("custom").</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1254
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1255<p>A target implementation tells the legalizer which operations are not
1256 supported (and which of the above three actions to take) by calling the
1257 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
1258 constructor.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1259
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1260<p>Prior to the existence of the Legalize passes, we required that every target
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1261 <a href="#selectiondag_optimize">selector</a> supported and handled every
1262 operator and type even if they are not natively supported. The introduction
1263 of the Legalize phases allows all of the canonicalization patterns to be
1264 shared across targets, and makes it very easy to optimize the canonicalized
1265 code because it is still in the form of a DAG.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1266
1267</div>
1268
1269<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1270<h4>
1271 <a name="selectiondag_optimize">
1272 SelectionDAG Optimization Phase: the DAG Combiner
1273 </a>
1274</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1275
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1276<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1277
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1278<p>The SelectionDAG optimization phase is run multiple times for code
1279 generation, immediately after the DAG is built and once after each
1280 legalization. The first run of the pass allows the initial code to be
1281 cleaned up (e.g. performing optimizations that depend on knowing that the
1282 operators have restricted type inputs). Subsequent runs of the pass clean up
1283 the messy code generated by the Legalize passes, which allows Legalize to be
1284 very simple (it can focus on making code legal instead of focusing on
1285 generating <em>good</em> and legal code).</p>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1286
1287<p>One important class of optimizations performed is optimizing inserted sign
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1288 and zero extension instructions. We currently use ad-hoc techniques, but
1289 could move to more rigorous techniques in the future. Here are some good
1290 papers on the subject:</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1291
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1292<p>"<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
1293 integer arithmetic</a>"<br>
1294 Kevin Redwine and Norman Ramsey<br>
1295 International Conference on Compiler Construction (CC) 2004</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1296
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1297<p>"<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
1298 sign extension elimination</a>"<br>
1299 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1300 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1301 and Implementation.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1302
1303</div>
1304
1305<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1306<h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1307 <a name="selectiondag_select">SelectionDAG Select Phase</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1308</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1309
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1310<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1311
1312<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1313 selection. This phase takes a legal SelectionDAG as input, pattern matches
1314 the instructions supported by the target to this DAG, and produces a new DAG
1315 of target code. For example, consider the following LLVM fragment:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1316
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1317<div class="doc_code">
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1318<pre>
Dan Gohman6f34abd2010-03-02 01:11:08 +0000[diff] [blame]1319%t1 = fadd float %W, %X
1320%t2 = fmul float %t1, %Y
1321%t3 = fadd float %t2, %Z
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1322</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1323</div>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1324
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1325<p>This LLVM code corresponds to a SelectionDAG that looks basically like
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1326 this:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1327
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1328<div class="doc_code">
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1329<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1330(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1331</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1332</div>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1333
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1334<p>If a target supports floating point multiply-and-add (FMA) operations, one of
1335 the adds can be merged with the multiply. On the PowerPC, for example, the
1336 output of the instruction selector might look like this DAG:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1337
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1338<div class="doc_code">
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1339<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1340(FMADDS (FADDS W, X), Y, Z)
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1341</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1342</div>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1343
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1344<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1345first two operands and adds the third (as single-precision floating-point
1346numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1347add instruction. To perform this pattern match, the PowerPC backend includes
1348the following instruction definitions:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1349
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1350<div class="doc_code">
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1351<pre>
1352def FMADDS : AForm_1&lt;59, 29,
1353 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1354 "fmadds $FRT, $FRA, $FRC, $FRB",
1355 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1356 F4RC:$FRB))</b>]&gt;;
1357def FADDS : AForm_2&lt;59, 21,
1358 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1359 "fadds $FRT, $FRA, $FRB",
1360 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1361</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1362</div>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1363
1364<p>The portion of the instruction definition in bold indicates the pattern used
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1365 to match the instruction. The DAG operators
1366 (like <tt>fmul</tt>/<tt>fadd</tt>) are defined in
Dan Gohman2a020352010-03-25 00:03:04 +0000[diff] [blame]1367 the <tt>include/llvm/Target/TargetSelectionDAG.td</tt> file. "
1368 <tt>F4RC</tt>" is the register class of the input and result values.</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1369
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1370<p>The TableGen DAG instruction selector generator reads the instruction
1371 patterns in the <tt>.td</tt> file and automatically builds parts of the
1372 pattern matching code for your target. It has the following strengths:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1373
1374<ul>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1375 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1376 you if your patterns make sense or not.</li>
1377
1378 <li>It can handle arbitrary constraints on operands for the pattern match. In
1379 particular, it is straight-forward to say things like "match any immediate
1380 that is a 13-bit sign-extended value". For examples, see the
1381 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1382 backend.</li>
1383
1384 <li>It knows several important identities for the patterns defined. For
1385 example, it knows that addition is commutative, so it allows the
1386 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1387 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1388 to specially handle this case.</li>
1389
1390 <li>It has a full-featured type-inferencing system. In particular, you should
1391 rarely have to explicitly tell the system what type parts of your patterns
1392 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1393 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'.
1394 It was able to infer and propagate this knowledge from the fact that
1395 <tt>F4RC</tt> has type 'f32'.</li>
1396
1397 <li>Targets can define their own (and rely on built-in) "pattern fragments".
1398 Pattern fragments are chunks of reusable patterns that get inlined into
1399 your patterns during compiler-compiler time. For example, the integer
1400 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment
1401 that expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not
1402 have a native '<tt>not</tt>' operation. Targets can define their own
1403 short-hand fragments as they see fit. See the definition of
1404 '<tt>not</tt>' and '<tt>ineg</tt>' for examples.</li>
1405
1406 <li>In addition to instructions, targets can specify arbitrary patterns that
1407 map to one or more instructions using the 'Pat' class. For example, the
1408 PowerPC has no way to load an arbitrary integer immediate into a register
1409 in one instruction. To tell tblgen how to do this, it defines:
1410 <br>
1411 <br>
1412<div class="doc_code">
1413<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1414// Arbitrary immediate support. Implement in terms of LIS/ORI.
1415def : Pat&lt;(i32 imm:$imm),
1416 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1417</pre>
1418</div>
1419 <br>
1420 If none of the single-instruction patterns for loading an immediate into a
1421 register match, this will be used. This rule says "match an arbitrary i32
1422 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and
1423 an <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to
1424 the left 16 bits') instruction". To make this work, the
1425 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate
1426 the input immediate (in this case, take the high or low 16-bits of the
1427 immediate).</li>
1428
1429 <li>While the system does automate a lot, it still allows you to write custom
1430 C++ code to match special cases if there is something that is hard to
1431 express.</li>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1432</ul>
1433
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1434<p>While it has many strengths, the system currently has some limitations,
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1435 primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1436
1437<ul>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1438 <li>Overall, there is no way to define or match SelectionDAG nodes that define
Dan Gohmana4fea5b2009-04-22 15:55:31 +0000[diff] [blame]1439 multiple values (e.g. <tt>SMUL_LOHI</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1440 etc). This is the biggest reason that you currently still <em>have
1441 to</em> write custom C++ code for your instruction selector.</li>
1442
1443 <li>There is no great way to support matching complex addressing modes yet.
1444 In the future, we will extend pattern fragments to allow them to define
1445 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1446 addressing mode</a>, which are currently matched with custom C++ code).
1447 In addition, we'll extend fragments so that a fragment can match multiple
1448 different patterns.</li>
1449
1450 <li>We don't automatically infer flags like isStore/isLoad yet.</li>
1451
1452 <li>We don't automatically generate the set of supported registers and
1453 operations for the <a href="#selectiondag_legalize">Legalizer</a>
1454 yet.</li>
1455
1456 <li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner721f3ce2005-10-17 04:18:41 +0000[diff] [blame]1457</ul>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1458
1459<p>Despite these limitations, the instruction selector generator is still quite
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1460 useful for most of the binary and logical operations in typical instruction
1461 sets. If you run into any problems or can't figure out how to do something,
1462 please let Chris know!</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1463
1464</div>
1465
1466<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1467<h4>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]1468 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1469</h4>
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]1470
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1471<div>
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]1472
1473<p>The scheduling phase takes the DAG of target instructions from the selection
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1474 phase and assigns an order. The scheduler can pick an order depending on
1475 various constraints of the machines (i.e. order for minimal register pressure
1476 or try to cover instruction latencies). Once an order is established, the
1477 DAG is converted to a list
1478 of <tt><a href="#machineinstr">MachineInstr</a></tt>s and the SelectionDAG is
1479 destroyed.</p>
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]1480
Jeff Cohendd24d7c2005-10-24 16:54:55 +0000[diff] [blame]1481<p>Note that this phase is logically separate from the instruction selection
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1482 phase, but is tied to it closely in the code because it operates on
1483 SelectionDAGs.</p>
Chris Lattner9fcf0002005-10-17 03:09:31 +0000[diff] [blame]1484
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]1485</div>
1486
1487<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1488<h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1489 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1490</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1491
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1492<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1493
1494<ol>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1495 <li>Optional function-at-a-time selection.</li>
1496
1497 <li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1498</ol>
1499
1500</div>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1501
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1502</div>
1503
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1504<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1505<h3>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1506 <a name="ssamco">SSA-based Machine Code Optimizations</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1507</h3>
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1508<div><p>To Be Written</p></div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1509
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1510<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1511<h3>
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]1512 <a name="liveintervals">Live Intervals</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1513</h3>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1514
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1515<div>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1516
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]1517<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1518 They are used by some <a href="#regalloc">register allocator</a> passes to
1519 determine if two or more virtual registers which require the same physical
1520 register are live at the same point in the program (i.e., they conflict).
1521 When this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1522
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1523<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1524<h4>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1525 <a name="livevariable_analysis">Live Variable Analysis</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1526</h4>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1527
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1528<div>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1529
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1530<p>The first step in determining the live intervals of variables is to calculate
1531 the set of registers that are immediately dead after the instruction (i.e.,
1532 the instruction calculates the value, but it is never used) and the set of
1533 registers that are used by the instruction, but are never used after the
1534 instruction (i.e., they are killed). Live variable information is computed
1535 for each <i>virtual</i> register and <i>register allocatable</i> physical
1536 register in the function. This is done in a very efficient manner because it
1537 uses SSA to sparsely compute lifetime information for virtual registers
1538 (which are in SSA form) and only has to track physical registers within a
1539 block. Before register allocation, LLVM can assume that physical registers
1540 are only live within a single basic block. This allows it to do a single,
1541 local analysis to resolve physical register lifetimes within each basic
1542 block. If a physical register is not register allocatable (e.g., a stack
1543 pointer or condition codes), it is not tracked.</p>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1544
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1545<p>Physical registers may be live in to or out of a function. Live in values are
1546 typically arguments in registers. Live out values are typically return values
1547 in registers. Live in values are marked as such, and are given a dummy
1548 "defining" instruction during live intervals analysis. If the last basic
1549 block of a function is a <tt>return</tt>, then it's marked as using all live
1550 out values in the function.</p>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1551
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1552<p><tt>PHI</tt> nodes need to be handled specially, because the calculation of
1553 the live variable information from a depth first traversal of the CFG of the
1554 function won't guarantee that a virtual register used by the <tt>PHI</tt>
1555 node is defined before it's used. When a <tt>PHI</tt> node is encountered,
1556 only the definition is handled, because the uses will be handled in other
1557 basic blocks.</p>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1558
1559<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1560 assignment at the end of the current basic block and traverse the successor
1561 basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1562 the <tt>PHI</tt> node's operands is coming from the current basic block, then
1563 the variable is marked as <i>alive</i> within the current basic block and all
1564 of its predecessor basic blocks, until the basic block with the defining
1565 instruction is encountered.</p>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1566
1567</div>
1568
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]1569<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1570<h4>
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]1571 <a name="liveintervals_analysis">Live Intervals Analysis</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1572</h4>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1573
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1574<div>
Bill Wendling34ab0672006-10-11 06:30:10 +0000[diff] [blame]1575
Bill Wendlingf21825f2006-10-11 18:00:22 +0000[diff] [blame]1576<p>We now have the information available to perform the live intervals analysis
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1577 and build the live intervals themselves. We start off by numbering the basic
1578 blocks and machine instructions. We then handle the "live-in" values. These
1579 are in physical registers, so the physical register is assumed to be killed
1580 by the end of the basic block. Live intervals for virtual registers are
1581 computed for some ordering of the machine instructions <tt>[1, N]</tt>. A
1582 live interval is an interval <tt>[i, j)</tt>, where <tt>1 &lt;= i &lt;= j
1583 &lt; N</tt>, for which a variable is live.</p>
Bill Wendling34ab0672006-10-11 06:30:10 +0000[diff] [blame]1584
Bill Wendlingf21825f2006-10-11 18:00:22 +0000[diff] [blame]1585<p><i><b>More to come...</b></i></p>
1586
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]1587</div>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1588
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1589</div>
1590
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1591<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1592<h3>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1593 <a name="regalloc">Register Allocation</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1594</h3>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1595
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1596<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1597
Bill Wendling34ab0672006-10-11 06:30:10 +0000[diff] [blame]1598<p>The <i>Register Allocation problem</i> consists in mapping a program
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1599 <i>P<sub>v</sub></i>, that can use an unbounded number of virtual registers,
1600 to a program <i>P<sub>p</sub></i> that contains a finite (possibly small)
1601 number of physical registers. Each target architecture has a different number
1602 of physical registers. If the number of physical registers is not enough to
1603 accommodate all the virtual registers, some of them will have to be mapped
1604 into memory. These virtuals are called <i>spilled virtuals</i>.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1605
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1606<!-- _______________________________________________________________________ -->
1607
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1608<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1609 <a name="regAlloc_represent">How registers are represented in LLVM</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1610</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1611
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1612<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1613
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1614<p>In LLVM, physical registers are denoted by integer numbers that normally
1615 range from 1 to 1023. To see how this numbering is defined for a particular
1616 architecture, you can read the <tt>GenRegisterNames.inc</tt> file for that
1617 architecture. For instance, by
1618 inspecting <tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the
1619 32-bit register <tt>EAX</tt> is denoted by 15, and the MMX register
1620 <tt>MM0</tt> is mapped to 48.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1621
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1622<p>Some architectures contain registers that share the same physical location. A
1623 notable example is the X86 platform. For instance, in the X86 architecture,
1624 the registers <tt>EAX</tt>, <tt>AX</tt> and <tt>AL</tt> share the first eight
1625 bits. These physical registers are marked as <i>aliased</i> in LLVM. Given a
1626 particular architecture, you can check which registers are aliased by
1627 inspecting its <tt>RegisterInfo.td</tt> file. Moreover, the method
1628 <tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1629 all the physical registers aliased to the register <tt>p_reg</tt>.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1630
1631<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1632 Elements in the same register class are functionally equivalent, and can be
1633 interchangeably used. Each virtual register can only be mapped to physical
1634 registers of a particular class. For instance, in the X86 architecture, some
1635 virtuals can only be allocated to 8 bit registers. A register class is
1636 described by <tt>TargetRegisterClass</tt> objects. To discover if a virtual
1637 register is compatible with a given physical, this code can be used:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1638
1639<div class="doc_code">
1640<pre>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]1641bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1642 unsigned v_reg,
1643 unsigned p_reg) {
Dan Gohman3a4be0f2008-02-10 18:45:23 +0000[diff] [blame]1644 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1645 "Target register must be physical");
Chris Lattner21ec2b42007-12-31 04:16:08 +0000[diff] [blame]1646 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1647 return trc-&gt;contains(p_reg);
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1648}
1649</pre>
1650</div>
1651
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1652<p>Sometimes, mostly for debugging purposes, it is useful to change the number
1653 of physical registers available in the target architecture. This must be done
1654 statically, inside the <tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt>
1655 for <tt>RegisterClass</tt>, the last parameter of which is a list of
1656 registers. Just commenting some out is one simple way to avoid them being
1657 used. A more polite way is to explicitly exclude some registers from
Dan Gohman17151152009-07-24 00:30:09 +0000[diff] [blame]1658 the <i>allocation order</i>. See the definition of the <tt>GR8</tt> register
1659 class in <tt>lib/Target/X86/X86RegisterInfo.td</tt> for an example of this.
1660 </p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1661
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1662<p>Virtual registers are also denoted by integer numbers. Contrary to physical
Jakob Stoklund Olesend3438eb2011-01-08 23:10:59 +0000[diff] [blame]1663 registers, different virtual registers never share the same number. Whereas
1664 physical registers are statically defined in a <tt>TargetRegisterInfo.td</tt>
1665 file and cannot be created by the application developer, that is not the case
1666 with virtual registers. In order to create new virtual registers, use the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1667 method <tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method
Jakob Stoklund Olesend3438eb2011-01-08 23:10:59 +0000[diff] [blame]1668 will return a new virtual register. Use an <tt>IndexedMap&lt;Foo,
1669 VirtReg2IndexFunctor&gt;</tt> to hold information per virtual register. If you
1670 need to enumerate all virtual registers, use the function
1671 <tt>TargetRegisterInfo::index2VirtReg()</tt> to find the virtual register
1672 numbers:</p>
1673
1674<div class="doc_code">
1675<pre>
1676 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1677 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(i);
1678 stuff(VirtReg);
1679 }
1680</pre>
1681</div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1682
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1683<p>Before register allocation, the operands of an instruction are mostly virtual
1684 registers, although physical registers may also be used. In order to check if
1685 a given machine operand is a register, use the boolean
1686 function <tt>MachineOperand::isRegister()</tt>. To obtain the integer code of
1687 a register, use <tt>MachineOperand::getReg()</tt>. An instruction may define
1688 or use a register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1689 defines the registers 1024, and uses registers 1025 and 1026. Given a
1690 register operand, the method <tt>MachineOperand::isUse()</tt> informs if that
1691 register is being used by the instruction. The
1692 method <tt>MachineOperand::isDef()</tt> informs if that registers is being
1693 defined.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1694
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1695<p>We will call physical registers present in the LLVM bitcode before register
1696 allocation <i>pre-colored registers</i>. Pre-colored registers are used in
1697 many different situations, for instance, to pass parameters of functions
1698 calls, and to store results of particular instructions. There are two types
1699 of pre-colored registers: the ones <i>implicitly</i> defined, and
1700 those <i>explicitly</i> defined. Explicitly defined registers are normal
1701 operands, and can be accessed
1702 with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In order to check
1703 which registers are implicitly defined by an instruction, use
1704 the <tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>,
1705 where <tt>opcode</tt> is the opcode of the target instruction. One important
1706 difference between explicit and implicit physical registers is that the
1707 latter are defined statically for each instruction, whereas the former may
1708 vary depending on the program being compiled. For example, an instruction
1709 that represents a function call will always implicitly define or use the same
1710 set of physical registers. To read the registers implicitly used by an
1711 instruction,
1712 use <tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1713 registers impose constraints on any register allocation algorithm. The
Bob Wilson35e856a2010-04-09 18:39:54 +0000[diff] [blame]1714 register allocator must make sure that none of them are overwritten by
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1715 the values of virtual registers while still alive.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1716
1717</div>
1718
1719<!-- _______________________________________________________________________ -->
1720
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1721<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1722 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1723</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1724
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1725<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1726
1727<p>There are two ways to map virtual registers to physical registers (or to
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1728 memory slots). The first way, that we will call <i>direct mapping</i>, is
1729 based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
1730 and <tt>MachineOperand</tt>. The second way, that we will call <i>indirect
1731 mapping</i>, relies on the <tt>VirtRegMap</tt> class in order to insert loads
1732 and stores sending and getting values to and from memory.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1733
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1734<p>The direct mapping provides more flexibility to the developer of the register
1735 allocator; however, it is more error prone, and demands more implementation
1736 work. Basically, the programmer will have to specify where load and store
1737 instructions should be inserted in the target function being compiled in
1738 order to get and store values in memory. To assign a physical register to a
1739 virtual register present in a given operand,
1740 use <tt>MachineOperand::setReg(p_reg)</tt>. To insert a store instruction,
Jakob Stoklund Olesen94e90b92010-08-31 22:01:07 +0000[diff] [blame]1741 use <tt>TargetInstrInfo::storeRegToStackSlot(...)</tt>, and to insert a
1742 load instruction, use <tt>TargetInstrInfo::loadRegFromStackSlot</tt>.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1743
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1744<p>The indirect mapping shields the application developer from the complexities
1745 of inserting load and store instructions. In order to map a virtual register
1746 to a physical one, use <tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In
1747 order to map a certain virtual register to memory,
1748 use <tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will return
1749 the stack slot where <tt>vreg</tt>'s value will be located. If it is
1750 necessary to map another virtual register to the same stack slot,
1751 use <tt>VirtRegMap::assignVirt2StackSlot(vreg, stack_location)</tt>. One
1752 important point to consider when using the indirect mapping, is that even if
1753 a virtual register is mapped to memory, it still needs to be mapped to a
1754 physical register. This physical register is the location where the virtual
1755 register is supposed to be found before being stored or after being
1756 reloaded.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1757
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1758<p>If the indirect strategy is used, after all the virtual registers have been
1759 mapped to physical registers or stack slots, it is necessary to use a spiller
1760 object to place load and store instructions in the code. Every virtual that
1761 has been mapped to a stack slot will be stored to memory after been defined
1762 and will be loaded before being used. The implementation of the spiller tries
1763 to recycle load/store instructions, avoiding unnecessary instructions. For an
1764 example of how to invoke the spiller,
1765 see <tt>RegAllocLinearScan::runOnMachineFunction</tt>
1766 in <tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1767
1768</div>
1769
1770<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1771<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1772 <a name="regAlloc_twoAddr">Handling two address instructions</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1773</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1774
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1775<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1776
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1777<p>With very rare exceptions (e.g., function calls), the LLVM machine code
1778 instructions are three address instructions. That is, each instruction is
1779 expected to define at most one register, and to use at most two registers.
1780 However, some architectures use two address instructions. In this case, the
1781 defined register is also one of the used register. For instance, an
1782 instruction such as <tt>ADD %EAX, %EBX</tt>, in X86 is actually equivalent
1783 to <tt>%EAX = %EAX + %EBX</tt>.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1784
1785<p>In order to produce correct code, LLVM must convert three address
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1786 instructions that represent two address instructions into true two address
1787 instructions. LLVM provides the pass <tt>TwoAddressInstructionPass</tt> for
1788 this specific purpose. It must be run before register allocation takes
1789 place. After its execution, the resulting code may no longer be in SSA
1790 form. This happens, for instance, in situations where an instruction such
1791 as <tt>%a = ADD %b %c</tt> is converted to two instructions such as:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1792
1793<div class="doc_code">
1794<pre>
1795%a = MOVE %b
Dan Gohman01cd2d92008-06-13 17:55:57 +0000[diff] [blame]1796%a = ADD %a %c
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1797</pre>
1798</div>
1799
1800<p>Notice that, internally, the second instruction is represented as
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1801 <tt>ADD %a[def/use] %c</tt>. I.e., the register operand <tt>%a</tt> is both
1802 used and defined by the instruction.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1803
1804</div>
1805
1806<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1807<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1808 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1809</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1810
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1811<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1812
1813<p>An important transformation that happens during register allocation is called
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1814 the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many analyses
1815 that are performed on the control flow graph of programs. However,
1816 traditional instruction sets do not implement PHI instructions. Thus, in
1817 order to generate executable code, compilers must replace PHI instructions
1818 with other instructions that preserve their semantics.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1819
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1820<p>There are many ways in which PHI instructions can safely be removed from the
1821 target code. The most traditional PHI deconstruction algorithm replaces PHI
1822 instructions with copy instructions. That is the strategy adopted by
1823 LLVM. The SSA deconstruction algorithm is implemented
1824 in <tt>lib/CodeGen/PHIElimination.cpp</tt>. In order to invoke this pass, the
1825 identifier <tt>PHIEliminationID</tt> must be marked as required in the code
1826 of the register allocator.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1827
1828</div>
1829
1830<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1831<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1832 <a name="regAlloc_fold">Instruction folding</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1833</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1834
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1835<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1836
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1837<p><i>Instruction folding</i> is an optimization performed during register
1838 allocation that removes unnecessary copy instructions. For instance, a
1839 sequence of instructions such as:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1840
1841<div class="doc_code">
1842<pre>
1843%EBX = LOAD %mem_address
1844%EAX = COPY %EBX
1845</pre>
1846</div>
1847
Dan Gohman970a5472008-11-24 16:35:31 +0000[diff] [blame]1848<p>can be safely substituted by the single instruction:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1849
1850<div class="doc_code">
1851<pre>
1852%EAX = LOAD %mem_address
1853</pre>
1854</div>
1855
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1856<p>Instructions can be folded with
1857 the <tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1858 taken when folding instructions; a folded instruction can be quite different
1859 from the original
1860 instruction. See <tt>LiveIntervals::addIntervalsForSpills</tt>
1861 in <tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its
1862 use.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1863
1864</div>
1865
1866<!-- _______________________________________________________________________ -->
1867
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1868<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1869 <a name="regAlloc_builtIn">Built in register allocators</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1870</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1871
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1872<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1873
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1874<p>The LLVM infrastructure provides the application developer with three
1875 different register allocators:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1876
1877<ul>
Jakob Stoklund Olesenec2e9642010-06-15 21:58:33 +0000[diff] [blame]1878 <li><i>Fast</i> &mdash; This register allocator is the default for debug
1879 builds. It allocates registers on a basic block level, attempting to keep
1880 values in registers and reusing registers as appropriate.</li>
1881
Andrew Tricke69a1952011-07-26 18:31:49 +0000[diff] [blame]1882 <li><i>Basic</i> &mdash; This is an incremental approach to register
1883 allocation. Live ranges are assigned to registers one at a time in
1884 an order that is driven by heuristics. Since code can be rewritten
1885 on-the-fly during allocation, this framework allows interesting
1886 allocators to be developed as extensions. It is not itself a
1887 production register allocator but is a potentially useful
1888 stand-alone mode for triaging bugs and as a performance baseline.
1889
1890 <li><i>Greedy</i> &mdash; <i>The default allocator</i>. This is a
1891 highly tuned implementation of the <i>Basic</i> allocator that
1892 incorporates global live range splitting. This allocator works hard
1893 to minimize the cost of spill code.
1894
Jakob Stoklund Olesenec2e9642010-06-15 21:58:33 +0000[diff] [blame]1895 <li><i>PBQP</i> &mdash; A Partitioned Boolean Quadratic Programming (PBQP)
1896 based register allocator. This allocator works by constructing a PBQP
1897 problem representing the register allocation problem under consideration,
1898 solving this using a PBQP solver, and mapping the solution back to a
1899 register assignment.</li>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1900</ul>
1901
1902<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1903 command line option <tt>-regalloc=...</tt>:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1904
1905<div class="doc_code">
1906<pre>
Dan Gohmandd121d52009-08-25 15:54:01 +0000[diff] [blame]1907$ llc -regalloc=linearscan file.bc -o ln.s;
Jakob Stoklund Olesenec2e9642010-06-15 21:58:33 +0000[diff] [blame]1908$ llc -regalloc=fast file.bc -o fa.s;
1909$ llc -regalloc=pbqp file.bc -o pbqp.s;
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1910</pre>
1911</div>
1912
1913</div>
1914
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1915</div>
1916
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1917<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1918<h3>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1919 <a name="proepicode">Prolog/Epilog Code Insertion</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1920</h3>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1921
NAKAMURA Takumia35cdd62011-10-31 13:04:26 +0000[diff] [blame]1922<div>
1923
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1924<!-- _______________________________________________________________________ -->
1925<h4>
1926 <a name="compact_unwind">Compact Unwind</a>
1927</h4>
1928
1929<div>
1930
Bill Wendlingdd7805a2011-07-26 07:58:09 +0000[diff] [blame]1931<p>Throwing an exception requires <em>unwinding</em> out of a function. The
1932 information on how to unwind a given function is traditionally expressed in
1933 DWARF unwind (a.k.a. frame) info. But that format was originally developed
1934 for debuggers to backtrace, and each Frame Description Entry (FDE) requires
1935 ~20-30 bytes per function. There is also the cost of mapping from an address
1936 in a function to the corresponding FDE at runtime. An alternative unwind
1937 encoding is called <em>compact unwind</em> and requires just 4-bytes per
1938 function.</p>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1939
1940<p>The compact unwind encoding is a 32-bit value, which is encoded in an
1941 architecture-specific way. It specifies which registers to restore and from
Roman Divacky2fbb48a2011-08-01 20:38:27 +0000[diff] [blame]1942 where, and how to unwind out of the function. When the linker creates a final
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1943 linked image, it will create a <code>__TEXT,__unwind_info</code>
1944 section. This section is a small and fast way for the runtime to access
1945 unwind info for any given function. If we emit compact unwind info for the
1946 function, that compact unwind info will be encoded in
1947 the <code>__TEXT,__unwind_info</code> section. If we emit DWARF unwind info,
1948 the <code>__TEXT,__unwind_info</code> section will contain the offset of the
1949 FDE in the <code>__TEXT,__eh_frame</code> section in the final linked
1950 image.</p>
1951
1952<p>For X86, there are three modes for the compact unwind encoding:</p>
1953
Bill Wendlingdd7805a2011-07-26 07:58:09 +0000[diff] [blame]1954<dl>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1955 <dt><i>Function with a Frame Pointer (<code>EBP</code> or <code>RBP</code>)</i></dt>
1956 <dd><p><code>EBP/RBP</code>-based frame, where <code>EBP/RBP</code> is pushed
1957 onto the stack immediately after the return address,
1958 then <code>ESP/RSP</code> is moved to <code>EBP/RBP</code>. Thus to
1959 unwind, <code>ESP/RSP</code> is restored with the
1960 current <code>EBP/RBP</code> value, then <code>EBP/RBP</code> is restored
1961 by popping the stack, and the return is done by popping the stack once
1962 more into the PC. All non-volatile registers that need to be restored must
1963 have been saved in a small range on the stack that
1964 starts <code>EBP-4</code> to <code>EBP-1020</code> (<code>RBP-8</code>
Bill Wendlingdd7805a2011-07-26 07:58:09 +0000[diff] [blame]1965 to <code>RBP-1020</code>). The offset (divided by 4 in 32-bit mode and 8
1966 in 64-bit mode) is encoded in bits 16-23 (mask: <code>0x00FF0000</code>).
1967 The registers saved are encoded in bits 0-14
1968 (mask: <code>0x00007FFF</code>) as five 3-bit entries from the following
1969 table:</p>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1970<table border="1" cellspacing="0">
1971 <tr>
1972 <th>Compact Number</th>
1973 <th>i386 Register</th>
1974 <th>x86-64 Regiser</th>
1975 </tr>
1976 <tr>
1977 <td>1</td>
1978 <td><code>EBX</code></td>
1979 <td><code>RBX</code></td>
1980 </tr>
1981 <tr>
1982 <td>2</td>
1983 <td><code>ECX</code></td>
1984 <td><code>R12</code></td>
1985 </tr>
1986 <tr>
1987 <td>3</td>
1988 <td><code>EDX</code></td>
1989 <td><code>R13</code></td>
1990 </tr>
1991 <tr>
1992 <td>4</td>
1993 <td><code>EDI</code></td>
1994 <td><code>R14</code></td>
1995 </tr>
1996 <tr>
1997 <td>5</td>
1998 <td><code>ESI</code></td>
1999 <td><code>R15</code></td>
2000 </tr>
2001 <tr>
2002 <td>6</td>
2003 <td><code>EBP</code></td>
2004 <td><code>RBP</code></td>
2005 </tr>
2006</table>
2007
2008</dd>
2009
Bill Wendlinge2225052011-07-25 20:25:03 +0000[diff] [blame]2010 <dt><i>Frameless with a Small Constant Stack Size (<code>EBP</code>
2011 or <code>RBP</code> is not used as a frame pointer)</i></dt>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]2012 <dd><p>To return, a constant (encoded in the compact unwind encoding) is added
2013 to the <code>ESP/RSP</code>. Then the return is done by popping the stack
2014 into the PC. All non-volatile registers that need to be restored must have
2015 been saved on the stack immediately after the return address. The stack
Bill Wendlingdd7805a2011-07-26 07:58:09 +0000[diff] [blame]2016 size (divided by 4 in 32-bit mode and 8 in 64-bit mode) is encoded in bits
2017 16-23 (mask: <code>0x00FF0000</code>). There is a maximum stack size of
2018 1024 bytes in 32-bit mode and 2048 in 64-bit mode. The number of registers
2019 saved is encoded in bits 9-12 (mask: <code>0x00001C00</code>). Bits 0-9
2020 (mask: <code>0x000003FF</code>) contain which registers were saved and
2021 their order. (See
2022 the <code>encodeCompactUnwindRegistersWithoutFrame()</code> function
2023 in <code>lib/Target/X86FrameLowering.cpp</code> for the encoding
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]2024 algorithm.)</p></dd>
2025
Bill Wendlinge2225052011-07-25 20:25:03 +0000[diff] [blame]2026 <dt><i>Frameless with a Large Constant Stack Size (<code>EBP</code>
2027 or <code>RBP</code> is not used as a frame pointer)</i></dt>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]2028 <dd><p>This case is like the "Frameless with a Small Constant Stack Size"
Bill Wendlinge2225052011-07-25 20:25:03 +0000[diff] [blame]2029 case, but the stack size is too large to encode in the compact unwind
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]2030 encoding. Instead it requires that the function contains "<code>subl
2031 $nnnnnn, %esp</code>" in its prolog. The compact encoding contains the
Bill Wendlinge2225052011-07-25 20:25:03 +0000[diff] [blame]2032 offset to the <code>$nnnnnn</code> value in the function in bits 9-12
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]2033 (mask: <code>0x00001C00</code>).</p></dd>
Bill Wendlingdd7805a2011-07-26 07:58:09 +0000[diff] [blame]2034</dl>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]2035
2036</div>
2037
NAKAMURA Takumia35cdd62011-10-31 13:04:26 +0000[diff] [blame]2038</div>
2039
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]2040<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2041<h3>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]2042 <a name="latemco">Late Machine Code Optimizations</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2043</h3>
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2044<div><p>To Be Written</p></div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2045
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]2046<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2047<h3>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2048 <a name="codeemit">Code Emission</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2049</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2050
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2051<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2052
2053<p>The code emission step of code generation is responsible for lowering from
2054the code generator abstractions (like <a
2055href="#machinefunction">MachineFunction</a>, <a
2056href="#machineinstr">MachineInstr</a>, etc) down
2057to the abstractions used by the MC layer (<a href="#mcinst">MCInst</a>,
2058<a href="#mcstreamer">MCStreamer</a>, etc). This is
2059done with a combination of several different classes: the (misnamed)
2060target-independent AsmPrinter class, target-specific subclasses of AsmPrinter
2061(such as SparcAsmPrinter), and the TargetLoweringObjectFile class.</p>
2062
2063<p>Since the MC layer works at the level of abstraction of object files, it
2064doesn't have a notion of functions, global variables etc. Instead, it thinks
2065about labels, directives, and instructions. A key class used at this time is
2066the MCStreamer class. This is an abstract API that is implemented in different
2067ways (e.g. to output a .s file, output an ELF .o file, etc) that is effectively
2068an "assembler API". MCStreamer has one method per directive, such as EmitLabel,
2069EmitSymbolAttribute, SwitchSection, etc, which directly correspond to assembly
2070level directives.
2071</p>
2072
2073<p>If you are interested in implementing a code generator for a target, there
2074are three important things that you have to implement for your target:</p>
2075
2076<ol>
2077<li>First, you need a subclass of AsmPrinter for your target. This class
2078implements the general lowering process converting MachineFunction's into MC
2079label constructs. The AsmPrinter base class provides a number of useful methods
2080and routines, and also allows you to override the lowering process in some
2081important ways. You should get much of the lowering for free if you are
2082implementing an ELF, COFF, or MachO target, because the TargetLoweringObjectFile
2083class implements much of the common logic.</li>
2084
2085<li>Second, you need to implement an instruction printer for your target. The
2086instruction printer takes an <a href="#mcinst">MCInst</a> and renders it to a
2087raw_ostream as text. Most of this is automatically generated from the .td file
2088(when you specify something like "<tt>add $dst, $src1, $src2</tt>" in the
2089instructions), but you need to implement routines to print operands.</li>
2090
2091<li>Third, you need to implement code that lowers a <a
2092href="#machineinstr">MachineInstr</a> to an MCInst, usually implemented in
2093"&lt;target&gt;MCInstLower.cpp". This lowering process is often target
2094specific, and is responsible for turning jump table entries, constant pool
2095indices, global variable addresses, etc into MCLabels as appropriate. This
2096translation layer is also responsible for expanding pseudo ops used by the code
2097generator into the actual machine instructions they correspond to. The MCInsts
2098that are generated by this are fed into the instruction printer or the encoder.
2099</li>
2100
2101</ol>
2102
2103<p>Finally, at your choosing, you can also implement an subclass of
2104MCCodeEmitter which lowers MCInst's into machine code bytes and relocations.
2105This is important if you want to support direct .o file emission, or would like
2106to implement an assembler for your target.</p>
2107
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2108</div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2109
Anshuman Dasguptabcfa2f82011-12-06 23:12:42 +0000[diff] [blame]2110<!-- ======================================================================= -->
2111<h3>
2112 <a name="vliw_packetizer">VLIW Packetizer</a>
2113</h3>
2114
2115<div>
2116
2117<p>In a Very Long Instruction Word (VLIW) architecture, the compiler is
2118 responsible for mapping instructions to functional-units available on
2119 the architecture. To that end, the compiler creates groups of instructions
2120 called <i>packets</i> or <i>bundles</i>. The VLIW packetizer in LLVM is
2121 a target-independent mechanism to enable the packetization of machine
2122 instructions.</p>
2123
2124<!-- _______________________________________________________________________ -->
2125
2126<h4>
2127 <a name="vliw_mapping">Mapping from instructions to functional units</a>
2128</h4>
2129
2130<div>
2131
2132<p>Instructions in a VLIW target can typically be mapped to multiple functional
2133units. During the process of packetizing, the compiler must be able to reason
2134about whether an instruction can be added to a packet. This decision can be
2135complex since the compiler has to examine all possible mappings of instructions
2136to functional units. Therefore to alleviate compilation-time complexity, the
2137VLIW packetizer parses the instruction classes of a target and generates tables
2138at compiler build time. These tables can then be queried by the provided
2139machine-independent API to determine if an instruction can be accommodated in a
2140packet.</p>
2141</div>
2142
2143<!-- ======================================================================= -->
2144<h4>
2145 <a name="vliw_repr">
2146 How the packetization tables are generated and used
2147 </a>
2148</h4>
2149
2150<div>
2151
2152<p>The packetizer reads instruction classes from a target's itineraries and
2153creates a deterministic finite automaton (DFA) to represent the state of a
2154packet. A DFA consists of three major elements: inputs, states, and
2155transitions. The set of inputs for the generated DFA represents the instruction
2156being added to a packet. The states represent the possible consumption
2157of functional units by instructions in a packet. In the DFA, transitions from
2158one state to another occur on the addition of an instruction to an existing
2159packet. If there is a legal mapping of functional units to instructions, then
2160the DFA contains a corresponding transition. The absence of a transition
2161indicates that a legal mapping does not exist and that the instruction cannot
2162be added to the packet.</p>
2163
2164<p>To generate tables for a VLIW target, add <i>Target</i>GenDFAPacketizer.inc
2165as a target to the Makefile in the target directory. The exported API provides
2166three functions: <tt>DFAPacketizer::clearResources()</tt>,
2167<tt>DFAPacketizer::reserveResources(MachineInstr *MI)</tt>, and
2168<tt>DFAPacketizer::canReserveResources(MachineInstr *MI)</tt>. These functions
2169allow a target packetizer to add an instruction to an existing packet and to
2170check whether an instruction can be added to a packet. See
2171<tt>llvm/CodeGen/DFAPacketizer.h</tt> for more information.</p>
2172
2173</div>
2174
2175</div>
2176
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2177</div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2178
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2179<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2180<h2>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2181 <a name="nativeassembler">Implementing a Native Assembler</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2182</h2>
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2183<!-- *********************************************************************** -->
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2184
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2185<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2186
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2187<p>Though you're probably reading this because you want to write or maintain a
2188compiler backend, LLVM also fully supports building a native assemblers too.
2189We've tried hard to automate the generation of the assembler from the .td files
2190(in particular the instruction syntax and encodings), which means that a large
2191part of the manual and repetitive data entry can be factored and shared with the
2192compiler.</p>
2193
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2194<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2195<h3 id="na_instparsing">Instruction Parsing</h3>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2196
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2197<div><p>To Be Written</p></div>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2198
2199
2200<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2201<h3 id="na_instaliases">
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2202 Instruction Alias Processing
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2203</h3>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2204
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2205<div>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2206<p>Once the instruction is parsed, it enters the MatchInstructionImpl function.
2207The MatchInstructionImpl function performs alias processing and then does
2208actual matching.</p>
2209
Chris Lattner2cb092d2010-10-30 19:23:13 +0000[diff] [blame]2210<p>Alias processing is the phase that canonicalizes different lexical forms of
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2211the same instructions down to one representation. There are several different
2212kinds of alias that are possible to implement and they are listed below in the
2213order that they are processed (which is in order from simplest/weakest to most
2214complex/powerful). Generally you want to use the first alias mechanism that
2215meets the needs of your instruction, because it will allow a more concise
2216description.</p>
2217
2218<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2219<h4>Mnemonic Aliases</h4>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2220
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2221<div>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2222
Chris Lattnerf9ec2fb2010-10-30 19:47:49 +0000[diff] [blame]2223<p>The first phase of alias processing is simple instruction mnemonic
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2224remapping for classes of instructions which are allowed with two different
Chris Lattner2cb092d2010-10-30 19:23:13 +0000[diff] [blame]2225mnemonics. This phase is a simple and unconditionally remapping from one input
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2226mnemonic to one output mnemonic. It isn't possible for this form of alias to
2227look at the operands at all, so the remapping must apply for all forms of a
2228given mnemonic. Mnemonic aliases are defined simply, for example X86 has:
2229</p>
2230
2231<div class="doc_code">
2232<pre>
2233def : MnemonicAlias&lt;"cbw", "cbtw"&gt;;
2234def : MnemonicAlias&lt;"smovq", "movsq"&gt;;
2235def : MnemonicAlias&lt;"fldcww", "fldcw"&gt;;
2236def : MnemonicAlias&lt;"fucompi", "fucomip"&gt;;
2237def : MnemonicAlias&lt;"ud2a", "ud2"&gt;;
2238</pre>
2239</div>
2240
2241<p>... and many others. With a MnemonicAlias definition, the mnemonic is
Chris Lattner2cb092d2010-10-30 19:23:13 +0000[diff] [blame]2242remapped simply and directly. Though MnemonicAlias's can't look at any aspect
2243of the instruction (such as the operands) they can depend on global modes (the
2244same ones supported by the matcher), through a Requires clause:</p>
2245
2246<div class="doc_code">
2247<pre>
2248def : MnemonicAlias&lt;"pushf", "pushfq"&gt;, Requires&lt;[In64BitMode]&gt;;
2249def : MnemonicAlias&lt;"pushf", "pushfl"&gt;, Requires&lt;[In32BitMode]&gt;;
2250</pre>
2251</div>
2252
2253<p>In this example, the mnemonic gets mapped into different a new one depending
2254on the current instruction set.</p>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2255
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2256</div>
2257
Chris Lattner8b0a71f2010-11-06 08:30:26 +0000[diff] [blame]2258<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2259<h4>Instruction Aliases</h4>
Chris Lattner8b0a71f2010-11-06 08:30:26 +0000[diff] [blame]2260
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2261<div>
Chris Lattner8b0a71f2010-11-06 08:30:26 +0000[diff] [blame]2262
2263<p>The most general phase of alias processing occurs while matching is
2264happening: it provides new forms for the matcher to match along with a specific
2265instruction to generate. An instruction alias has two parts: the string to
2266match and the instruction to generate. For example:
2267</p>
2268
2269<div class="doc_code">
2270<pre>
2271def : InstAlias&lt;"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8 :$src)&gt;;
2272def : InstAlias&lt;"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)&gt;;
2273def : InstAlias&lt;"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8 :$src)&gt;;
2274def : InstAlias&lt;"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16 :$src)&gt;;
2275def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8 :$src)&gt;;
2276def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16 :$src)&gt;;
2277def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32 :$src)&gt;;
2278</pre>
2279</div>
2280
2281<p>This shows a powerful example of the instruction aliases, matching the
2282same mnemonic in multiple different ways depending on what operands are present
2283in the assembly. The result of instruction aliases can include operands in a
2284different order than the destination instruction, and can use an input
2285multiple times, for example:</p>
2286
2287<div class="doc_code">
2288<pre>
2289def : InstAlias&lt;"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)&gt;;
2290def : InstAlias&lt;"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)&gt;;
2291def : InstAlias&lt;"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)&gt;;
2292def : InstAlias&lt;"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)&gt;;
2293</pre>
2294</div>
2295
2296<p>This example also shows that tied operands are only listed once. In the X86
2297backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied
2298to the output). InstAliases take a flattened operand list without duplicates
Chris Lattner4869d342010-11-06 19:57:21 +0000[diff] [blame]2299for tied operands. The result of an instruction alias can also use immediates
2300and fixed physical registers which are added as simple immediate operands in the
2301result, for example:</p>
Chris Lattnerb6f8e822010-11-06 19:25:43 +0000[diff] [blame]2302
2303<div class="doc_code">
2304<pre>
Chris Lattner4869d342010-11-06 19:57:21 +0000[diff] [blame]2305// Fixed Immediate operand.
Chris Lattnerb6f8e822010-11-06 19:25:43 +0000[diff] [blame]2306def : InstAlias&lt;"aad", (AAD8i8 10)&gt;;
Chris Lattner4869d342010-11-06 19:57:21 +0000[diff] [blame]2307
2308// Fixed register operand.
2309def : InstAlias&lt;"fcomi", (COM_FIr ST1)&gt;;
2310
2311// Simple alias.
2312def : InstAlias&lt;"fcomi $reg", (COM_FIr RST:$reg)&gt;;
Chris Lattnerb6f8e822010-11-06 19:25:43 +0000[diff] [blame]2313</pre>
2314</div>
2315
Chris Lattner8b0a71f2010-11-06 08:30:26 +0000[diff] [blame]2316
2317<p>Instruction aliases can also have a Requires clause to make them
2318subtarget specific.</p>
2319
Bill Wendling260c4a92011-05-04 23:40:14 +0000[diff] [blame]2320<p>If the back-end supports it, the instruction printer can automatically emit
2321 the alias rather than what's being aliased. It typically leads to better,
2322 more readable code. If it's better to print out what's being aliased, then
2323 pass a '0' as the third parameter to the InstAlias definition.</p>
2324
Chris Lattner8b0a71f2010-11-06 08:30:26 +0000[diff] [blame]2325</div>
2326
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2327</div>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2328
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2329<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2330<h3 id="na_matching">Instruction Matching</h3>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2331
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2332<div><p>To Be Written</p></div>
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2333
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2334</div>
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2335
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]2336<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2337<h2>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2338 <a name="targetimpls">Target-specific Implementation Notes</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2339</h2>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2340<!-- *********************************************************************** -->
2341
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2342<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2343
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2344<p>This section of the document explains features or design decisions that are
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2345 specific to the code generator for a particular target. First we start
2346 with a table that summarizes what features are supported by each target.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2347
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]2348<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2349<h3>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2350 <a name="targetfeatures">Target Feature Matrix</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2351</h3>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2352
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2353<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2354
2355<p>Note that this table does not include the C backend or Cpp backends, since
2356they do not use the target independent code generator infrastructure. It also
2357doesn't list features that are not supported fully by any target yet. It
2358considers a feature to be supported if at least one subtarget supports it. A
2359feature being supported means that it is useful and works for most cases, it
2360does not indicate that there are zero known bugs in the implementation. Here
2361is the key:</p>
2362
2363
2364<table border="1" cellspacing="0">
2365 <tr>
2366 <th>Unknown</th>
2367 <th>No support</th>
2368 <th>Partial Support</th>
2369 <th>Complete Support</th>
2370 </tr>
2371 <tr>
2372 <td class="unknown"></td>
2373 <td class="no"></td>
2374 <td class="partial"></td>
2375 <td class="yes"></td>
2376 </tr>
2377</table>
2378
2379<p>Here is the table:</p>
2380
2381<table width="689" border="1" cellspacing="0">
2382<tr><td></td>
Benjamin Kramerc940bcf2010-10-30 21:07:28 +0000[diff] [blame]2383<td colspan="13" align="center" style="background-color:#ffc">Target</td>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2384</tr>
2385 <tr>
2386 <th>Feature</th>
2387 <th>ARM</th>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2388 <th>CellSPU</th>
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2389 <th>Hexagon</th>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2390 <th>MBlaze</th>
2391 <th>MSP430</th>
2392 <th>Mips</th>
2393 <th>PTX</th>
2394 <th>PowerPC</th>
2395 <th>Sparc</th>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2396 <th>X86</th>
2397 <th>XCore</th>
2398 </tr>
2399
2400<tr>
2401 <td><a href="#feat_reliable">is generally reliable</a></td>
2402 <td class="yes"></td> <!-- ARM -->
Kalle Raiskila829b21f2010-10-25 08:57:30 +0000[diff] [blame]2403 <td class="no"></td> <!-- CellSPU -->
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2404 <td class="yes"></td> <!-- Hexagon -->
Wesley Peck188dead2010-10-24 18:50:12 +0000[diff] [blame]2405 <td class="no"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2406 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes4f6d7d42011-10-25 20:09:31 +0000[diff] [blame]2407 <td class="yes"></td> <!-- Mips -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2408 <td class="no"></td> <!-- PTX -->
2409 <td class="yes"></td> <!-- PowerPC -->
2410 <td class="yes"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2411 <td class="yes"></td> <!-- X86 -->
2412 <td class="unknown"></td> <!-- XCore -->
2413</tr>
2414
2415<tr>
2416 <td><a href="#feat_asmparser">assembly parser</a></td>
2417 <td class="no"></td> <!-- ARM -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2418 <td class="no"></td> <!-- CellSPU -->
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2419 <td class="no"></td> <!-- Hexagon -->
Wesley Peck671d54d2010-12-20 21:54:50 +0000[diff] [blame]2420 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2421 <td class="no"></td> <!-- MSP430 -->
2422 <td class="no"></td> <!-- Mips -->
2423 <td class="no"></td> <!-- PTX -->
2424 <td class="no"></td> <!-- PowerPC -->
2425 <td class="no"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2426 <td class="yes"></td> <!-- X86 -->
2427 <td class="no"></td> <!-- XCore -->
2428</tr>
2429
2430<tr>
2431 <td><a href="#feat_disassembler">disassembler</a></td>
2432 <td class="yes"></td> <!-- ARM -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2433 <td class="no"></td> <!-- CellSPU -->
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2434 <td class="no"></td> <!-- Hexagon -->
Wesley Peck671d54d2010-12-20 21:54:50 +0000[diff] [blame]2435 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2436 <td class="no"></td> <!-- MSP430 -->
2437 <td class="no"></td> <!-- Mips -->
2438 <td class="no"></td> <!-- PTX -->
2439 <td class="no"></td> <!-- PowerPC -->
2440 <td class="no"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2441 <td class="yes"></td> <!-- X86 -->
2442 <td class="no"></td> <!-- XCore -->
2443</tr>
2444
2445<tr>
2446 <td><a href="#feat_inlineasm">inline asm</a></td>
2447 <td class="yes"></td> <!-- ARM -->
Kalle Raiskila829b21f2010-10-25 08:57:30 +0000[diff] [blame]2448 <td class="no"></td> <!-- CellSPU -->
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2449 <td class="yes"></td> <!-- Hexagon -->
Wesley Peck671d54d2010-12-20 21:54:50 +0000[diff] [blame]2450 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2451 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes8e303e82010-12-19 22:41:43 +0000[diff] [blame]2452 <td class="no"></td> <!-- Mips -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2453 <td class="unknown"></td> <!-- PTX -->
2454 <td class="yes"></td> <!-- PowerPC -->
2455 <td class="unknown"></td> <!-- Sparc -->
Jakob Stoklund Olesen1c483172011-09-19 18:15:46 +0000[diff] [blame]2456 <td class="yes"></td> <!-- X86 -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2457 <td class="unknown"></td> <!-- XCore -->
2458</tr>
2459
2460<tr>
2461 <td><a href="#feat_jit">jit</a></td>
2462 <td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
Kalle Raiskila829b21f2010-10-25 08:57:30 +0000[diff] [blame]2463 <td class="no"></td> <!-- CellSPU -->
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2464 <td class="no"></td> <!-- Hexagon -->
Wesley Peck188dead2010-10-24 18:50:12 +0000[diff] [blame]2465 <td class="no"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2466 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes4f6d7d42011-10-25 20:09:31 +0000[diff] [blame]2467 <td class="yes"></td> <!-- Mips -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2468 <td class="unknown"></td> <!-- PTX -->
2469 <td class="yes"></td> <!-- PowerPC -->
2470 <td class="unknown"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2471 <td class="yes"></td> <!-- X86 -->
2472 <td class="unknown"></td> <!-- XCore -->
2473</tr>
2474
2475<tr>
2476 <td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>
2477 <td class="no"></td> <!-- ARM -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2478 <td class="no"></td> <!-- CellSPU -->
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2479 <td class="no"></td> <!-- Hexagon -->
Wesley Peck671d54d2010-12-20 21:54:50 +0000[diff] [blame]2480 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2481 <td class="no"></td> <!-- MSP430 -->
2482 <td class="no"></td> <!-- Mips -->
2483 <td class="no"></td> <!-- PTX -->
2484 <td class="no"></td> <!-- PowerPC -->
2485 <td class="no"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2486 <td class="yes"></td> <!-- X86 -->
2487 <td class="no"></td> <!-- XCore -->
2488</tr>
2489
2490<tr>
2491 <td><a href="#feat_tailcall">tail calls</a></td>
2492 <td class="yes"></td> <!-- ARM -->
Kalle Raiskila829b21f2010-10-25 08:57:30 +0000[diff] [blame]2493 <td class="no"></td> <!-- CellSPU -->
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2494 <td class="yes"></td> <!-- Hexagon -->
Wesley Peck188dead2010-10-24 18:50:12 +0000[diff] [blame]2495 <td class="no"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2496 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes8e303e82010-12-19 22:41:43 +0000[diff] [blame]2497 <td class="no"></td> <!-- Mips -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2498 <td class="unknown"></td> <!-- PTX -->
2499 <td class="yes"></td> <!-- PowerPC -->
2500 <td class="unknown"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2501 <td class="yes"></td> <!-- X86 -->
2502 <td class="unknown"></td> <!-- XCore -->
2503</tr>
2504
Rafael Espindola799ca892011-11-27 22:05:46 +0000[diff] [blame]2505<tr>
2506 <td><a href="#feat_segstacks">segmented stacks</a></td>
2507 <td class="no"></td> <!-- ARM -->
2508 <td class="no"></td> <!-- CellSPU -->
Joe Abbey36cd89e2012-01-16 13:16:05 +0000[diff] [blame]2509 <td class="no"></td> <!-- Hexagon -->
Rafael Espindola799ca892011-11-27 22:05:46 +0000[diff] [blame]2510 <td class="no"></td> <!-- MBlaze -->
2511 <td class="no"></td> <!-- MSP430 -->
2512 <td class="no"></td> <!-- Mips -->
2513 <td class="no"></td> <!-- PTX -->
2514 <td class="no"></td> <!-- PowerPC -->
2515 <td class="no"></td> <!-- Sparc -->
2516 <td class="partial"><a href="#feat_segstacks_x86">*</a></td> <!-- X86 -->
2517 <td class="no"></td> <!-- XCore -->
2518</tr>
2519
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2520
2521</table>
2522
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2523<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2524<h4 id="feat_reliable">Is Generally Reliable</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2525
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2526<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2527<p>This box indicates whether the target is considered to be production quality.
2528This indicates that the target has been used as a static compiler to
2529compile large amounts of code by a variety of different people and is in
2530continuous use.</p>
2531</div>
2532
2533<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2534<h4 id="feat_asmparser">Assembly Parser</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2535
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2536<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2537<p>This box indicates whether the target supports parsing target specific .s
2538files by implementing the MCAsmParser interface. This is required for llvm-mc
2539to be able to act as a native assembler and is required for inline assembly
2540support in the native .o file writer.</p>
2541
2542</div>
2543
2544
2545<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2546<h4 id="feat_disassembler">Disassembler</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2547
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2548<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2549<p>This box indicates whether the target supports the MCDisassembler API for
2550disassembling machine opcode bytes into MCInst's.</p>
2551
2552</div>
2553
2554<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2555<h4 id="feat_inlineasm">Inline Asm</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2556
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2557<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2558<p>This box indicates whether the target supports most popular inline assembly
2559constraints and modifiers.</p>
2560
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2561</div>
2562
2563<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2564<h4 id="feat_jit">JIT Support</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2565
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2566<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2567<p>This box indicates whether the target supports the JIT compiler through
2568the ExecutionEngine interface.</p>
2569
Chris Lattner60616b12010-10-24 16:24:22 +0000[diff] [blame]2570<p id="feat_jit_arm">The ARM backend has basic support for integer code
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2571in ARM codegen mode, but lacks NEON and full Thumb support.</p>
2572
2573</div>
2574
2575<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2576<h4 id="feat_objectwrite">.o File Writing</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2577
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2578<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2579
2580<p>This box indicates whether the target supports writing .o files (e.g. MachO,
2581ELF, and/or COFF) files directly from the target. Note that the target also
2582must include an assembly parser and general inline assembly support for full
2583inline assembly support in the .o writer.</p>
2584
Chris Lattner15597532010-10-28 02:22:02 +0000[diff] [blame]2585<p>Targets that don't support this feature can obviously still write out .o
2586files, they just rely on having an external assembler to translate from a .s
2587file to a .o file (as is the case for many C compilers).</p>
2588
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2589</div>
2590
2591<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2592<h4 id="feat_tailcall">Tail Calls</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2593
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2594<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2595
2596<p>This box indicates whether the target supports guaranteed tail calls. These
2597are calls marked "<a href="LangRef.html#i_call">tail</a>" and use the fastcc
2598calling convention. Please see the <a href="#tailcallopt">tail call section
2599more more details</a>.</p>
2600
2601</div>
2602
Rafael Espindola799ca892011-11-27 22:05:46 +0000[diff] [blame]2603<!-- _______________________________________________________________________ -->
2604<h4 id="feat_segstacks">Segmented Stacks</h4>
2605
2606<div>
2607
2608<p>This box indicates whether the target supports segmented stacks. This
2609replaces the traditional large C stack with many linked segments. It
2610is compatible with the <a href="http://gcc.gnu.org/wiki/SplitStacks">gcc
2611implementation</a> used by the Go front end.</p>
2612
Rafael Espindolac87cebf2011-11-28 17:06:58 +0000[diff] [blame]2613<p id="feat_segstacks_x86">Basic support exists on the X86 backend. Currently
2614vararg doesn't work and the object files are not marked the way the gold
Rafael Espindolab61cc442011-11-29 19:38:09 +0000[diff] [blame]2615linker expects, but simple Go programs can be built by dragonegg.</p>
Rafael Espindola799ca892011-11-27 22:05:46 +0000[diff] [blame]2616
2617</div>
2618
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2619</div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2620
2621<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2622<h3>
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]2623 <a name="tailcallopt">Tail call optimization</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2624</h3>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2625
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2626<div>
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]2627
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2628<p>Tail call optimization, callee reusing the stack of the caller, is currently
2629 supported on x86/x86-64 and PowerPC. It is performed if:</p>
2630
2631<ul>
Chris Lattnera179e4d2010-03-11 00:22:57 +0000[diff] [blame]2632 <li>Caller and callee have the calling convention <tt>fastcc</tt> or
2633 <tt>cc 10</tt> (GHC call convention).</li>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2634
2635 <li>The call is a tail call - in tail position (ret immediately follows call
2636 and ret uses value of call or is void).</li>
2637
2638 <li>Option <tt>-tailcallopt</tt> is enabled.</li>
2639
2640 <li>Platform specific constraints are met.</li>
2641</ul>
2642
2643<p>x86/x86-64 constraints:</p>
2644
2645<ul>
2646 <li>No variable argument lists are used.</li>
2647
2648 <li>On x86-64 when generating GOT/PIC code only module-local calls (visibility
2649 = hidden or protected) are supported.</li>
2650</ul>
2651
2652<p>PowerPC constraints:</p>
2653
2654<ul>
2655 <li>No variable argument lists are used.</li>
2656
2657 <li>No byval parameters are used.</li>
2658
2659 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
2660</ul>
2661
2662<p>Example:</p>
2663
2664<p>Call as <tt>llc -tailcallopt test.ll</tt>.</p>
2665
2666<div class="doc_code">
2667<pre>
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]2668declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
2669
2670define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
2671 %l1 = add i32 %in1, %in2
2672 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
2673 ret i32 %tmp
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2674}
2675</pre>
2676</div>
2677
2678<p>Implications of <tt>-tailcallopt</tt>:</p>
2679
2680<p>To support tail call optimization in situations where the callee has more
2681 arguments than the caller a 'callee pops arguments' convention is used. This
2682 currently causes each <tt>fastcc</tt> call that is not tail call optimized
2683 (because one or more of above constraints are not met) to be followed by a
2684 readjustment of the stack. So performance might be worse in such cases.</p>
2685
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]2686</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2687<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2688<h3>
Evan Cheng59676492010-03-08 21:05:02 +0000[diff] [blame]2689 <a name="sibcallopt">Sibling call optimization</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2690</h3>
Evan Cheng59676492010-03-08 21:05:02 +0000[diff] [blame]2691
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2692<div>
Evan Cheng59676492010-03-08 21:05:02 +0000[diff] [blame]2693
2694<p>Sibling call optimization is a restricted form of tail call optimization.
2695 Unlike tail call optimization described in the previous section, it can be
2696 performed automatically on any tail calls when <tt>-tailcallopt</tt> option
2697 is not specified.</p>
2698
2699<p>Sibling call optimization is currently performed on x86/x86-64 when the
2700 following constraints are met:</p>
2701
2702<ul>
2703 <li>Caller and callee have the same calling convention. It can be either
2704 <tt>c</tt> or <tt>fastcc</tt>.
2705
2706 <li>The call is a tail call - in tail position (ret immediately follows call
2707 and ret uses value of call or is void).</li>
2708
2709 <li>Caller and callee have matching return type or the callee result is not
2710 used.
2711
2712 <li>If any of the callee arguments are being passed in stack, they must be
2713 available in caller's own incoming argument stack and the frame offsets
2714 must be the same.
2715</ul>
2716
2717<p>Example:</p>
2718<div class="doc_code">
2719<pre>
2720declare i32 @bar(i32, i32)
2721
2722define i32 @foo(i32 %a, i32 %b, i32 %c) {
2723entry:
2724 %0 = tail call i32 @bar(i32 %a, i32 %b)
2725 ret i32 %0
2726}
2727</pre>
2728</div>
2729
2730</div>
2731<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2732<h3>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2733 <a name="x86">The X86 backend</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2734</h3>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2735
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2736<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2737
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]2738<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2739 code generator is capable of targeting a variety of x86-32 and x86-64
2740 processors, and includes support for ISA extensions such as MMX and SSE.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2741
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2742<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2743<h4>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2744 <a name="x86_tt">X86 Target Triples supported</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2745</h4>
Chris Lattnerde69bf92005-07-12 00:20:49 +0000[diff] [blame]2746
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2747<div>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]2748
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2749<p>The following are the known target triples that are supported by the X86
2750 backend. This is not an exhaustive list, and it would be useful to add those
2751 that people test.</p>
Chris Lattnerde69bf92005-07-12 00:20:49 +0000[diff] [blame]2752
2753<ul>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2754 <li><b>i686-pc-linux-gnu</b> &mdash; Linux</li>
2755
2756 <li><b>i386-unknown-freebsd5.3</b> &mdash; FreeBSD 5.3</li>
2757
2758 <li><b>i686-pc-cygwin</b> &mdash; Cygwin on Win32</li>
2759
2760 <li><b>i686-pc-mingw32</b> &mdash; MingW on Win32</li>
2761
2762 <li><b>i386-pc-mingw32msvc</b> &mdash; MingW crosscompiler on Linux</li>
2763
2764 <li><b>i686-apple-darwin*</b> &mdash; Apple Darwin on X86</li>
Torok Edwin4378bf02009-06-15 12:17:44 +0000[diff] [blame]2765
2766 <li><b>x86_64-unknown-linux-gnu</b> &mdash; Linux</li>
Chris Lattnerde69bf92005-07-12 00:20:49 +0000[diff] [blame]2767</ul>
2768
2769</div>
2770
2771<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2772<h4>
Anton Korobeynikov6f7072c2006-09-17 20:25:45 +0000[diff] [blame]2773 <a name="x86_cc">X86 Calling Conventions supported</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2774</h4>
Anton Korobeynikov6f7072c2006-09-17 20:25:45 +0000[diff] [blame]2775
2776
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2777<div>
Anton Korobeynikov6f7072c2006-09-17 20:25:45 +0000[diff] [blame]2778
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]2779<p>The following target-specific calling conventions are known to backend:</p>
Anton Korobeynikov6f7072c2006-09-17 20:25:45 +0000[diff] [blame]2780
2781<ul>
Chris Lattnerf98eade2011-05-22 22:28:47 +0000[diff] [blame]2782<li><b>x86_StdCall</b> &mdash; stdcall calling convention seen on Microsoft
2783 Windows platform (CC ID = 64).</li>
2784<li><b>x86_FastCall</b> &mdash; fastcall calling convention seen on Microsoft
2785 Windows platform (CC ID = 65).</li>
2786<li><b>x86_ThisCall</b> &mdash; Similar to X86_StdCall. Passes first argument
2787 in ECX, others via stack. Callee is responsible for stack cleaning. This
2788 convention is used by MSVC by default for methods in its ABI
2789 (CC ID = 70).</li>
Anton Korobeynikov6f7072c2006-09-17 20:25:45 +0000[diff] [blame]2790</ul>
2791
2792</div>
2793
2794<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2795<h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2796 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2797</h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2798
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2799<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2800
Misha Brukman37036852005-02-17 22:22:24 +0000[diff] [blame]2801<p>The x86 has a very flexible way of accessing memory. It is capable of
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2802 forming memory addresses of the following expression directly in integer
2803 instructions (which use ModR/M addressing):</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2804
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]2805<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2806<pre>
Chris Lattner10a5a6f2009-10-10 21:30:55 +0000[diff] [blame]2807SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2808</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]2809</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2810
Chris Lattner10a5a6f2009-10-10 21:30:55 +0000[diff] [blame]2811<p>In order to represent this, LLVM tracks no less than 5 operands for each
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2812 memory operand of this form. This means that the "load" form of
2813 '<tt>mov</tt>' has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2814
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2815<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2816<pre>
Chris Lattner10a5a6f2009-10-10 21:30:55 +0000[diff] [blame]2817Index: 0 | 1 2 3 4 5
2818Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
2819OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2820</pre>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2821</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2822
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2823<p>Stores, and all other instructions, treat the four memory operands in the
Chris Lattner10a5a6f2009-10-10 21:30:55 +0000[diff] [blame]2824 same way and in the same order. If the segment register is unspecified
2825 (regno = 0), then no segment override is generated. "Lea" operations do not
2826 have a segment register specified, so they only have 4 operands for their
2827 memory reference.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2828
2829</div>
2830
2831<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2832<h4>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2833 <a name="x86_memory">X86 address spaces supported</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2834</h4>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2835
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2836<div>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2837
Jay Foad1a7cc442011-04-06 07:55:30 +0000[diff] [blame]2838<p>x86 has a feature which provides
Dan Gohmand99feb82009-05-05 20:48:47 +0000[diff] [blame]2839 the ability to perform loads and stores to different address spaces
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2840 via the x86 segment registers. A segment override prefix byte on an
2841 instruction causes the instruction's memory access to go to the specified
2842 segment. LLVM address space 0 is the default address space, which includes
2843 the stack, and any unqualified memory accesses in a program. Address spaces
2844 1-255 are currently reserved for user-defined code. The GS-segment is
Chris Lattnerbe9fa502009-05-05 18:52:19 +0000[diff] [blame]2845 represented by address space 256, while the FS-segment is represented by
2846 address space 257. Other x86 segments have yet to be allocated address space
2847 numbers.</p>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2848
Dan Gohmand99feb82009-05-05 20:48:47 +0000[diff] [blame]2849<p>While these address spaces may seem similar to TLS via the
2850 <tt>thread_local</tt> keyword, and often use the same underlying hardware,
2851 there are some fundamental differences.</p>
2852
2853<p>The <tt>thread_local</tt> keyword applies to global variables and
2854 specifies that they are to be allocated in thread-local memory. There are
2855 no type qualifiers involved, and these variables can be pointed to with
2856 normal pointers and accessed with normal loads and stores.
2857 The <tt>thread_local</tt> keyword is target-independent at the LLVM IR
2858 level (though LLVM doesn't yet have implementations of it for some
2859 configurations).<p>
2860
2861<p>Special address spaces, in contrast, apply to static types. Every
2862 load and store has a particular address space in its address operand type,
2863 and this is what determines which address space is accessed.
2864 LLVM ignores these special address space qualifiers on global variables,
2865 and does not provide a way to directly allocate storage in them.
2866 At the LLVM IR level, the behavior of these special address spaces depends
2867 in part on the underlying OS or runtime environment, and they are specific
2868 to x86 (and LLVM doesn't yet handle them correctly in some cases).</p>
2869
2870<p>Some operating systems and runtime environments use (or may in the future
2871 use) the FS/GS-segment registers for various low-level purposes, so care
2872 should be taken when considering them.</p>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2873
2874</div>
2875
2876<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2877<h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2878 <a name="x86_names">Instruction naming</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2879</h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2880
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2881<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2882
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]2883<p>An instruction name consists of the base name, a default operand size, and a
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2884 a character per operand with an optional special size. For example:</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2885
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2886<div class="doc_code">
2887<pre>
2888ADD8rr -&gt; add, 8-bit register, 8-bit register
2889IMUL16rmi -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate
2890IMUL16rmi8 -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate
2891MOVSX32rm16 -&gt; movsx, 32-bit register, 16-bit memory
2892</pre>
2893</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2894
2895</div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]2896
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2897</div>
2898
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2899<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2900<h3>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2901 <a name="ppc">The PowerPC backend</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2902</h3>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2903
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2904<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2905
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2906<p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2907 code generation is retargetable to several variations or <i>subtargets</i> of
2908 the PowerPC ISA; including ppc32, ppc64 and altivec.</p>
2909
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2910<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2911<h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2912 <a name="ppc_abi">LLVM PowerPC ABI</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2913</h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2914
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2915<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2916
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2917<p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2918 relative (PIC) or static addressing for accessing global values, so no TOC
2919 (r2) is used. Second, r31 is used as a frame pointer to allow dynamic growth
2920 of a stack frame. LLVM takes advantage of having no TOC to provide space to
2921 save the frame pointer in the PowerPC linkage area of the caller frame.
2922 Other details of PowerPC ABI can be found at <a href=
2923 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
2924 >PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The 64 bit ABI
2925 is similar except space for GPRs are 8 bytes wide (not 4) and r13 is reserved
2926 for system use.</p>
2927
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2928</div>
2929
2930<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2931<h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2932 <a name="ppc_frame">Frame Layout</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2933</h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2934
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2935<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2936
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2937<p>The size of a PowerPC frame is usually fixed for the duration of a
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2938 function's invocation. Since the frame is fixed size, all references
2939 into the frame can be accessed via fixed offsets from the stack pointer. The
2940 exception to this is when dynamic alloca or variable sized arrays are
2941 present, then a base pointer (r31) is used as a proxy for the stack pointer
2942 and stack pointer is free to grow or shrink. A base pointer is also used if
2943 llvm-gcc is not passed the -fomit-frame-pointer flag. The stack pointer is
2944 always aligned to 16 bytes, so that space allocated for altivec vectors will
2945 be properly aligned.</p>
2946
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]2947<p>An invocation frame is laid out as follows (low memory at top);</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2948
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2949<table class="layout">
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2950 <tr>
2951 <td>Linkage<br><br></td>
2952 </tr>
2953 <tr>
2954 <td>Parameter area<br><br></td>
2955 </tr>
2956 <tr>
2957 <td>Dynamic area<br><br></td>
2958 </tr>
2959 <tr>
2960 <td>Locals area<br><br></td>
2961 </tr>
2962 <tr>
2963 <td>Saved registers area<br><br></td>
2964 </tr>
2965 <tr style="border-style: none hidden none hidden;">
2966 <td><br></td>
2967 </tr>
2968 <tr>
2969 <td>Previous Frame<br><br></td>
2970 </tr>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2971</table>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2972
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2973<p>The <i>linkage</i> area is used by a callee to save special registers prior
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2974 to allocating its own frame. Only three entries are relevant to LLVM. The
2975 first entry is the previous stack pointer (sp), aka link. This allows
2976 probing tools like gdb or exception handlers to quickly scan the frames in
2977 the stack. A function epilog can also use the link to pop the frame from the
2978 stack. The third entry in the linkage area is used to save the return
2979 address from the lr register. Finally, as mentioned above, the last entry is
2980 used to save the previous frame pointer (r31.) The entries in the linkage
2981 area are the size of a GPR, thus the linkage area is 24 bytes long in 32 bit
2982 mode and 48 bytes in 64 bit mode.</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2983
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2984<p>32 bit linkage area</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2985
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2986<table class="layout">
2987 <tr>
2988 <td>0</td>
2989 <td>Saved SP (r1)</td>
2990 </tr>
2991 <tr>
2992 <td>4</td>
2993 <td>Saved CR</td>
2994 </tr>
2995 <tr>
2996 <td>8</td>
2997 <td>Saved LR</td>
2998 </tr>
2999 <tr>
3000 <td>12</td>
3001 <td>Reserved</td>
3002 </tr>
3003 <tr>
3004 <td>16</td>
3005 <td>Reserved</td>
3006 </tr>
3007 <tr>
3008 <td>20</td>
3009 <td>Saved FP (r31)</td>
3010 </tr>
3011</table>
3012
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3013<p>64 bit linkage area</p>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]3014
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3015<table class="layout">
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]3016 <tr>
3017 <td>0</td>
3018 <td>Saved SP (r1)</td>
3019 </tr>
3020 <tr>
3021 <td>8</td>
3022 <td>Saved CR</td>
3023 </tr>
3024 <tr>
3025 <td>16</td>
3026 <td>Saved LR</td>
3027 </tr>
3028 <tr>
3029 <td>24</td>
3030 <td>Reserved</td>
3031 </tr>
3032 <tr>
3033 <td>32</td>
3034 <td>Reserved</td>
3035 </tr>
3036 <tr>
3037 <td>40</td>
3038 <td>Saved FP (r31)</td>
3039 </tr>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3040</table>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3041
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3042<p>The <i>parameter area</i> is used to store arguments being passed to a callee
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]3043 function. Following the PowerPC ABI, the first few arguments are actually
3044 passed in registers, with the space in the parameter area unused. However,
3045 if there are not enough registers or the callee is a thunk or vararg
3046 function, these register arguments can be spilled into the parameter area.
3047 Thus, the parameter area must be large enough to store all the parameters for
3048 the largest call sequence made by the caller. The size must also be
3049 minimally large enough to spill registers r3-r10. This allows callees blind
3050 to the call signature, such as thunks and vararg functions, enough space to
3051 cache the argument registers. Therefore, the parameter area is minimally 32
3052 bytes (64 bytes in 64 bit mode.) Also note that since the parameter area is
3053 a fixed offset from the top of the frame, that a callee can access its spilt
3054 arguments using fixed offsets from the stack pointer (or base pointer.)</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3055
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3056<p>Combining the information about the linkage, parameter areas and alignment. A
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]3057 stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
3058 mode.</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3059
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3060<p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]3061 alloca then space is added to the stack, the linkage and parameter areas are
3062 shifted to top of stack, and the new space is available immediately below the
3063 linkage and parameter areas. The cost of shifting the linkage and parameter
3064 areas is minor since only the link value needs to be copied. The link value
3065 can be easily fetched by adding the original frame size to the base pointer.
3066 Note that allocations in the dynamic space need to observe 16 byte
3067 alignment.</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3068
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3069<p>The <i>locals area</i> is where the llvm compiler reserves space for local
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]3070 variables.</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3071
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]3072<p>The <i>saved registers area</i> is where the llvm compiler spills callee
3073 saved registers on entry to the callee.</p>
3074
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3075</div>
3076
3077<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]3078<h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3079 <a name="ppc_prolog">Prolog/Epilog</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]3080</h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3081
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]3082<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]3083
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3084<p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]3085 the following exceptions. Callee saved registers are spilled after the frame
3086 is created. This allows the llvm epilog/prolog support to be common with
3087 other targets. The base pointer callee saved register r31 is saved in the
3088 TOC slot of linkage area. This simplifies allocation of space for the base
3089 pointer and makes it convenient to locate programatically and during
3090 debugging.</p>
3091
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3092</div>
3093
3094<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]3095<h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3096 <a name="ppc_dynamic">Dynamic Allocation</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]3097</h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3098
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]3099<div>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3100
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]3101<p><i>TODO - More to come.</i></p>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]3102
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]3103</div>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3104
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]3105</div>
3106
Justin Holewinski6c6a7fd2011-08-11 17:34:16 +0000[diff] [blame]3107<!-- ======================================================================= -->
3108<h3>
3109 <a name="ptx">The PTX backend</a>
3110</h3>
3111
3112<div>
3113
3114<p>The PTX code generator lives in the lib/Target/PTX directory. It is
3115 currently a work-in-progress, but already supports most of the code
3116 generation functionality needed to generate correct PTX kernels for
3117 CUDA devices.</p>
3118
3119<p>The code generator can target PTX 2.0+, and shader model 1.0+. The
3120 PTX ISA Reference Manual is used as the primary source of ISA
3121 information, though an effort is made to make the output of the code
3122 generator match the output of the NVidia nvcc compiler, whenever
3123 possible.</p>
3124
3125<p>Code Generator Options:</p>
3126<table border="1" cellspacing="0">
3127 <tr>
3128 <th>Option</th>
3129 <th>Description</th>
3130 </tr>
3131 <tr>
3132 <td><code>double</code></td>
3133 <td align="left">If enabled, the map_f64_to_f32 directive is
3134 disabled in the PTX output, allowing native double-precision
3135 arithmetic</td>
3136 </tr>
3137 <tr>
3138 <td><code>no-fma</code></td>
3139 <td align="left">Disable generation of Fused-Multiply Add
3140 instructions, which may be beneficial for some devices</td>
3141 </tr>
3142 <tr>
3143 <td><code>smxy / computexy</code></td>
3144 <td align="left">Set shader model/compute capability to x.y,
3145 e.g. sm20 or compute13</td>
3146 </tr>
3147</table>
3148
3149<p>Working:</p>
3150<ul>
3151 <li>Arithmetic instruction selection (including combo FMA)</li>
3152 <li>Bitwise instruction selection</li>
3153 <li>Control-flow instruction selection</li>
3154 <li>Function calls (only on SM 2.0+ and no return arguments)</li>
3155 <li>Addresses spaces (0 = global, 1 = constant, 2 = local, 4 =
3156 shared)</li>
3157 <li>Thread synchronization (bar.sync)</li>
3158 <li>Special register reads ([N]TID, [N]CTAID, PMx, CLOCK, etc.)</li>
3159</ul>
3160
3161<p>In Progress:</p>
3162<ul>
3163 <li>Robust call instruction selection</li>
3164 <li>Stack frame allocation</li>
3165 <li>Device-specific instruction scheduling optimizations</li>
3166</ul>
3167
3168
3169</div>
3170
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]3171</div>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3172
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]3173<!-- *********************************************************************** -->
3174<hr>
3175<address>
3176 <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
Misha Brukman86242e12008-12-11 17:34:48 +0000[diff] [blame]3177 src="http://jigsaw.w3.org/css-validator/images/vcss-blue" alt="Valid CSS"></a>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]3178 <a href="http://validator.w3.org/check/referer"><img
Misha Brukman21a63702008-12-11 18:23:24 +0000[diff] [blame]3179 src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]3180
3181 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
NAKAMURA Takumica46f5a2011-04-09 02:13:37 +0000[diff] [blame]3182 <a href="http://llvm.org/">The LLVM Compiler Infrastructure</a><br>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]3183 Last modified: $Date$
3184</address>
3185
3186</body>
3187</html>