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gerrit-public.fairphone.software / toolchain / llvm-project / 41d9ef3cedbe05b83e8c03c62aeaf01a1e52b134 / . / llvm / test / CodeGen / AArch64 / arm64-anyregcc.ll
blob: 1af3103832432eff169c3ceb12a1977cf4c12e18 [file] [log] [blame]
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]1; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
2
3; Stackmap Header: no constants - 6 callsites
4; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
5; CHECK-NEXT: __LLVM_StackMaps:
6; Header
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]7; CHECK-NEXT: .byte 2
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]8; CHECK-NEXT: .byte 0
9; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]10; Num Functions
11; CHECK-NEXT: .long 8
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]12; Num LargeConstants
13; CHECK-NEXT: .long 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]14; Num Callsites
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]15; CHECK-NEXT: .long 8
16
17; Functions and stack size
18; CHECK-NEXT: .quad _test
19; CHECK-NEXT: .quad 16
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]20; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]21; CHECK-NEXT: .quad _property_access1
22; CHECK-NEXT: .quad 16
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]23; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]24; CHECK-NEXT: .quad _property_access2
25; CHECK-NEXT: .quad 32
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]26; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]27; CHECK-NEXT: .quad _property_access3
28; CHECK-NEXT: .quad 32
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]29; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]30; CHECK-NEXT: .quad _anyreg_test1
31; CHECK-NEXT: .quad 16
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]32; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]33; CHECK-NEXT: .quad _anyreg_test2
34; CHECK-NEXT: .quad 16
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]35; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]36; CHECK-NEXT: .quad _patchpoint_spilldef
37; CHECK-NEXT: .quad 112
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]38; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]39; CHECK-NEXT: .quad _patchpoint_spillargs
40; CHECK-NEXT: .quad 128
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]41; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]42
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]43
44; test
45; CHECK-LABEL: .long L{{.*}}-_test
46; CHECK-NEXT: .short 0
47; 3 locations
48; CHECK-NEXT: .short 3
49; Loc 0: Register
50; CHECK-NEXT: .byte 1
51; CHECK-NEXT: .byte 4
52; CHECK-NEXT: .short {{[0-9]+}}
53; CHECK-NEXT: .long 0
54; Loc 1: Register
55; CHECK-NEXT: .byte 1
56; CHECK-NEXT: .byte 4
57; CHECK-NEXT: .short {{[0-9]+}}
58; CHECK-NEXT: .long 0
59; Loc 2: Constant 3
60; CHECK-NEXT: .byte 4
61; CHECK-NEXT: .byte 8
62; CHECK-NEXT: .short 0
63; CHECK-NEXT: .long 3
64define i64 @test() nounwind ssp uwtable {
65entry:
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]66 call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]67 ret i64 0
68}
69
70; property access 1 - %obj is an anyreg call argument and should therefore be in a register
71; CHECK-LABEL: .long L{{.*}}-_property_access1
72; CHECK-NEXT: .short 0
73; 2 locations
74; CHECK-NEXT: .short 2
75; Loc 0: Register <-- this is the return register
76; CHECK-NEXT: .byte 1
77; CHECK-NEXT: .byte 8
78; CHECK-NEXT: .short {{[0-9]+}}
79; CHECK-NEXT: .long 0
80; Loc 1: Register
81; CHECK-NEXT: .byte 1
82; CHECK-NEXT: .byte 8
83; CHECK-NEXT: .short {{[0-9]+}}
84; CHECK-NEXT: .long 0
85define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
86entry:
87 %f = inttoptr i64 281474417671919 to i8*
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]88 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]89 ret i64 %ret
90}
91
92; property access 2 - %obj is an anyreg call argument and should therefore be in a register
93; CHECK-LABEL: .long L{{.*}}-_property_access2
94; CHECK-NEXT: .short 0
95; 2 locations
96; CHECK-NEXT: .short 2
97; Loc 0: Register <-- this is the return register
98; CHECK-NEXT: .byte 1
99; CHECK-NEXT: .byte 8
100; CHECK-NEXT: .short {{[0-9]+}}
101; CHECK-NEXT: .long 0
102; Loc 1: Register
103; CHECK-NEXT: .byte 1
104; CHECK-NEXT: .byte 8
105; CHECK-NEXT: .short {{[0-9]+}}
106; CHECK-NEXT: .long 0
107define i64 @property_access2() nounwind ssp uwtable {
108entry:
109 %obj = alloca i64, align 8
110 %f = inttoptr i64 281474417671919 to i8*
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]111 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]112 ret i64 %ret
113}
114
115; property access 3 - %obj is a frame index
116; CHECK-LABEL: .long L{{.*}}-_property_access3
117; CHECK-NEXT: .short 0
118; 2 locations
119; CHECK-NEXT: .short 2
120; Loc 0: Register <-- this is the return register
121; CHECK-NEXT: .byte 1
122; CHECK-NEXT: .byte 8
123; CHECK-NEXT: .short {{[0-9]+}}
124; CHECK-NEXT: .long 0
125; Loc 1: Direct FP - 8
126; CHECK-NEXT: .byte 2
127; CHECK-NEXT: .byte 8
128; CHECK-NEXT: .short 29
129; CHECK-NEXT: .long -8
130define i64 @property_access3() nounwind ssp uwtable {
131entry:
132 %obj = alloca i64, align 8
133 %f = inttoptr i64 281474417671919 to i8*
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]134 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]135 ret i64 %ret
136}
137
138; anyreg_test1
139; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
140; CHECK-NEXT: .short 0
141; 14 locations
142; CHECK-NEXT: .short 14
143; Loc 0: Register <-- this is the return register
144; CHECK-NEXT: .byte 1
145; CHECK-NEXT: .byte 8
146; CHECK-NEXT: .short {{[0-9]+}}
147; CHECK-NEXT: .long 0
148; Loc 1: Register
149; CHECK-NEXT: .byte 1
150; CHECK-NEXT: .byte 8
151; CHECK-NEXT: .short {{[0-9]+}}
152; CHECK-NEXT: .long 0
153; Loc 2: Register
154; CHECK-NEXT: .byte 1
155; CHECK-NEXT: .byte 8
156; CHECK-NEXT: .short {{[0-9]+}}
157; CHECK-NEXT: .long 0
158; Loc 3: Register
159; CHECK-NEXT: .byte 1
160; CHECK-NEXT: .byte 8
161; CHECK-NEXT: .short {{[0-9]+}}
162; CHECK-NEXT: .long 0
163; Loc 4: Register
164; CHECK-NEXT: .byte 1
165; CHECK-NEXT: .byte 8
166; CHECK-NEXT: .short {{[0-9]+}}
167; CHECK-NEXT: .long 0
168; Loc 5: Register
169; CHECK-NEXT: .byte 1
170; CHECK-NEXT: .byte 8
171; CHECK-NEXT: .short {{[0-9]+}}
172; CHECK-NEXT: .long 0
173; Loc 6: Register
174; CHECK-NEXT: .byte 1
175; CHECK-NEXT: .byte 8
176; CHECK-NEXT: .short {{[0-9]+}}
177; CHECK-NEXT: .long 0
178; Loc 7: Register
179; CHECK-NEXT: .byte 1
180; CHECK-NEXT: .byte 8
181; CHECK-NEXT: .short {{[0-9]+}}
182; CHECK-NEXT: .long 0
183; Loc 8: Register
184; CHECK-NEXT: .byte 1
185; CHECK-NEXT: .byte 8
186; CHECK-NEXT: .short {{[0-9]+}}
187; CHECK-NEXT: .long 0
188; Loc 9: Register
189; CHECK-NEXT: .byte 1
190; CHECK-NEXT: .byte 8
191; CHECK-NEXT: .short {{[0-9]+}}
192; CHECK-NEXT: .long 0
193; Loc 10: Register
194; CHECK-NEXT: .byte 1
195; CHECK-NEXT: .byte 8
196; CHECK-NEXT: .short {{[0-9]+}}
197; CHECK-NEXT: .long 0
198; Loc 11: Register
199; CHECK-NEXT: .byte 1
200; CHECK-NEXT: .byte 8
201; CHECK-NEXT: .short {{[0-9]+}}
202; CHECK-NEXT: .long 0
203; Loc 12: Register
204; CHECK-NEXT: .byte 1
205; CHECK-NEXT: .byte 8
206; CHECK-NEXT: .short {{[0-9]+}}
207; CHECK-NEXT: .long 0
208; Loc 13: Register
209; CHECK-NEXT: .byte 1
210; CHECK-NEXT: .byte 8
211; CHECK-NEXT: .short {{[0-9]+}}
212; CHECK-NEXT: .long 0
213define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
214entry:
215 %f = inttoptr i64 281474417671919 to i8*
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]216 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]217 ret i64 %ret
218}
219
220; anyreg_test2
221; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
222; CHECK-NEXT: .short 0
223; 14 locations
224; CHECK-NEXT: .short 14
225; Loc 0: Register <-- this is the return register
226; CHECK-NEXT: .byte 1
227; CHECK-NEXT: .byte 8
228; CHECK-NEXT: .short {{[0-9]+}}
229; CHECK-NEXT: .long 0
230; Loc 1: Register
231; CHECK-NEXT: .byte 1
232; CHECK-NEXT: .byte 8
233; CHECK-NEXT: .short {{[0-9]+}}
234; CHECK-NEXT: .long 0
235; Loc 2: Register
236; CHECK-NEXT: .byte 1
237; CHECK-NEXT: .byte 8
238; CHECK-NEXT: .short {{[0-9]+}}
239; CHECK-NEXT: .long 0
240; Loc 3: Register
241; CHECK-NEXT: .byte 1
242; CHECK-NEXT: .byte 8
243; CHECK-NEXT: .short {{[0-9]+}}
244; CHECK-NEXT: .long 0
245; Loc 4: Register
246; CHECK-NEXT: .byte 1
247; CHECK-NEXT: .byte 8
248; CHECK-NEXT: .short {{[0-9]+}}
249; CHECK-NEXT: .long 0
250; Loc 5: Register
251; CHECK-NEXT: .byte 1
252; CHECK-NEXT: .byte 8
253; CHECK-NEXT: .short {{[0-9]+}}
254; CHECK-NEXT: .long 0
255; Loc 6: Register
256; CHECK-NEXT: .byte 1
257; CHECK-NEXT: .byte 8
258; CHECK-NEXT: .short {{[0-9]+}}
259; CHECK-NEXT: .long 0
260; Loc 7: Register
261; CHECK-NEXT: .byte 1
262; CHECK-NEXT: .byte 8
263; CHECK-NEXT: .short {{[0-9]+}}
264; CHECK-NEXT: .long 0
265; Loc 8: Register
266; CHECK-NEXT: .byte 1
267; CHECK-NEXT: .byte 8
268; CHECK-NEXT: .short {{[0-9]+}}
269; CHECK-NEXT: .long 0
270; Loc 9: Register
271; CHECK-NEXT: .byte 1
272; CHECK-NEXT: .byte 8
273; CHECK-NEXT: .short {{[0-9]+}}
274; CHECK-NEXT: .long 0
275; Loc 10: Register
276; CHECK-NEXT: .byte 1
277; CHECK-NEXT: .byte 8
278; CHECK-NEXT: .short {{[0-9]+}}
279; CHECK-NEXT: .long 0
280; Loc 11: Register
281; CHECK-NEXT: .byte 1
282; CHECK-NEXT: .byte 8
283; CHECK-NEXT: .short {{[0-9]+}}
284; CHECK-NEXT: .long 0
285; Loc 12: Register
286; CHECK-NEXT: .byte 1
287; CHECK-NEXT: .byte 8
288; CHECK-NEXT: .short {{[0-9]+}}
289; CHECK-NEXT: .long 0
290; Loc 13: Register
291; CHECK-NEXT: .byte 1
292; CHECK-NEXT: .byte 8
293; CHECK-NEXT: .short {{[0-9]+}}
294; CHECK-NEXT: .long 0
295define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
296entry:
297 %f = inttoptr i64 281474417671919 to i8*
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]298 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]299 ret i64 %ret
300}
301
302; Test spilling the return value of an anyregcc call.
303;
304; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
305;
306; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
307; CHECK-NEXT: .short 0
308; CHECK-NEXT: .short 3
309; Loc 0: Register (some register that will be spilled to the stack)
310; CHECK-NEXT: .byte 1
311; CHECK-NEXT: .byte 8
312; CHECK-NEXT: .short {{[0-9]+}}
313; CHECK-NEXT: .long 0
314; Loc 1: Register
315; CHECK-NEXT: .byte 1
316; CHECK-NEXT: .byte 8
317; CHECK-NEXT: .short {{[0-9]+}}
318; CHECK-NEXT: .long 0
319; Loc 1: Register
320; CHECK-NEXT: .byte 1
321; CHECK-NEXT: .byte 8
322; CHECK-NEXT: .short {{[0-9]+}}
323; CHECK-NEXT: .long 0
324define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
325entry:
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]326 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]327 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
328 ret i64 %result
329}
330
331; Test spilling the arguments of an anyregcc call.
332;
333; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
334;
335; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
336; CHECK-NEXT: .short 0
337; CHECK-NEXT: .short 5
338; Loc 0: Return a register
339; CHECK-NEXT: .byte 1
340; CHECK-NEXT: .byte 8
341; CHECK-NEXT: .short {{[0-9]+}}
342; CHECK-NEXT: .long 0
343; Loc 1: Arg0 in a Register
344; CHECK-NEXT: .byte 1
345; CHECK-NEXT: .byte 8
346; CHECK-NEXT: .short {{[0-9]+}}
347; CHECK-NEXT: .long 0
348; Loc 2: Arg1 in a Register
349; CHECK-NEXT: .byte 1
350; CHECK-NEXT: .byte 8
351; CHECK-NEXT: .short {{[0-9]+}}
352; CHECK-NEXT: .long 0
353; Loc 3: Arg2 spilled to FP -96
354; CHECK-NEXT: .byte 3
355; CHECK-NEXT: .byte 8
356; CHECK-NEXT: .short 29
357; CHECK-NEXT: .long -96
358; Loc 4: Arg3 spilled to FP - 88
359; CHECK-NEXT: .byte 3
360; CHECK-NEXT: .byte 8
361; CHECK-NEXT: .short 29
362; CHECK-NEXT: .long -88
363define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
364entry:
365 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]366 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]367 ret i64 %result
368}
369
370declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
371declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)