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gerrit-public.fairphone.software / toolchain / llvm-project / bc041b82d44b51a3b7da79c38e4052e28ff8011c / . / llvm / test / CodeGen / ARM / cmpxchg-weak.ll
blob: 4038528c91bc847d00729ed43553f5476863b575 [file] [log] [blame]
Tim Northover20b9f732014-06-13 16:45:52 +0000[diff] [blame]1; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
2
3define void @test_cmpxchg_weak(i32 *%addr, i32 %desired, i32 %new) {
4; CHECK-LABEL: test_cmpxchg_weak:
5
6 %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
7 %oldval = extractvalue { i32, i1 } %pair, 0
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000[diff] [blame]8; CHECK-NEXT: BB#0:
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000[diff] [blame]9; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0]
10; CHECK-NEXT: cmp [[LOADED]], r1
11; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]]
12; CHECK-NEXT: BB#1:
Tim Northoverd32f8e62016-02-22 20:55:50 +0000[diff] [blame]13; CHECK-NEXT: dmb ish
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000[diff] [blame]14; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r2, [r0]
15; CHECK-NEXT: cmp [[SUCCESS]], #0
16; CHECK-NEXT: bne [[FAILBB:LBB[0-9]+_[0-9]+]]
17; CHECK-NEXT: BB#2:
18; CHECK-NEXT: dmb ish
19; CHECK-NEXT: str r3, [r0]
20; CHECK-NEXT: bx lr
21; CHECK-NEXT: [[LDFAILBB]]:
22; CHECK-NEXT: clrex
23; CHECK-NEXT: [[FAILBB]]:
24; CHECK-NEXT: str r3, [r0]
25; CHECK-NEXT: bx lr
Tim Northover20b9f732014-06-13 16:45:52 +0000[diff] [blame]26
27 store i32 %oldval, i32* %addr
28 ret void
29}
30
31
32define i1 @test_cmpxchg_weak_to_bool(i32, i32 *%addr, i32 %desired, i32 %new) {
33; CHECK-LABEL: test_cmpxchg_weak_to_bool:
34
35 %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
36 %success = extractvalue { i32, i1 } %pair, 1
37
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000[diff] [blame]38; CHECK-NEXT: BB#0:
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000[diff] [blame]39; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1]
40; CHECK-NEXT: cmp [[LOADED]], r2
41; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]]
42; CHECK-NEXT: BB#1:
Tim Northoverd32f8e62016-02-22 20:55:50 +0000[diff] [blame]43; CHECK-NEXT: dmb ish
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000[diff] [blame]44; CHECK-NEXT: mov r0, #0
Tim Northoverd32f8e62016-02-22 20:55:50 +0000[diff] [blame]45; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r3, [r1]
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000[diff] [blame]46; CHECK-NEXT: cmp [[SUCCESS]], #0
47; CHECK-NEXT: bxne lr
48; CHECK-NEXT: dmb ish
49; CHECK-NEXT: mov r0, #1
50; CHECK-NEXT: bx lr
51; CHECK-NEXT: [[LDFAILBB]]:
52; CHECK-NEXT: clrex
53; CHECK-NEXT: mov r0, #0
54; CHECK-NEXT: bx lr
Tim Northover20b9f732014-06-13 16:45:52 +0000[diff] [blame]55
56 ret i1 %success
57}