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Nate Begeman0b71e002005-10-18 00:28:58 +00001//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
Chris Lattnerf22556d2005-08-16 17:14:42 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Chris Lattnerf22556d2005-08-16 17:14:42 +00007//
8//===----------------------------------------------------------------------===//
9//
Nate Begeman6cca84e2005-10-16 05:39:50 +000010// This file implements the PPCISelLowering class.
Chris Lattnerf22556d2005-08-16 17:14:42 +000011//
12//===----------------------------------------------------------------------===//
13
Chris Lattner6f3b9542005-10-14 23:59:06 +000014#include "PPCISelLowering.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000015#include "MCTargetDesc/PPCPredicates.h"
Jim Laskey48850c12006-11-16 22:43:37 +000016#include "PPCMachineFunctionInfo.h"
Bill Wendlingdd3fe942010-03-12 02:00:43 +000017#include "PPCPerfectShuffle.h"
Chris Lattner6f3b9542005-10-14 23:59:06 +000018#include "PPCTargetMachine.h"
Bill Schmidt22d40dc2013-05-13 19:34:37 +000019#include "PPCTargetObjectFile.h"
Owen Andersone2f23a32007-09-07 04:06:50 +000020#include "llvm/ADT/STLExtras.h"
Hal Finkel0d8db462014-05-11 19:29:11 +000021#include "llvm/ADT/StringSwitch.h"
Eric Christopher89958332014-05-31 00:07:32 +000022#include "llvm/ADT/Triple.h"
Chris Lattner4f2e4e02007-03-06 00:59:59 +000023#include "llvm/CodeGen/CallingConvLower.h"
Chris Lattnerf22556d2005-08-16 17:14:42 +000024#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner9b577f12005-08-26 21:23:58 +000026#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattnera10fff52007-12-31 04:13:23 +000027#include "llvm/CodeGen/MachineRegisterInfo.h"
Chris Lattnerf22556d2005-08-16 17:14:42 +000028#include "llvm/CodeGen/SelectionDAG.h"
Anton Korobeynikovab663a02010-02-15 22:37:53 +000029#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000030#include "llvm/IR/CallingConv.h"
31#include "llvm/IR/Constants.h"
32#include "llvm/IR/DerivedTypes.h"
33#include "llvm/IR/Function.h"
34#include "llvm/IR/Intrinsics.h"
Chris Lattnerce645542006-11-10 02:08:47 +000035#include "llvm/Support/CommandLine.h"
Torok Edwinfb8d6d52009-07-08 20:53:28 +000036#include "llvm/Support/ErrorHandling.h"
Craig Topperb25fda92012-03-17 18:46:09 +000037#include "llvm/Support/MathExtras.h"
Torok Edwinfb8d6d52009-07-08 20:53:28 +000038#include "llvm/Support/raw_ostream.h"
Craig Topperb25fda92012-03-17 18:46:09 +000039#include "llvm/Target/TargetOptions.h"
Chris Lattnerf22556d2005-08-16 17:14:42 +000040using namespace llvm;
41
Hal Finkel595817e2012-06-04 02:21:00 +000042static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
Chris Lattnerce645542006-11-10 02:08:47 +000044
Hal Finkel4e9f1a82012-06-10 19:32:29 +000045static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
47
Hal Finkel8d7fbc92013-03-15 15:27:13 +000048static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
50
Hal Finkel940ab932014-02-28 00:27:01 +000051// FIXME: Remove this once the bug has been fixed!
52extern cl::opt<bool> ANDIGlueBug;
53
Eric Christopher89958332014-05-31 00:07:32 +000054static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
Eric Christophera84189a2014-06-02 17:29:07 +000055 // If it isn't a Mach-O file then it's going to be a linux ELF
56 // object file.
Eric Christopher89958332014-05-31 00:07:32 +000057 if (TT.isOSDarwin())
Bill Wendlingbbcaa402010-03-15 21:09:38 +000058 return new TargetLoweringObjectFileMachO();
Eric Christophera84189a2014-06-02 17:29:07 +000059
60 return new PPC64LinuxTargetObjectFile();
Chris Lattner5e693ed2009-07-28 03:13:23 +000061}
62
Chris Lattner584a11a2006-11-02 01:44:04 +000063PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
Eric Christopher89958332014-05-31 00:07:32 +000064 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
Eric Christopherb1aaebe2014-06-12 22:38:18 +000065 Subtarget(*TM.getSubtargetImpl()) {
Nate Begeman4dd38312005-10-21 00:02:42 +000066 setPow2DivIsCheap();
Dale Johannesenc31eb202008-07-31 18:13:12 +000067
Chris Lattnera028e7a2005-09-27 22:18:25 +000068 // Use _setjmp/_longjmp instead of setjmp/longjmp.
Anton Korobeynikov3b7c2572006-12-10 23:12:42 +000069 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
Scott Michelcf0da6c2009-02-17 22:15:04 +000071
Chris Lattnerd10babf2010-10-10 18:34:00 +000072 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
Eric Christopherb1aaebe2014-06-12 22:38:18 +000074 bool isPPC64 = Subtarget.isPPC64();
Evan Cheng39e90022012-07-02 22:39:56 +000075 setMinStackArgumentAlignment(isPPC64 ? 8:4);
Wesley Peck527da1b2010-11-23 03:31:01 +000076
Chris Lattnerf22556d2005-08-16 17:14:42 +000077 // Set up the register classes.
Craig Topperabadc662012-04-20 06:31:50 +000078 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
Scott Michelcf0da6c2009-02-17 22:15:04 +000081
Evan Cheng5d9fd972006-10-04 00:56:09 +000082 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
Owen Anderson9f944592009-08-11 20:47:22 +000083 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
Duncan Sands95d46ef2008-01-23 20:39:46 +000085
Owen Anderson9f944592009-08-11 20:47:22 +000086 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Scott Michelcf0da6c2009-02-17 22:15:04 +000087
Chris Lattnerc9fa36d2006-11-10 23:58:45 +000088 // PowerPC has pre-inc load and store's.
Owen Anderson9f944592009-08-11 20:47:22 +000089 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
Evan Cheng36a8fbf2006-11-09 19:11:50 +000099
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000100 if (Subtarget.useCRBits()) {
Hal Finkel940ab932014-02-28 00:27:01 +0000101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
102
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000103 if (isPPC64 || Subtarget.hasFPCVT()) {
Hal Finkel6a56b212014-03-05 22:14:00 +0000104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
110 } else {
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
113 }
Hal Finkel940ab932014-02-28 00:27:01 +0000114
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
118
119 // FIXME: Remove this once the ANDI glue bug is fixed:
120 if (ANDIGlueBug)
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
122
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
129
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
131 }
132
Dale Johannesen666323e2007-10-10 01:01:31 +0000133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
Owen Anderson9f944592009-08-11 20:47:22 +0000135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
Dale Johannesenf864ac92007-10-06 01:24:11 +0000136
Roman Divacky1faf5b02012-08-16 18:19:29 +0000137 // We do not currently implement these libm ops for PowerPC.
Owen Anderson0b9b9da2011-12-08 19:32:14 +0000138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
Bill Schmidt92e26642013-04-03 13:05:44 +0000143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
Owen Anderson0b9b9da2011-12-08 19:32:14 +0000144
Chris Lattnerf22556d2005-08-16 17:14:42 +0000145 // PowerPC has no SREM/UREM instructions
Owen Anderson9f944592009-08-11 20:47:22 +0000146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
Dan Gohman71f0d7d2007-10-08 17:28:24 +0000150
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
Owen Anderson9f944592009-08-11 20:47:22 +0000152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000160
Dan Gohman482732a2007-10-11 23:21:31 +0000161 // We don't support sin/cos/sqrt/fmod/pow
Owen Anderson9f944592009-08-11 20:47:22 +0000162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
Evan Cheng0e88c7d2013-01-29 02:32:37 +0000164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
Owen Anderson9f944592009-08-11 20:47:22 +0000165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
Hal Finkel0a479ae2012-06-22 00:49:52 +0000167 setOperationAction(ISD::FMA , MVT::f64, Legal);
Owen Anderson9f944592009-08-11 20:47:22 +0000168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
Evan Cheng0e88c7d2013-01-29 02:32:37 +0000170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
Owen Anderson9f944592009-08-11 20:47:22 +0000171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
Hal Finkel0a479ae2012-06-22 00:49:52 +0000173 setOperationAction(ISD::FMA , MVT::f32, Legal);
Dale Johannesen5c94cb32008-01-18 19:55:37 +0000174
Owen Anderson9f944592009-08-11 20:47:22 +0000175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000176
Chris Lattnerf22556d2005-08-16 17:14:42 +0000177 // If we're enabling GP optimizations, use hardware square root
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000178 if (!Subtarget.hasFSQRT() &&
Hal Finkel2e103312013-04-03 04:01:11 +0000179 !(TM.Options.UnsafeFPMath &&
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
Owen Anderson9f944592009-08-11 20:47:22 +0000181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
Hal Finkel2e103312013-04-03 04:01:11 +0000182
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000183 if (!Subtarget.hasFSQRT() &&
Hal Finkel2e103312013-04-03 04:01:11 +0000184 !(TM.Options.UnsafeFPMath &&
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
Owen Anderson9f944592009-08-11 20:47:22 +0000186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000187
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000188 if (Subtarget.hasFCPSGN()) {
Hal Finkeldbc78e12013-08-19 05:01:02 +0000189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
191 } else {
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
194 }
Scott Michelcf0da6c2009-02-17 22:15:04 +0000195
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000196 if (Subtarget.hasFPRND()) {
Hal Finkelc20a08d2013-03-29 08:57:48 +0000197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
Hal Finkel2b7b2f32013-08-08 04:31:34 +0000200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
Hal Finkelc20a08d2013-03-29 08:57:48 +0000201
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
Hal Finkel2b7b2f32013-08-08 04:31:34 +0000205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
Hal Finkelc20a08d2013-03-29 08:57:48 +0000206 }
207
Nate Begeman2fba8a32006-01-14 03:14:10 +0000208 // PowerPC does not have BSWAP, CTPOP or CTTZ
Owen Anderson9f944592009-08-11 20:47:22 +0000209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
Owen Anderson9f944592009-08-11 20:47:22 +0000210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
Chandler Carruth637cc6a2011-12-13 01:56:10 +0000211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
Owen Anderson9f944592009-08-11 20:47:22 +0000213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
Owen Anderson9f944592009-08-11 20:47:22 +0000214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
Chandler Carruth637cc6a2011-12-13 01:56:10 +0000215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000217
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000218 if (Subtarget.hasPOPCNTD()) {
Hal Finkel290376d2013-04-01 15:58:15 +0000219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
Hal Finkela4d07482013-03-28 13:29:47 +0000220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
221 } else {
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
224 }
225
Nate Begeman1b8121b2006-01-11 21:21:00 +0000226 // PowerPC does not have ROTR
Owen Anderson9f944592009-08-11 20:47:22 +0000227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000229
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000230 if (!Subtarget.useCRBits()) {
Hal Finkel940ab932014-02-28 00:27:01 +0000231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
236 }
Scott Michelcf0da6c2009-02-17 22:15:04 +0000237
Chris Lattner7f1fa8e2005-08-26 17:36:52 +0000238 // PowerPC wants to turn select_cc of FP into fsel when possible.
Owen Anderson9f944592009-08-11 20:47:22 +0000239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
Nate Begemana162f202006-01-31 08:17:29 +0000241
Nate Begeman7e7f4392006-02-01 07:19:44 +0000242 // PowerPC wants to optimize integer setcc a bit
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000243 if (!Subtarget.useCRBits())
Hal Finkel940ab932014-02-28 00:27:01 +0000244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000245
Nate Begemanbb01d4f2006-03-17 01:40:33 +0000246 // PowerPC does not have BRCOND which requires SetCC
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000247 if (!Subtarget.useCRBits())
Hal Finkel940ab932014-02-28 00:27:01 +0000248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
Evan Cheng0d41d192006-10-30 08:02:39 +0000249
Owen Anderson9f944592009-08-11 20:47:22 +0000250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000251
Chris Lattnerda2e04c2005-08-31 21:09:52 +0000252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
Owen Anderson9f944592009-08-11 20:47:22 +0000253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
Nate Begeman60952142005-09-06 22:03:27 +0000254
Jim Laskey6267b2c2005-08-17 00:40:22 +0000255 // PowerPC does not have [U|S]INT_TO_FP
Owen Anderson9f944592009-08-11 20:47:22 +0000256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
Jim Laskey6267b2c2005-08-17 00:40:22 +0000258
Wesley Peck527da1b2010-11-23 03:31:01 +0000259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
Chris Lattnerc46fc242005-12-23 05:13:35 +0000263
Chris Lattner84b49d52006-04-28 21:56:10 +0000264 // We cannot sextinreg(i1). Expand to shifts.
Owen Anderson9f944592009-08-11 20:47:22 +0000265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
Jim Laskeye0008e22007-02-22 14:56:36 +0000266
Hal Finkel1996f3d2013-03-27 19:10:42 +0000267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
Hal Finkel756810f2013-03-21 21:37:52 +0000268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000275
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
Nate Begeman4e56db62005-12-10 02:36:00 +0000277 // appropriate instructions to materialize the address.
Owen Anderson9f944592009-08-11 20:47:22 +0000278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
Bob Wilsonf84f7102009-11-04 21:31:18 +0000280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Owen Anderson9f944592009-08-11 20:47:22 +0000281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
Bob Wilsonf84f7102009-11-04 21:31:18 +0000285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
Owen Anderson9f944592009-08-11 20:47:22 +0000286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000288
Nate Begemanf69d13b2008-08-11 17:36:31 +0000289 // TRAP is legal.
Owen Anderson9f944592009-08-11 20:47:22 +0000290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
Bill Wendling95e1af22008-09-17 00:30:57 +0000291
292 // TRAMPOLINE is custom lowered.
Duncan Sandsa0984362011-09-06 13:37:06 +0000293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
Bill Wendling95e1af22008-09-17 00:30:57 +0000295
Nate Begemane74795c2006-01-25 18:21:52 +0000296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
Owen Anderson9f944592009-08-11 20:47:22 +0000297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000298
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000299 if (Subtarget.isSVR4ABI()) {
Evan Cheng39e90022012-07-02 22:39:56 +0000300 if (isPPC64) {
Hal Finkele44eb282012-03-24 03:53:55 +0000301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
311 } else {
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
315 }
Roman Divacky4394e682011-06-28 15:30:42 +0000316 } else
Owen Anderson9f944592009-08-11 20:47:22 +0000317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000318
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000319 if (Subtarget.isSVR4ABI() && !isPPC64)
Roman Divackyc3825df2013-07-25 21:36:47 +0000320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
322 else
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
324
Chris Lattner5bd514d2006-01-15 09:02:48 +0000325 // Use the default implementation.
Owen Anderson9f944592009-08-11 20:47:22 +0000326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
Chris Lattnerab4df8342006-10-18 01:18:48 +0000331
Chris Lattner6961fc72006-03-26 10:06:40 +0000332 // We want to custom lower some of our intrinsics.
Owen Anderson9f944592009-08-11 20:47:22 +0000333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000334
Hal Finkel25c19922013-05-15 21:37:41 +0000335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
337
Dale Johannesen160be0f2008-11-07 22:54:33 +0000338 // Comparisons that require checking two conditions.
Owen Anderson9f944592009-08-11 20:47:22 +0000339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000351
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000352 if (Subtarget.has64BitSupport()) {
Nate Begeman0b71e002005-10-18 00:28:58 +0000353 // They also have instructions for converting between i64 and fp.
Owen Anderson9f944592009-08-11 20:47:22 +0000354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
Dale Johannesen37bc85f2009-06-04 20:53:52 +0000358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
Owen Anderson9f944592009-08-11 20:47:22 +0000360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000361
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
Hal Finkele53429a2013-03-31 01:58:02 +0000363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
Nate Begeman762bf802005-10-25 23:48:36 +0000364 } else {
Chris Lattner595088a2005-11-17 07:30:41 +0000365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
Owen Anderson9f944592009-08-11 20:47:22 +0000366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
Nate Begemane74dfbb2005-10-18 00:56:42 +0000367 }
368
Hal Finkelf6d45f22013-04-01 17:52:07 +0000369 // With the instructions enabled under FPCVT, we can do everything.
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
Hal Finkelf6d45f22013-04-01 17:52:07 +0000372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
376 }
377
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
382 }
383
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000384 if (Subtarget.use64BitRegs()) {
Chris Lattnerb1935762007-10-19 04:08:28 +0000385 // 64-bit PowerPC implementations can support i64 types directly
Craig Topperabadc662012-04-20 06:31:50 +0000386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
Nate Begeman0b71e002005-10-18 00:28:58 +0000387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
Owen Anderson9f944592009-08-11 20:47:22 +0000388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
Dan Gohman8d2ead22008-03-07 20:36:53 +0000389 // 64-bit PowerPC wants to expand i128 shifts itself.
Owen Anderson9f944592009-08-11 20:47:22 +0000390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
Nate Begeman0b71e002005-10-18 00:28:58 +0000393 } else {
Chris Lattnerb1935762007-10-19 04:08:28 +0000394 // 32-bit PowerPC wants to expand i64 shifts itself.
Owen Anderson9f944592009-08-11 20:47:22 +0000395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
Nate Begeman60952142005-09-06 22:03:27 +0000398 }
Evan Cheng19264272006-03-01 01:11:20 +0000399
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000400 if (Subtarget.hasAltivec()) {
Chris Lattnerbaa73e02006-03-31 19:52:36 +0000401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
Owen Anderson9f944592009-08-11 20:47:22 +0000403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
Duncan Sands13237ac2008-06-06 12:08:01 +0000406
Chris Lattner06a21ba2006-04-16 01:37:57 +0000407 // add/sub are legal for all supported vector VT's.
Duncan Sands13237ac2008-06-06 12:08:01 +0000408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000410
Chris Lattner95c7adc2006-04-04 17:25:31 +0000411 // We promote all shuffles to v16i8.
Duncan Sands13237ac2008-06-06 12:08:01 +0000412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
Owen Anderson9f944592009-08-11 20:47:22 +0000413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
Chris Lattner06a21ba2006-04-16 01:37:57 +0000414
415 // We promote all non-typed operations to v4i32.
Duncan Sands13237ac2008-06-06 12:08:01 +0000416 setOperationAction(ISD::AND , VT, Promote);
Owen Anderson9f944592009-08-11 20:47:22 +0000417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
Duncan Sands13237ac2008-06-06 12:08:01 +0000418 setOperationAction(ISD::OR , VT, Promote);
Owen Anderson9f944592009-08-11 20:47:22 +0000419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
Duncan Sands13237ac2008-06-06 12:08:01 +0000420 setOperationAction(ISD::XOR , VT, Promote);
Owen Anderson9f944592009-08-11 20:47:22 +0000421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
Duncan Sands13237ac2008-06-06 12:08:01 +0000422 setOperationAction(ISD::LOAD , VT, Promote);
Owen Anderson9f944592009-08-11 20:47:22 +0000423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
Duncan Sands13237ac2008-06-06 12:08:01 +0000424 setOperationAction(ISD::SELECT, VT, Promote);
Owen Anderson9f944592009-08-11 20:47:22 +0000425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
Duncan Sands13237ac2008-06-06 12:08:01 +0000426 setOperationAction(ISD::STORE, VT, Promote);
Owen Anderson9f944592009-08-11 20:47:22 +0000427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000428
Chris Lattner06a21ba2006-04-16 01:37:57 +0000429 // No other operations are legal.
Duncan Sands13237ac2008-06-06 12:08:01 +0000430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
Hal Finkele3930222013-07-08 17:30:25 +0000436 setOperationAction(ISD::FREM, VT, Expand);
Duncan Sands13237ac2008-06-06 12:08:01 +0000437 setOperationAction(ISD::FNEG, VT, Expand);
Craig Topperc8a2adf2012-11-15 08:02:19 +0000438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
Craig Topperc4343f22012-11-14 08:11:25 +0000448 setOperationAction(ISD::FFLOOR, VT, Expand);
Craig Topper61d04572012-11-15 06:51:10 +0000449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
Duncan Sands13237ac2008-06-06 12:08:01 +0000453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
Benjamin Kramerf3ad2352014-05-19 13:12:38 +0000462 setOperationAction(ISD::BSWAP, VT, Expand);
Duncan Sands13237ac2008-06-06 12:08:01 +0000463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
Chandler Carruth637cc6a2011-12-13 01:56:10 +0000465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
Duncan Sands13237ac2008-06-06 12:08:01 +0000466 setOperationAction(ISD::CTTZ, VT, Expand);
Chandler Carruth637cc6a2011-12-13 01:56:10 +0000467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
Benjamin Kramerc5071462012-12-19 15:49:14 +0000468 setOperationAction(ISD::VSELECT, VT, Expand);
Adhemerval Zanellac4182d12012-11-05 17:15:56 +0000469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
470
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
475 }
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
Chris Lattnerbaa73e02006-03-31 19:52:36 +0000479 }
480
Chris Lattner95c7adc2006-04-04 17:25:31 +0000481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
Owen Anderson9f944592009-08-11 20:47:22 +0000483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
Chris Lattner95c7adc2006-04-04 17:25:31 +0000484
Owen Anderson9f944592009-08-11 20:47:22 +0000485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
Hal Finkel940ab932014-02-28 00:27:01 +0000489 setOperationAction(ISD::SELECT, MVT::v4i32,
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000490 Subtarget.useCRBits() ? Legal : Expand);
Owen Anderson9f944592009-08-11 20:47:22 +0000491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
Adhemerval Zanella5c6e0842012-10-08 17:27:24 +0000492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
Adhemerval Zanellabdface52012-11-15 20:56:03 +0000496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000500
Craig Topperabadc662012-04-20 06:31:50 +0000501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000505
Owen Anderson9f944592009-08-11 20:47:22 +0000506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
Hal Finkel0a479ae2012-06-22 00:49:52 +0000507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
Hal Finkel2e103312013-04-03 04:01:11 +0000508
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
Hal Finkel2e103312013-04-03 04:01:11 +0000510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
512 }
513
Owen Anderson9f944592009-08-11 20:47:22 +0000514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
Chris Lattnera8713b12006-03-20 01:53:53 +0000517
Owen Anderson9f944592009-08-11 20:47:22 +0000518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000520
Owen Anderson9f944592009-08-11 20:47:22 +0000521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
Adhemerval Zanella56775e02012-10-30 13:50:19 +0000525
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
Hal Finkel21ada792013-07-08 20:00:03 +0000533
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
Hal Finkel27774d92014-03-13 07:58:58 +0000536
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000537 if (Subtarget.hasVSX()) {
Hal Finkel27774d92014-03-13 07:58:58 +0000538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
Hal Finkel82569b62014-03-27 22:22:48 +0000539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
Hal Finkel27774d92014-03-13 07:58:58 +0000540
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
546
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
548
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
551
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
554
Hal Finkel732f0f72014-03-26 12:49:28 +0000555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
560
Hal Finkel27774d92014-03-13 07:58:58 +0000561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
568
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
571
Hal Finkel9281c9a2014-03-26 18:26:30 +0000572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
574
Hal Finkeldf3e34d2014-03-26 22:58:37 +0000575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
576
Hal Finkel19be5062014-03-29 05:29:01 +0000577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
Hal Finkel27774d92014-03-13 07:58:58 +0000578
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
Hal Finkela6c8b512014-03-26 16:12:58 +0000581
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
585
Hal Finkelad801b72014-03-27 21:26:33 +0000586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
589
Hal Finkel777c9dd2014-03-29 16:04:40 +0000590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
591
Hal Finkel9281c9a2014-03-26 18:26:30 +0000592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
596
Hal Finkeldf3e34d2014-03-26 22:58:37 +0000597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
598
Hal Finkel7279f4b2014-03-26 19:13:54 +0000599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
603
Hal Finkel5c0d1452014-03-30 13:22:59 +0000604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
610
Hal Finkela6c8b512014-03-26 16:12:58 +0000611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
Hal Finkel27774d92014-03-13 07:58:58 +0000612 }
Nate Begeman3e7db9c2005-11-29 08:17:20 +0000613 }
Scott Michelcf0da6c2009-02-17 22:15:04 +0000614
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000615 if (Subtarget.has64BitSupport()) {
Hal Finkel322e41a2012-04-01 20:08:17 +0000616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
Hal Finkel70381a72012-08-04 14:10:46 +0000617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
618 }
Hal Finkel322e41a2012-04-01 20:08:17 +0000619
Eli Friedman7dfa7912011-08-29 18:23:02 +0000620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
Hal Finkel1b5ff082012-12-25 17:22:53 +0000622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
Eli Friedman7dfa7912011-08-29 18:23:02 +0000624
Duncan Sands8d6e2e12008-11-23 15:47:28 +0000625 setBooleanContents(ZeroOrOneBooleanContent);
Bill Schmidta76bf5a2013-04-23 18:49:44 +0000626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000628
Evan Cheng39e90022012-07-02 22:39:56 +0000629 if (isPPC64) {
Chris Lattner454436d2006-10-18 01:20:43 +0000630 setStackPointerRegisterToSaveRestore(PPC::X1);
Jim Laskeye0008e22007-02-22 14:56:36 +0000631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
633 } else {
Chris Lattner454436d2006-10-18 01:20:43 +0000634 setStackPointerRegisterToSaveRestore(PPC::R1);
Jim Laskeye0008e22007-02-22 14:56:36 +0000635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
637 }
Scott Michelcf0da6c2009-02-17 22:15:04 +0000638
Chris Lattnerf4184352006-03-01 04:57:39 +0000639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
Hal Finkelcf2e9082013-05-24 23:00:14 +0000641 setTargetDAGCombine(ISD::LOAD);
Chris Lattner27f53452006-03-01 05:50:56 +0000642 setTargetDAGCombine(ISD::STORE);
Chris Lattner9754d142006-04-18 17:59:36 +0000643 setTargetDAGCombine(ISD::BR_CC);
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000644 if (Subtarget.useCRBits())
Hal Finkel940ab932014-02-28 00:27:01 +0000645 setTargetDAGCombine(ISD::BRCOND);
Chris Lattnera7976d32006-07-10 20:56:58 +0000646 setTargetDAGCombine(ISD::BSWAP);
Hal Finkelbc2ee4c2013-05-25 04:05:05 +0000647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
Scott Michelcf0da6c2009-02-17 22:15:04 +0000648
Hal Finkel46043ed2014-03-01 21:36:57 +0000649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
652
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000653 if (Subtarget.useCRBits()) {
Hal Finkel940ab932014-02-28 00:27:01 +0000654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
657 }
658
Hal Finkel2e103312013-04-03 04:01:11 +0000659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
663 }
664
Dale Johannesen10432e52007-10-19 00:59:18 +0000665 // Darwin long double math library functions have $LDBL128 appended.
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000666 if (Subtarget.isDarwin()) {
Duncan Sands53c954f2008-01-10 10:28:30 +0000667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
Dale Johannesen10432e52007-10-19 00:59:18 +0000668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
Duncan Sands53c954f2008-01-10 10:28:30 +0000670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
Dale Johannesenda2d8062008-09-04 00:47:13 +0000672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
Dale Johannesen10432e52007-10-19 00:59:18 +0000677 }
678
Hal Finkel940ab932014-02-28 00:27:01 +0000679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000681 if (Subtarget.useCRBits())
Hal Finkel940ab932014-02-28 00:27:01 +0000682 setHasMultipleConditionRegisters();
683
Hal Finkel65298572011-10-17 18:53:03 +0000684 setMinFunctionAlignment(2);
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000685 if (Subtarget.isDarwin())
Hal Finkel65298572011-10-17 18:53:03 +0000686 setPrefFunctionAlignment(4);
Eli Friedman2518f832011-05-06 20:34:06 +0000687
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000688 if (isPPC64 && Subtarget.isJITCodeModel())
Evan Cheng39e90022012-07-02 22:39:56 +0000689 // Temporary workaround for the inability of PPC64 JIT to handle jump
690 // tables.
691 setSupportJumpTables(false);
692
Eli Friedman30a49e92011-08-03 21:06:02 +0000693 setInsertFencesForAtomic(true);
694
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000695 if (Subtarget.enableMachineScheduler())
Hal Finkel21442b22013-09-11 23:05:25 +0000696 setSchedulingPreference(Sched::Source);
697 else
698 setSchedulingPreference(Sched::Hybrid);
Hal Finkel6f0ae782011-11-22 16:21:04 +0000699
Chris Lattnerf22556d2005-08-16 17:14:42 +0000700 computeRegisterProperties();
Hal Finkel742b5352012-08-28 16:12:39 +0000701
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000704 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
Jim Grosbach341ad3e2013-02-20 21:13:59 +0000706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
Hal Finkel742b5352012-08-28 16:12:39 +0000712
713 setPrefFunctionAlignment(4);
Hal Finkel742b5352012-08-28 16:12:39 +0000714 }
Chris Lattnerf22556d2005-08-16 17:14:42 +0000715}
716
Hal Finkel262a2242013-09-12 23:20:06 +0000717/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718/// the desired ByVal argument alignment.
719static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
722 return;
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
725 MaxAlign = 32;
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
727 MaxAlign = 16;
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
732 MaxAlign = EltAlign;
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
738 MaxAlign = EltAlign;
739 if (MaxAlign == MaxMaxAlign)
740 break;
741 }
742 }
743}
744
Dale Johannesencbde4c22008-02-28 22:31:51 +0000745/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746/// function arguments in the caller parameter area.
Chris Lattner229907c2011-07-18 04:54:35 +0000747unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
Dale Johannesencbde4c22008-02-28 22:31:51 +0000748 // Darwin passes everything on 4 byte boundary.
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000749 if (Subtarget.isDarwin())
Dale Johannesencbde4c22008-02-28 22:31:51 +0000750 return 4;
Roman Divackyb9663cc2012-04-02 15:49:30 +0000751
752 // 16byte and wider vectors are passed on 16byte boundary.
Roman Divackyb9663cc2012-04-02 15:49:30 +0000753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000754 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
756 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
Hal Finkel262a2242013-09-12 23:20:06 +0000757 return Align;
Dale Johannesencbde4c22008-02-28 22:31:51 +0000758}
759
Chris Lattner347ed8a2006-01-09 23:52:17 +0000760const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
761 switch (Opcode) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000762 default: return nullptr;
Evan Cheng32e376f2008-07-12 02:23:19 +0000763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
Hal Finkel2e103312013-04-03 04:01:11 +0000767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
Evan Cheng32e376f2008-07-12 02:23:19 +0000769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
Tilmann Schellerd1aaa322009-08-15 11:54:46 +0000775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
Tilmann Scheller79fef932009-12-18 13:00:15 +0000776 case PPCISD::LOAD: return "PPCISD::LOAD";
777 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
Evan Cheng32e376f2008-07-12 02:23:19 +0000778 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
779 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
780 case PPCISD::SRL: return "PPCISD::SRL";
781 case PPCISD::SRA: return "PPCISD::SRA";
782 case PPCISD::SHL: return "PPCISD::SHL";
Ulrich Weigandf62e83f2013-03-22 15:24:13 +0000783 case PPCISD::CALL: return "PPCISD::CALL";
784 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
Evan Cheng32e376f2008-07-12 02:23:19 +0000785 case PPCISD::MTCTR: return "PPCISD::MTCTR";
Ulrich Weigandf62e83f2013-03-22 15:24:13 +0000786 case PPCISD::BCTRL: return "PPCISD::BCTRL";
Evan Cheng32e376f2008-07-12 02:23:19 +0000787 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
Hal Finkel756810f2013-03-21 21:37:52 +0000788 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
789 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
Ulrich Weigandd5ebc622013-07-03 17:05:42 +0000790 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
Evan Cheng32e376f2008-07-12 02:23:19 +0000791 case PPCISD::VCMP: return "PPCISD::VCMP";
792 case PPCISD::VCMPo: return "PPCISD::VCMPo";
793 case PPCISD::LBRX: return "PPCISD::LBRX";
794 case PPCISD::STBRX: return "PPCISD::STBRX";
Evan Cheng32e376f2008-07-12 02:23:19 +0000795 case PPCISD::LARX: return "PPCISD::LARX";
796 case PPCISD::STCX: return "PPCISD::STCX";
797 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
Hal Finkel25c19922013-05-15 21:37:41 +0000798 case PPCISD::BDNZ: return "PPCISD::BDNZ";
799 case PPCISD::BDZ: return "PPCISD::BDZ";
Evan Cheng32e376f2008-07-12 02:23:19 +0000800 case PPCISD::MFFS: return "PPCISD::MFFS";
Evan Cheng32e376f2008-07-12 02:23:19 +0000801 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
Evan Cheng32e376f2008-07-12 02:23:19 +0000802 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
Hal Finkel5ab37802012-08-28 02:10:27 +0000803 case PPCISD::CR6SET: return "PPCISD::CR6SET";
804 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
Bill Schmidt34627e32012-11-27 17:35:46 +0000805 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
806 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
807 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
Roman Divacky32143e22013-12-20 18:08:54 +0000808 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
Bill Schmidt9f0b4ec2012-12-14 17:02:38 +0000809 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
810 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
Bill Schmidtca4a0c92012-12-04 16:18:08 +0000811 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
Bill Schmidtc56f1d32012-12-11 20:30:11 +0000812 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
813 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
814 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
Bill Schmidt24b8dd62012-12-12 19:29:35 +0000815 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
816 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
817 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
818 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
819 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
Bill Schmidt51e79512013-02-20 15:50:31 +0000820 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
Bill Schmidta87a7e22013-05-14 19:35:45 +0000821 case PPCISD::SC: return "PPCISD::SC";
Chris Lattner347ed8a2006-01-09 23:52:17 +0000822 }
823}
824
Matt Arsenault758659232013-05-18 00:21:46 +0000825EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
Adhemerval Zanellafe3f7932012-10-08 18:59:53 +0000826 if (!VT.isVector())
Eric Christopherb1aaebe2014-06-12 22:38:18 +0000827 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
Adhemerval Zanellafe3f7932012-10-08 18:59:53 +0000828 return VT.changeVectorElementTypeToInteger();
Scott Michela6729e82008-03-10 15:42:14 +0000829}
830
Chris Lattner4211ca92006-04-14 06:01:58 +0000831//===----------------------------------------------------------------------===//
832// Node matching predicates, for use by the tblgen matching code.
833//===----------------------------------------------------------------------===//
834
Chris Lattner7f1fa8e2005-08-26 17:36:52 +0000835/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000836static bool isFloatingPointZero(SDValue Op) {
Chris Lattner7f1fa8e2005-08-26 17:36:52 +0000837 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
Dale Johannesen3cf889f2007-08-31 04:03:46 +0000838 return CFP->getValueAPF().isZero();
Gabor Greiff304a7a2008-08-28 21:40:38 +0000839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
Chris Lattner7f1fa8e2005-08-26 17:36:52 +0000840 // Maybe this has already been legalized into the constant pool?
841 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
Dan Gohmanbcaf6812010-04-15 01:51:59 +0000842 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
Dale Johannesen3cf889f2007-08-31 04:03:46 +0000843 return CFP->getValueAPF().isZero();
Chris Lattner7f1fa8e2005-08-26 17:36:52 +0000844 }
845 return false;
846}
847
Chris Lattnere8b83b42006-04-06 17:23:16 +0000848/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
849/// true if Op is undef or if it matches the specified value.
Nate Begeman8d6d4b92009-04-27 18:41:29 +0000850static bool isConstantOrUndef(int Op, int Val) {
851 return Op < 0 || Op == Val;
Chris Lattnere8b83b42006-04-06 17:23:16 +0000852}
853
854/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
855/// VPKUHUM instruction.
Bill Schmidtf910a062014-06-10 14:35:01 +0000856bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
857 SelectionDAG &DAG) {
858 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
Chris Lattnera4bbfae2006-04-06 22:28:36 +0000859 if (!isUnary) {
860 for (unsigned i = 0; i != 16; ++i)
Bill Schmidtf910a062014-06-10 14:35:01 +0000861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
Chris Lattnera4bbfae2006-04-06 22:28:36 +0000862 return false;
863 } else {
864 for (unsigned i = 0; i != 8; ++i)
Bill Schmidtf910a062014-06-10 14:35:01 +0000865 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
866 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
Chris Lattnera4bbfae2006-04-06 22:28:36 +0000867 return false;
868 }
Chris Lattner1d338192006-04-06 18:26:28 +0000869 return true;
Chris Lattnere8b83b42006-04-06 17:23:16 +0000870}
871
872/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
873/// VPKUWUM instruction.
Bill Schmidtf910a062014-06-10 14:35:01 +0000874bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
875 SelectionDAG &DAG) {
876 unsigned j, k;
877 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
878 j = 0;
879 k = 1;
880 } else {
881 j = 2;
882 k = 3;
883 }
Chris Lattnera4bbfae2006-04-06 22:28:36 +0000884 if (!isUnary) {
885 for (unsigned i = 0; i != 16; i += 2)
Bill Schmidtf910a062014-06-10 14:35:01 +0000886 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
887 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
Chris Lattnera4bbfae2006-04-06 22:28:36 +0000888 return false;
889 } else {
890 for (unsigned i = 0; i != 8; i += 2)
Bill Schmidtf910a062014-06-10 14:35:01 +0000891 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
892 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
893 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
Chris Lattnera4bbfae2006-04-06 22:28:36 +0000895 return false;
896 }
Chris Lattner1d338192006-04-06 18:26:28 +0000897 return true;
Chris Lattnere8b83b42006-04-06 17:23:16 +0000898}
899
Chris Lattnerf38e0332006-04-06 22:02:42 +0000900/// isVMerge - Common function, used to match vmrg* shuffles.
901///
Nate Begeman8d6d4b92009-04-27 18:41:29 +0000902static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
Chris Lattnerf38e0332006-04-06 22:02:42 +0000903 unsigned LHSStart, unsigned RHSStart) {
Hal Finkeldf3e34d2014-03-26 22:58:37 +0000904 if (N->getValueType(0) != MVT::v16i8)
905 return false;
Chris Lattnerd1dcb522006-04-06 21:11:54 +0000906 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
907 "Unsupported merge size!");
Scott Michelcf0da6c2009-02-17 22:15:04 +0000908
Chris Lattnerd1dcb522006-04-06 21:11:54 +0000909 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
910 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
Nate Begeman8d6d4b92009-04-27 18:41:29 +0000911 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
Chris Lattnerf38e0332006-04-06 22:02:42 +0000912 LHSStart+j+i*UnitSize) ||
Nate Begeman8d6d4b92009-04-27 18:41:29 +0000913 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
Chris Lattnerf38e0332006-04-06 22:02:42 +0000914 RHSStart+j+i*UnitSize))
Chris Lattnerd1dcb522006-04-06 21:11:54 +0000915 return false;
916 }
Nate Begeman8d6d4b92009-04-27 18:41:29 +0000917 return true;
Chris Lattnerf38e0332006-04-06 22:02:42 +0000918}
919
920/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
Bill Schmidtf910a062014-06-10 14:35:01 +0000921/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
Wesley Peck527da1b2010-11-23 03:31:01 +0000922bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
Bill Schmidtf910a062014-06-10 14:35:01 +0000923 bool isUnary, SelectionDAG &DAG) {
924 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
925 if (!isUnary)
926 return isVMerge(N, UnitSize, 0, 16);
927 return isVMerge(N, UnitSize, 0, 0);
928 } else {
929 if (!isUnary)
930 return isVMerge(N, UnitSize, 8, 24);
931 return isVMerge(N, UnitSize, 8, 8);
932 }
Chris Lattnerd1dcb522006-04-06 21:11:54 +0000933}
934
935/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
Bill Schmidtf910a062014-06-10 14:35:01 +0000936/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
Wesley Peck527da1b2010-11-23 03:31:01 +0000937bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
Bill Schmidtf910a062014-06-10 14:35:01 +0000938 bool isUnary, SelectionDAG &DAG) {
939 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
940 if (!isUnary)
941 return isVMerge(N, UnitSize, 8, 24);
942 return isVMerge(N, UnitSize, 8, 8);
943 } else {
944 if (!isUnary)
945 return isVMerge(N, UnitSize, 0, 16);
946 return isVMerge(N, UnitSize, 0, 0);
947 }
Chris Lattnerd1dcb522006-04-06 21:11:54 +0000948}
949
950
Chris Lattner1d338192006-04-06 18:26:28 +0000951/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
952/// amount, otherwise return -1.
Bill Schmidtf910a062014-06-10 14:35:01 +0000953int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
Hal Finkeldf3e34d2014-03-26 22:58:37 +0000954 if (N->getValueType(0) != MVT::v16i8)
Hal Finkela775e512014-04-08 19:00:27 +0000955 return -1;
Nate Begeman8d6d4b92009-04-27 18:41:29 +0000956
957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
Wesley Peck527da1b2010-11-23 03:31:01 +0000958
Chris Lattner1d338192006-04-06 18:26:28 +0000959 // Find the first non-undef value in the shuffle mask.
960 unsigned i;
Nate Begeman8d6d4b92009-04-27 18:41:29 +0000961 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
Chris Lattner1d338192006-04-06 18:26:28 +0000962 /*search*/;
Scott Michelcf0da6c2009-02-17 22:15:04 +0000963
Chris Lattner1d338192006-04-06 18:26:28 +0000964 if (i == 16) return -1; // all undef.
Scott Michelcf0da6c2009-02-17 22:15:04 +0000965
Nate Begeman8d6d4b92009-04-27 18:41:29 +0000966 // Otherwise, check to see if the rest of the elements are consecutively
Chris Lattner1d338192006-04-06 18:26:28 +0000967 // numbered from this value.
Nate Begeman8d6d4b92009-04-27 18:41:29 +0000968 unsigned ShiftAmt = SVOp->getMaskElt(i);
Chris Lattner1d338192006-04-06 18:26:28 +0000969 if (ShiftAmt < i) return -1;
Chris Lattnere8b83b42006-04-06 17:23:16 +0000970
Bill Schmidtf910a062014-06-10 14:35:01 +0000971 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
972
973 ShiftAmt += i;
974
975 if (!isUnary) {
976 // Check the rest of the elements to see if they are consecutive.
977 for (++i; i != 16; ++i)
978 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
979 return -1;
980 } else {
981 // Check the rest of the elements to see if they are consecutive.
982 for (++i; i != 16; ++i)
983 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
984 return -1;
985 }
986
987 } else { // Big Endian
988
989 ShiftAmt -= i;
990
991 if (!isUnary) {
992 // Check the rest of the elements to see if they are consecutive.
993 for (++i; i != 16; ++i)
994 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
995 return -1;
996 } else {
997 // Check the rest of the elements to see if they are consecutive.
998 for (++i; i != 16; ++i)
999 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1000 return -1;
1001 }
Chris Lattnera4bbfae2006-04-06 22:28:36 +00001002 }
Chris Lattner1d338192006-04-06 18:26:28 +00001003 return ShiftAmt;
1004}
Chris Lattnerffc47562006-03-20 06:33:01 +00001005
1006/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1007/// specifies a splat of a single element that is suitable for input to
1008/// VSPLTB/VSPLTH/VSPLTW.
Nate Begeman8d6d4b92009-04-27 18:41:29 +00001009bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
Owen Anderson9f944592009-08-11 20:47:22 +00001010 assert(N->getValueType(0) == MVT::v16i8 &&
Chris Lattner95c7adc2006-04-04 17:25:31 +00001011 (EltSize == 1 || EltSize == 2 || EltSize == 4));
Scott Michelcf0da6c2009-02-17 22:15:04 +00001012
Chris Lattnera8fbb6d2006-03-20 06:37:44 +00001013 // This is a splat operation if each element of the permute is the same, and
1014 // if the value doesn't reference the second vector.
Nate Begeman8d6d4b92009-04-27 18:41:29 +00001015 unsigned ElementBase = N->getMaskElt(0);
Wesley Peck527da1b2010-11-23 03:31:01 +00001016
Nate Begeman8d6d4b92009-04-27 18:41:29 +00001017 // FIXME: Handle UNDEF elements too!
1018 if (ElementBase >= 16)
Chris Lattner95c7adc2006-04-04 17:25:31 +00001019 return false;
Scott Michelcf0da6c2009-02-17 22:15:04 +00001020
Nate Begeman8d6d4b92009-04-27 18:41:29 +00001021 // Check that the indices are consecutive, in the case of a multi-byte element
1022 // splatted with a v16i8 mask.
1023 for (unsigned i = 1; i != EltSize; ++i)
1024 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
Chris Lattner95c7adc2006-04-04 17:25:31 +00001025 return false;
Scott Michelcf0da6c2009-02-17 22:15:04 +00001026
Chris Lattner95c7adc2006-04-04 17:25:31 +00001027 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
Nate Begeman8d6d4b92009-04-27 18:41:29 +00001028 if (N->getMaskElt(i) < 0) continue;
Chris Lattner95c7adc2006-04-04 17:25:31 +00001029 for (unsigned j = 0; j != EltSize; ++j)
Nate Begeman8d6d4b92009-04-27 18:41:29 +00001030 if (N->getMaskElt(i+j) != N->getMaskElt(j))
Chris Lattner95c7adc2006-04-04 17:25:31 +00001031 return false;
Chris Lattnera8fbb6d2006-03-20 06:37:44 +00001032 }
Chris Lattner95c7adc2006-04-04 17:25:31 +00001033 return true;
Chris Lattnerffc47562006-03-20 06:33:01 +00001034}
1035
Evan Cheng581d2792007-07-30 07:51:22 +00001036/// isAllNegativeZeroVector - Returns true if all elements of build_vector
1037/// are -0.0.
1038bool PPC::isAllNegativeZeroVector(SDNode *N) {
Nate Begeman8d6d4b92009-04-27 18:41:29 +00001039 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1040
1041 APInt APVal, APUndef;
1042 unsigned BitSize;
1043 bool HasAnyUndefs;
Wesley Peck527da1b2010-11-23 03:31:01 +00001044
Dale Johannesen5f4eecf2009-11-13 01:45:18 +00001045 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
Nate Begeman8d6d4b92009-04-27 18:41:29 +00001046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
Dale Johannesen3cf889f2007-08-31 04:03:46 +00001047 return CFP->getValueAPF().isNegZero();
Nate Begeman8d6d4b92009-04-27 18:41:29 +00001048
Evan Cheng581d2792007-07-30 07:51:22 +00001049 return false;
1050}
1051
Chris Lattnerffc47562006-03-20 06:33:01 +00001052/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1053/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
Bill Schmidtf910a062014-06-10 14:35:01 +00001054unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1055 SelectionDAG &DAG) {
Nate Begeman8d6d4b92009-04-27 18:41:29 +00001056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1057 assert(isSplatShuffleMask(SVOp, EltSize));
Bill Schmidtf910a062014-06-10 14:35:01 +00001058 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1059 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1060 else
1061 return SVOp->getMaskElt(0) / EltSize;
Chris Lattnerffc47562006-03-20 06:33:01 +00001062}
1063
Chris Lattner74cf9ff2006-04-12 17:37:20 +00001064/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
Chris Lattnerd71a1f92006-04-08 06:46:53 +00001065/// by using a vspltis[bhw] instruction of the specified element size, return
1066/// the constant being splatted. The ByteSize field indicates the number of
1067/// bytes of each element [124] -> [bhw].
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001068SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
Craig Topper062a2ba2014-04-25 05:30:21 +00001069 SDValue OpVal(nullptr, 0);
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001070
1071 // If ByteSize of the splat is bigger than the element size of the
1072 // build_vector, then we have a case where we are checking for a splat where
1073 // multiple elements of the buildvector are folded together into a single
1074 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1075 unsigned EltSize = 16/N->getNumOperands();
1076 if (EltSize < ByteSize) {
1077 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001078 SDValue UniquedVals[4];
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001079 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
Scott Michelcf0da6c2009-02-17 22:15:04 +00001080
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001081 // See if all of the elements in the buildvector agree across.
1082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1083 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1084 // If the element isn't a constant, bail fully out.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001085 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001086
Scott Michelcf0da6c2009-02-17 22:15:04 +00001087
Craig Topper062a2ba2014-04-25 05:30:21 +00001088 if (!UniquedVals[i&(Multiple-1)].getNode())
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001089 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1090 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001091 return SDValue(); // no match.
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001092 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00001093
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001094 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1095 // either constant or undef values that are identical for each chunk. See
1096 // if these chunks can form into a larger vspltis*.
Scott Michelcf0da6c2009-02-17 22:15:04 +00001097
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001098 // Check to see if all of the leading entries are either 0 or -1. If
1099 // neither, then this won't fit into the immediate field.
1100 bool LeadingZero = true;
1101 bool LeadingOnes = true;
1102 for (unsigned i = 0; i != Multiple-1; ++i) {
Craig Topper062a2ba2014-04-25 05:30:21 +00001103 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
Scott Michelcf0da6c2009-02-17 22:15:04 +00001104
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001105 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1106 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1107 }
1108 // Finally, check the least significant entry.
1109 if (LeadingZero) {
Craig Topper062a2ba2014-04-25 05:30:21 +00001110 if (!UniquedVals[Multiple-1].getNode())
Owen Anderson9f944592009-08-11 20:47:22 +00001111 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
Dan Gohmaneffb8942008-09-12 16:56:44 +00001112 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001113 if (Val < 16)
Owen Anderson9f944592009-08-11 20:47:22 +00001114 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001115 }
1116 if (LeadingOnes) {
Craig Topper062a2ba2014-04-25 05:30:21 +00001117 if (!UniquedVals[Multiple-1].getNode())
Owen Anderson9f944592009-08-11 20:47:22 +00001118 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
Dan Gohman6e054832008-09-26 21:54:37 +00001119 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001120 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
Owen Anderson9f944592009-08-11 20:47:22 +00001121 return DAG.getTargetConstant(Val, MVT::i32);
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001122 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00001123
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001124 return SDValue();
Chris Lattnerd9e80f42006-04-08 07:14:26 +00001125 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00001126
Chris Lattner2771e2c2006-03-25 06:12:06 +00001127 // Check to see if this buildvec has a single non-undef value in its elements.
1128 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1129 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
Craig Topper062a2ba2014-04-25 05:30:21 +00001130 if (!OpVal.getNode())
Chris Lattner2771e2c2006-03-25 06:12:06 +00001131 OpVal = N->getOperand(i);
1132 else if (OpVal != N->getOperand(i))
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001133 return SDValue();
Chris Lattner2771e2c2006-03-25 06:12:06 +00001134 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00001135
Craig Topper062a2ba2014-04-25 05:30:21 +00001136 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
Scott Michelcf0da6c2009-02-17 22:15:04 +00001137
Eli Friedman9c6ab1a2009-05-24 02:03:36 +00001138 unsigned ValSizeInBytes = EltSize;
Nate Begeman1b392872006-03-28 04:15:58 +00001139 uint64_t Value = 0;
Chris Lattner2771e2c2006-03-25 06:12:06 +00001140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
Dan Gohmaneffb8942008-09-12 16:56:44 +00001141 Value = CN->getZExtValue();
Chris Lattner2771e2c2006-03-25 06:12:06 +00001142 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
Owen Anderson9f944592009-08-11 20:47:22 +00001143 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
Dale Johannesen3cf889f2007-08-31 04:03:46 +00001144 Value = FloatToBits(CN->getValueAPF().convertToFloat());
Chris Lattner2771e2c2006-03-25 06:12:06 +00001145 }
1146
1147 // If the splat value is larger than the element value, then we can never do
1148 // this splat. The only case that we could fit the replicated bits into our
1149 // immediate field for would be zero, and we prefer to use vxor for it.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001150 if (ValSizeInBytes < ByteSize) return SDValue();
Scott Michelcf0da6c2009-02-17 22:15:04 +00001151
Chris Lattner2771e2c2006-03-25 06:12:06 +00001152 // If the element value is larger than the splat value, cut it in half and
1153 // check to see if the two halves are equal. Continue doing this until we
1154 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1155 while (ValSizeInBytes > ByteSize) {
1156 ValSizeInBytes >>= 1;
Scott Michelcf0da6c2009-02-17 22:15:04 +00001157
Chris Lattner2771e2c2006-03-25 06:12:06 +00001158 // If the top half equals the bottom half, we're still ok.
Chris Lattner39cc7172006-04-05 17:39:25 +00001159 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1160 (Value & ((1 << (8*ValSizeInBytes))-1)))
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001161 return SDValue();
Chris Lattner2771e2c2006-03-25 06:12:06 +00001162 }
1163
1164 // Properly sign extend the value.
Richard Smith228e6d42012-08-24 23:29:28 +00001165 int MaskVal = SignExtend32(Value, ByteSize * 8);
Scott Michelcf0da6c2009-02-17 22:15:04 +00001166
Evan Chengb1ddc982006-03-26 09:52:32 +00001167 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001168 if (MaskVal == 0) return SDValue();
Chris Lattner2771e2c2006-03-25 06:12:06 +00001169
Chris Lattnerd71a1f92006-04-08 06:46:53 +00001170 // Finally, if this value fits in a 5 bit sext field, return it
Richard Smith228e6d42012-08-24 23:29:28 +00001171 if (SignExtend32<5>(MaskVal) == MaskVal)
Owen Anderson9f944592009-08-11 20:47:22 +00001172 return DAG.getTargetConstant(MaskVal, MVT::i32);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001173 return SDValue();
Chris Lattner2771e2c2006-03-25 06:12:06 +00001174}
1175
Chris Lattner4211ca92006-04-14 06:01:58 +00001176//===----------------------------------------------------------------------===//
Chris Lattnera801fced2006-11-08 02:15:41 +00001177// Addressing Mode Selection
1178//===----------------------------------------------------------------------===//
1179
1180/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1181/// or 64-bit immediate, and if the value can be accurately represented as a
1182/// sign extension from a 16-bit value. If so, this returns true and the
1183/// immediate.
1184static bool isIntS16Immediate(SDNode *N, short &Imm) {
Adam Nemet571eb5f2014-05-20 17:20:34 +00001185 if (!isa<ConstantSDNode>(N))
Chris Lattnera801fced2006-11-08 02:15:41 +00001186 return false;
Scott Michelcf0da6c2009-02-17 22:15:04 +00001187
Dan Gohmaneffb8942008-09-12 16:56:44 +00001188 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
Owen Anderson9f944592009-08-11 20:47:22 +00001189 if (N->getValueType(0) == MVT::i32)
Dan Gohmaneffb8942008-09-12 16:56:44 +00001190 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
Chris Lattnera801fced2006-11-08 02:15:41 +00001191 else
Dan Gohmaneffb8942008-09-12 16:56:44 +00001192 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
Chris Lattnera801fced2006-11-08 02:15:41 +00001193}
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001194static bool isIntS16Immediate(SDValue Op, short &Imm) {
Gabor Greiff304a7a2008-08-28 21:40:38 +00001195 return isIntS16Immediate(Op.getNode(), Imm);
Chris Lattnera801fced2006-11-08 02:15:41 +00001196}
1197
1198
1199/// SelectAddressRegReg - Given the specified addressed, check to see if it
1200/// can be represented as an indexed [r+r] operation. Returns false if it
1201/// can be more efficiently represented with [r+imm].
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001202bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1203 SDValue &Index,
Dan Gohman02b93132009-01-15 16:29:45 +00001204 SelectionDAG &DAG) const {
Chris Lattnera801fced2006-11-08 02:15:41 +00001205 short imm = 0;
1206 if (N.getOpcode() == ISD::ADD) {
1207 if (isIntS16Immediate(N.getOperand(1), imm))
1208 return false; // r+i
1209 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1210 return false; // r+i
Scott Michelcf0da6c2009-02-17 22:15:04 +00001211
Chris Lattnera801fced2006-11-08 02:15:41 +00001212 Base = N.getOperand(0);
1213 Index = N.getOperand(1);
1214 return true;
1215 } else if (N.getOpcode() == ISD::OR) {
1216 if (isIntS16Immediate(N.getOperand(1), imm))
1217 return false; // r+i can fold it if we can.
Scott Michelcf0da6c2009-02-17 22:15:04 +00001218
Chris Lattnera801fced2006-11-08 02:15:41 +00001219 // If this is an or of disjoint bitfields, we can codegen this as an add
1220 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1221 // disjoint.
Dan Gohmanf19609a2008-02-27 01:23:58 +00001222 APInt LHSKnownZero, LHSKnownOne;
1223 APInt RHSKnownZero, RHSKnownOne;
Jay Foada0653a32014-05-14 21:14:37 +00001224 DAG.computeKnownBits(N.getOperand(0),
1225 LHSKnownZero, LHSKnownOne);
Scott Michelcf0da6c2009-02-17 22:15:04 +00001226
Dan Gohmanf19609a2008-02-27 01:23:58 +00001227 if (LHSKnownZero.getBoolValue()) {
Jay Foada0653a32014-05-14 21:14:37 +00001228 DAG.computeKnownBits(N.getOperand(1),
1229 RHSKnownZero, RHSKnownOne);
Chris Lattnera801fced2006-11-08 02:15:41 +00001230 // If all of the bits are known zero on the LHS or RHS, the add won't
1231 // carry.
Dan Gohman26854f22008-02-27 21:12:32 +00001232 if (~(LHSKnownZero | RHSKnownZero) == 0) {
Chris Lattnera801fced2006-11-08 02:15:41 +00001233 Base = N.getOperand(0);
1234 Index = N.getOperand(1);
1235 return true;
1236 }
1237 }
1238 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00001239
Chris Lattnera801fced2006-11-08 02:15:41 +00001240 return false;
1241}
1242
Hal Finkeldbbf09b2013-07-09 06:34:51 +00001243// If we happen to be doing an i64 load or store into a stack slot that has
1244// less than a 4-byte alignment, then the frame-index elimination may need to
1245// use an indexed load or store instruction (because the offset may not be a
1246// multiple of 4). The extra register needed to hold the offset comes from the
1247// register scavenger, and it is possible that the scavenger will need to use
1248// an emergency spill slot. As a result, we need to make sure that a spill slot
1249// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1250// stack slot.
1251static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1252 // FIXME: This does not handle the LWA case.
1253 if (VT != MVT::i64)
1254 return;
1255
Hal Finkel7ab3db52013-07-10 15:29:01 +00001256 // NOTE: We'll exclude negative FIs here, which come from argument
1257 // lowering, because there are no known test cases triggering this problem
1258 // using packed structures (or similar). We can remove this exclusion if
1259 // we find such a test case. The reason why this is so test-case driven is
1260 // because this entire 'fixup' is only to prevent crashes (from the
1261 // register scavenger) on not-really-valid inputs. For example, if we have:
1262 // %a = alloca i1
1263 // %b = bitcast i1* %a to i64*
1264 // store i64* a, i64 b
1265 // then the store should really be marked as 'align 1', but is not. If it
1266 // were marked as 'align 1' then the indexed form would have been
1267 // instruction-selected initially, and the problem this 'fixup' is preventing
1268 // won't happen regardless.
Hal Finkeldbbf09b2013-07-09 06:34:51 +00001269 if (FrameIdx < 0)
1270 return;
1271
1272 MachineFunction &MF = DAG.getMachineFunction();
1273 MachineFrameInfo *MFI = MF.getFrameInfo();
1274
1275 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1276 if (Align >= 4)
1277 return;
1278
1279 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1280 FuncInfo->setHasNonRISpills();
1281}
1282
Chris Lattnera801fced2006-11-08 02:15:41 +00001283/// Returns true if the address N can be represented by a base register plus
1284/// a signed 16-bit displacement [r+imm], and if it is not better
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00001285/// represented as reg+reg. If Aligned is true, only accept displacements
1286/// suitable for STD and friends, i.e. multiples of 4.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001287bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
Dan Gohman02b93132009-01-15 16:29:45 +00001288 SDValue &Base,
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00001289 SelectionDAG &DAG,
1290 bool Aligned) const {
Dale Johannesenab8e4422009-02-06 19:16:40 +00001291 // FIXME dl should come from parent load or store, not from address
Andrew Trickef9de2a2013-05-25 02:42:55 +00001292 SDLoc dl(N);
Chris Lattnera801fced2006-11-08 02:15:41 +00001293 // If this can be more profitably realized as r+r, fail.
1294 if (SelectAddressRegReg(N, Disp, Base, DAG))
1295 return false;
Scott Michelcf0da6c2009-02-17 22:15:04 +00001296
Chris Lattnera801fced2006-11-08 02:15:41 +00001297 if (N.getOpcode() == ISD::ADD) {
1298 short imm = 0;
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00001299 if (isIntS16Immediate(N.getOperand(1), imm) &&
1300 (!Aligned || (imm & 3) == 0)) {
Ulrich Weigand7aa76b62013-05-16 14:53:05 +00001301 Disp = DAG.getTargetConstant(imm, N.getValueType());
Chris Lattnera801fced2006-11-08 02:15:41 +00001302 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1303 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
Hal Finkeldbbf09b2013-07-09 06:34:51 +00001304 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
Chris Lattnera801fced2006-11-08 02:15:41 +00001305 } else {
1306 Base = N.getOperand(0);
1307 }
1308 return true; // [r+i]
1309 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1310 // Match LOAD (ADD (X, Lo(G))).
Gabor Greifc8a9abe2012-04-20 11:41:38 +00001311 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
Chris Lattnera801fced2006-11-08 02:15:41 +00001312 && "Cannot handle constant offsets yet!");
1313 Disp = N.getOperand(1).getOperand(0); // The global address.
1314 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
Roman Divackye3f15c982012-06-04 17:36:38 +00001315 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
Chris Lattnera801fced2006-11-08 02:15:41 +00001316 Disp.getOpcode() == ISD::TargetConstantPool ||
1317 Disp.getOpcode() == ISD::TargetJumpTable);
1318 Base = N.getOperand(0);
1319 return true; // [&g+r]
1320 }
1321 } else if (N.getOpcode() == ISD::OR) {
1322 short imm = 0;
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00001323 if (isIntS16Immediate(N.getOperand(1), imm) &&
1324 (!Aligned || (imm & 3) == 0)) {
Chris Lattnera801fced2006-11-08 02:15:41 +00001325 // If this is an or of disjoint bitfields, we can codegen this as an add
1326 // (for better address arithmetic) if the LHS and RHS of the OR are
1327 // provably disjoint.
Dan Gohmanf19609a2008-02-27 01:23:58 +00001328 APInt LHSKnownZero, LHSKnownOne;
Jay Foada0653a32014-05-14 21:14:37 +00001329 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
Bill Wendling63061832008-03-24 23:16:37 +00001330
Dan Gohmanf19609a2008-02-27 01:23:58 +00001331 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
Chris Lattnera801fced2006-11-08 02:15:41 +00001332 // If all of the bits are known zero on the LHS or RHS, the add won't
1333 // carry.
1334 Base = N.getOperand(0);
Ulrich Weigand7aa76b62013-05-16 14:53:05 +00001335 Disp = DAG.getTargetConstant(imm, N.getValueType());
Chris Lattnera801fced2006-11-08 02:15:41 +00001336 return true;
1337 }
1338 }
1339 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1340 // Loading from a constant address.
Scott Michelcf0da6c2009-02-17 22:15:04 +00001341
Chris Lattnera801fced2006-11-08 02:15:41 +00001342 // If this address fits entirely in a 16-bit sext immediate field, codegen
1343 // this as "d, 0"
1344 short Imm;
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00001345 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
Chris Lattnera801fced2006-11-08 02:15:41 +00001346 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
Eric Christopherb1aaebe2014-06-12 22:38:18 +00001347 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
Hal Finkelf70c41e2013-03-21 23:45:03 +00001348 CN->getValueType(0));
Chris Lattnera801fced2006-11-08 02:15:41 +00001349 return true;
1350 }
Chris Lattner4a9c0bb2007-02-17 06:44:03 +00001351
1352 // Handle 32-bit sext immediates with LIS + addr mode.
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00001353 if ((CN->getValueType(0) == MVT::i32 ||
1354 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1355 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
Dan Gohmaneffb8942008-09-12 16:56:44 +00001356 int Addr = (int)CN->getZExtValue();
Scott Michelcf0da6c2009-02-17 22:15:04 +00001357
Chris Lattnera801fced2006-11-08 02:15:41 +00001358 // Otherwise, break this down into an LIS + disp.
Owen Anderson9f944592009-08-11 20:47:22 +00001359 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
Scott Michelcf0da6c2009-02-17 22:15:04 +00001360
Owen Anderson9f944592009-08-11 20:47:22 +00001361 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1362 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
Dan Gohman32f71d72009-09-25 18:54:59 +00001363 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
Chris Lattnera801fced2006-11-08 02:15:41 +00001364 return true;
1365 }
1366 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00001367
Chris Lattnera801fced2006-11-08 02:15:41 +00001368 Disp = DAG.getTargetConstant(0, getPointerTy());
Hal Finkeldbbf09b2013-07-09 06:34:51 +00001369 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
Chris Lattnera801fced2006-11-08 02:15:41 +00001370 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
Hal Finkeldbbf09b2013-07-09 06:34:51 +00001371 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1372 } else
Chris Lattnera801fced2006-11-08 02:15:41 +00001373 Base = N;
1374 return true; // [r+0]
1375}
1376
1377/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1378/// represented as an indexed [r+r] operation.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001379bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1380 SDValue &Index,
Dan Gohman02b93132009-01-15 16:29:45 +00001381 SelectionDAG &DAG) const {
Chris Lattnera801fced2006-11-08 02:15:41 +00001382 // Check to see if we can easily represent this as an [r+r] address. This
1383 // will fail if it thinks that the address is more profitably represented as
1384 // reg+imm, e.g. where imm = 0.
1385 if (SelectAddressRegReg(N, Base, Index, DAG))
1386 return true;
Scott Michelcf0da6c2009-02-17 22:15:04 +00001387
Chris Lattnera801fced2006-11-08 02:15:41 +00001388 // If the operand is an addition, always emit this as [r+r], since this is
1389 // better (for code size, and execution, as the memop does the add for free)
1390 // than emitting an explicit add.
1391 if (N.getOpcode() == ISD::ADD) {
1392 Base = N.getOperand(0);
1393 Index = N.getOperand(1);
1394 return true;
1395 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00001396
Chris Lattnera801fced2006-11-08 02:15:41 +00001397 // Otherwise, do it the hard way, using R0 as the base register.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00001398 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
Hal Finkelf70c41e2013-03-21 23:45:03 +00001399 N.getValueType());
Chris Lattnera801fced2006-11-08 02:15:41 +00001400 Index = N;
1401 return true;
1402}
1403
Chris Lattnera801fced2006-11-08 02:15:41 +00001404/// getPreIndexedAddressParts - returns true by value, base pointer and
1405/// offset pointer and addressing mode by reference if the node's address
1406/// can be legally represented as pre-indexed load / store address.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001407bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1408 SDValue &Offset,
Evan Chengb1500072006-11-09 17:55:04 +00001409 ISD::MemIndexedMode &AM,
Dan Gohman02b93132009-01-15 16:29:45 +00001410 SelectionDAG &DAG) const {
Hal Finkel595817e2012-06-04 02:21:00 +00001411 if (DisablePPCPreinc) return false;
Scott Michelcf0da6c2009-02-17 22:15:04 +00001412
Ulrich Weigande90b0222013-03-22 14:58:48 +00001413 bool isLoad = true;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001414 SDValue Ptr;
Owen Anderson53aa7a92009-08-10 22:56:29 +00001415 EVT VT;
Hal Finkelb09680b2013-03-18 23:00:58 +00001416 unsigned Alignment;
Chris Lattnera801fced2006-11-08 02:15:41 +00001417 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1418 Ptr = LD->getBasePtr();
Dan Gohman47a7d6f2008-01-30 00:15:11 +00001419 VT = LD->getMemoryVT();
Hal Finkelb09680b2013-03-18 23:00:58 +00001420 Alignment = LD->getAlignment();
Chris Lattnera801fced2006-11-08 02:15:41 +00001421 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Chris Lattner68371252006-11-14 01:38:31 +00001422 Ptr = ST->getBasePtr();
Dan Gohman47a7d6f2008-01-30 00:15:11 +00001423 VT = ST->getMemoryVT();
Hal Finkelb09680b2013-03-18 23:00:58 +00001424 Alignment = ST->getAlignment();
Ulrich Weigande90b0222013-03-22 14:58:48 +00001425 isLoad = false;
Chris Lattnera801fced2006-11-08 02:15:41 +00001426 } else
1427 return false;
1428
Chris Lattner68371252006-11-14 01:38:31 +00001429 // PowerPC doesn't have preinc load/store instructions for vectors.
Duncan Sands13237ac2008-06-06 12:08:01 +00001430 if (VT.isVector())
Chris Lattner68371252006-11-14 01:38:31 +00001431 return false;
Scott Michelcf0da6c2009-02-17 22:15:04 +00001432
Ulrich Weigande90b0222013-03-22 14:58:48 +00001433 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1434
1435 // Common code will reject creating a pre-inc form if the base pointer
1436 // is a frame index, or if N is a store and the base pointer is either
1437 // the same as or a predecessor of the value being stored. Check for
1438 // those situations here, and try with swapped Base/Offset instead.
1439 bool Swap = false;
1440
1441 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1442 Swap = true;
1443 else if (!isLoad) {
1444 SDValue Val = cast<StoreSDNode>(N)->getValue();
1445 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1446 Swap = true;
1447 }
1448
1449 if (Swap)
1450 std::swap(Base, Offset);
1451
Hal Finkelca542be2012-06-20 15:43:03 +00001452 AM = ISD::PRE_INC;
1453 return true;
Hal Finkel1cc27e42012-06-19 02:34:32 +00001454 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00001455
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00001456 // LDU/STU can only handle immediates that are a multiple of 4.
Owen Anderson9f944592009-08-11 20:47:22 +00001457 if (VT != MVT::i64) {
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00001458 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
Chris Lattner474b5b72006-11-15 19:55:13 +00001459 return false;
1460 } else {
Hal Finkelb09680b2013-03-18 23:00:58 +00001461 // LDU/STU need an address with at least 4-byte alignment.
1462 if (Alignment < 4)
1463 return false;
1464
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00001465 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
Chris Lattner474b5b72006-11-15 19:55:13 +00001466 return false;
1467 }
Chris Lattnerb314b152006-11-11 00:08:42 +00001468
Chris Lattnerb314b152006-11-11 00:08:42 +00001469 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Chris Lattner474b5b72006-11-15 19:55:13 +00001470 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1471 // sext i32 to i64 when addr mode is r+i.
Owen Anderson9f944592009-08-11 20:47:22 +00001472 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
Chris Lattnerb314b152006-11-11 00:08:42 +00001473 LD->getExtensionType() == ISD::SEXTLOAD &&
1474 isa<ConstantSDNode>(Offset))
1475 return false;
Scott Michelcf0da6c2009-02-17 22:15:04 +00001476 }
1477
Chris Lattnerce645542006-11-10 02:08:47 +00001478 AM = ISD::PRE_INC;
1479 return true;
Chris Lattnera801fced2006-11-08 02:15:41 +00001480}
1481
1482//===----------------------------------------------------------------------===//
Chris Lattner4211ca92006-04-14 06:01:58 +00001483// LowerOperation implementation
1484//===----------------------------------------------------------------------===//
1485
Chris Lattneredb9d842010-11-15 02:46:57 +00001486/// GetLabelAccessInfo - Return true if we should reference labels using a
1487/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1488static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
Craig Topper062a2ba2014-04-25 05:30:21 +00001489 unsigned &LoOpFlags,
1490 const GlobalValue *GV = nullptr) {
Ulrich Weigandd51c09f2013-06-21 14:42:20 +00001491 HiOpFlags = PPCII::MO_HA;
1492 LoOpFlags = PPCII::MO_LO;
Wesley Peck527da1b2010-11-23 03:31:01 +00001493
Chris Lattneredb9d842010-11-15 02:46:57 +00001494 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1495 // non-darwin platform. We don't support PIC on other platforms yet.
Wesley Peck527da1b2010-11-23 03:31:01 +00001496 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
Chris Lattneredb9d842010-11-15 02:46:57 +00001497 TM.getSubtarget<PPCSubtarget>().isDarwin();
Chris Lattnerdd6df842010-11-15 03:13:19 +00001498 if (isPIC) {
1499 HiOpFlags |= PPCII::MO_PIC_FLAG;
1500 LoOpFlags |= PPCII::MO_PIC_FLAG;
1501 }
1502
1503 // If this is a reference to a global value that requires a non-lazy-ptr, make
1504 // sure that instruction lowering adds it.
1505 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1506 HiOpFlags |= PPCII::MO_NLP_FLAG;
1507 LoOpFlags |= PPCII::MO_NLP_FLAG;
Wesley Peck527da1b2010-11-23 03:31:01 +00001508
Chris Lattnerdd6df842010-11-15 03:13:19 +00001509 if (GV->hasHiddenVisibility()) {
1510 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1511 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1512 }
1513 }
Wesley Peck527da1b2010-11-23 03:31:01 +00001514
Chris Lattneredb9d842010-11-15 02:46:57 +00001515 return isPIC;
1516}
1517
1518static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1519 SelectionDAG &DAG) {
1520 EVT PtrVT = HiPart.getValueType();
1521 SDValue Zero = DAG.getConstant(0, PtrVT);
Andrew Trickef9de2a2013-05-25 02:42:55 +00001522 SDLoc DL(HiPart);
Chris Lattneredb9d842010-11-15 02:46:57 +00001523
1524 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1525 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
Wesley Peck527da1b2010-11-23 03:31:01 +00001526
Chris Lattneredb9d842010-11-15 02:46:57 +00001527 // With PIC, the first instruction is actually "GR+hi(&G)".
1528 if (isPIC)
1529 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1530 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
Wesley Peck527da1b2010-11-23 03:31:01 +00001531
Chris Lattneredb9d842010-11-15 02:46:57 +00001532 // Generate non-pic code that has direct accesses to the constant pool.
1533 // The address of the global is just (hi(&g)+lo(&g)).
1534 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1535}
1536
Scott Michelcf0da6c2009-02-17 22:15:04 +00001537SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
Dan Gohman21cea8a2010-04-17 15:26:15 +00001538 SelectionDAG &DAG) const {
Owen Anderson53aa7a92009-08-10 22:56:29 +00001539 EVT PtrVT = Op.getValueType();
Chris Lattner4211ca92006-04-14 06:01:58 +00001540 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Dan Gohmanbcaf6812010-04-15 01:51:59 +00001541 const Constant *C = CP->getConstVal();
Chris Lattner4211ca92006-04-14 06:01:58 +00001542
Roman Divackyace47072012-08-24 16:26:02 +00001543 // 64-bit SVR4 ABI code is always position-independent.
1544 // The actual address of the GlobalValue is stored in the TOC.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00001545 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
Roman Divackyace47072012-08-24 16:26:02 +00001546 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
Andrew Trickef9de2a2013-05-25 02:42:55 +00001547 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
Roman Divackyace47072012-08-24 16:26:02 +00001548 DAG.getRegister(PPC::X2, MVT::i64));
1549 }
1550
Chris Lattneredb9d842010-11-15 02:46:57 +00001551 unsigned MOHiFlag, MOLoFlag;
1552 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1553 SDValue CPIHi =
1554 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1555 SDValue CPILo =
1556 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1557 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
Chris Lattner4211ca92006-04-14 06:01:58 +00001558}
1559
Dan Gohman21cea8a2010-04-17 15:26:15 +00001560SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
Owen Anderson53aa7a92009-08-10 22:56:29 +00001561 EVT PtrVT = Op.getValueType();
Nate Begeman4ca2ea52006-04-22 18:53:45 +00001562 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Wesley Peck527da1b2010-11-23 03:31:01 +00001563
Roman Divackyace47072012-08-24 16:26:02 +00001564 // 64-bit SVR4 ABI code is always position-independent.
1565 // The actual address of the GlobalValue is stored in the TOC.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00001566 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
Roman Divackyace47072012-08-24 16:26:02 +00001567 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
Andrew Trickef9de2a2013-05-25 02:42:55 +00001568 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
Roman Divackyace47072012-08-24 16:26:02 +00001569 DAG.getRegister(PPC::X2, MVT::i64));
1570 }
1571
Chris Lattneredb9d842010-11-15 02:46:57 +00001572 unsigned MOHiFlag, MOLoFlag;
1573 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1574 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1575 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1576 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
Lauro Ramos Venancio09d73c02007-07-11 17:19:51 +00001577}
1578
Dan Gohman21cea8a2010-04-17 15:26:15 +00001579SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1580 SelectionDAG &DAG) const {
Bob Wilsonf84f7102009-11-04 21:31:18 +00001581 EVT PtrVT = Op.getValueType();
Bob Wilsonf84f7102009-11-04 21:31:18 +00001582
Dan Gohmanbcaf6812010-04-15 01:51:59 +00001583 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
Wesley Peck527da1b2010-11-23 03:31:01 +00001584
Chris Lattneredb9d842010-11-15 02:46:57 +00001585 unsigned MOHiFlag, MOLoFlag;
1586 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
Michael Liaoabb87d42012-09-12 21:43:09 +00001587 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1588 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
Chris Lattneredb9d842010-11-15 02:46:57 +00001589 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1590}
1591
Roman Divackye3f15c982012-06-04 17:36:38 +00001592SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1593 SelectionDAG &DAG) const {
1594
Bill Schmidtbdae03f2013-09-17 20:22:05 +00001595 // FIXME: TLS addresses currently use medium model code sequences,
1596 // which is the most useful form. Eventually support for small and
1597 // large models could be added if users need it, at the cost of
1598 // additional complexity.
Roman Divackye3f15c982012-06-04 17:36:38 +00001599 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
Andrew Trickef9de2a2013-05-25 02:42:55 +00001600 SDLoc dl(GA);
Roman Divackye3f15c982012-06-04 17:36:38 +00001601 const GlobalValue *GV = GA->getGlobal();
1602 EVT PtrVT = getPointerTy();
Eric Christopherb1aaebe2014-06-12 22:38:18 +00001603 bool is64bit = Subtarget.isPPC64();
Roman Divackye3f15c982012-06-04 17:36:38 +00001604
Bill Schmidtca4a0c92012-12-04 16:18:08 +00001605 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
Roman Divackye3f15c982012-06-04 17:36:38 +00001606
Bill Schmidtca4a0c92012-12-04 16:18:08 +00001607 if (Model == TLSModel::LocalExec) {
1608 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Ulrich Weigandd51c09f2013-06-21 14:42:20 +00001609 PPCII::MO_TPREL_HA);
Bill Schmidtca4a0c92012-12-04 16:18:08 +00001610 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Ulrich Weigandd51c09f2013-06-21 14:42:20 +00001611 PPCII::MO_TPREL_LO);
Bill Schmidtca4a0c92012-12-04 16:18:08 +00001612 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1613 is64bit ? MVT::i64 : MVT::i32);
1614 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1615 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1616 }
Roman Divackye3f15c982012-06-04 17:36:38 +00001617
Bill Schmidtc56f1d32012-12-11 20:30:11 +00001618 if (Model == TLSModel::InitialExec) {
Bill Schmidt732eb912012-12-13 18:45:54 +00001619 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
Ulrich Weigand5b427592013-07-05 12:22:36 +00001620 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1621 PPCII::MO_TLS);
Roman Divacky32143e22013-12-20 18:08:54 +00001622 SDValue GOTPtr;
1623 if (is64bit) {
1624 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1625 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1626 PtrVT, GOTReg, TGA);
1627 } else
1628 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
Bill Schmidt9f0b4ec2012-12-14 17:02:38 +00001629 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
Roman Divacky32143e22013-12-20 18:08:54 +00001630 PtrVT, TGA, GOTPtr);
Ulrich Weigand5b427592013-07-05 12:22:36 +00001631 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
Bill Schmidtc56f1d32012-12-11 20:30:11 +00001632 }
Bill Schmidtca4a0c92012-12-04 16:18:08 +00001633
Bill Schmidtc56f1d32012-12-11 20:30:11 +00001634 if (Model == TLSModel::GeneralDynamic) {
1635 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1636 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1637 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1638 GOTReg, TGA);
1639 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1640 GOTEntryHi, TGA);
1641
1642 // We need a chain node, and don't have one handy. The underlying
1643 // call has no side effects, so using the function entry node
1644 // suffices.
1645 SDValue Chain = DAG.getEntryNode();
1646 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1647 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1648 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1649 PtrVT, ParmReg, TGA);
Bill Schmidt24b8dd62012-12-12 19:29:35 +00001650 // The return value from GET_TLS_ADDR really is in X3 already, but
1651 // some hacks are needed here to tie everything together. The extra
1652 // copies dissolve during subsequent transforms.
Bill Schmidtc56f1d32012-12-11 20:30:11 +00001653 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1654 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1655 }
1656
Bill Schmidt24b8dd62012-12-12 19:29:35 +00001657 if (Model == TLSModel::LocalDynamic) {
1658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1659 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1660 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1661 GOTReg, TGA);
1662 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1663 GOTEntryHi, TGA);
1664
1665 // We need a chain node, and don't have one handy. The underlying
1666 // call has no side effects, so using the function entry node
1667 // suffices.
1668 SDValue Chain = DAG.getEntryNode();
1669 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1670 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1671 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1672 PtrVT, ParmReg, TGA);
1673 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1674 // some hacks are needed here to tie everything together. The extra
1675 // copies dissolve during subsequent transforms.
1676 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1677 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
Bill Schmidt9ed4dbc2012-12-13 20:57:10 +00001678 Chain, ParmReg, TGA);
Bill Schmidt24b8dd62012-12-12 19:29:35 +00001679 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1680 }
1681
1682 llvm_unreachable("Unknown TLS model!");
Roman Divackye3f15c982012-06-04 17:36:38 +00001683}
1684
Chris Lattneredb9d842010-11-15 02:46:57 +00001685SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1686 SelectionDAG &DAG) const {
1687 EVT PtrVT = Op.getValueType();
1688 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
Andrew Trickef9de2a2013-05-25 02:42:55 +00001689 SDLoc DL(GSDN);
Chris Lattneredb9d842010-11-15 02:46:57 +00001690 const GlobalValue *GV = GSDN->getGlobal();
1691
Chris Lattneredb9d842010-11-15 02:46:57 +00001692 // 64-bit SVR4 ABI code is always position-independent.
1693 // The actual address of the GlobalValue is stored in the TOC.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00001694 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
Chris Lattneredb9d842010-11-15 02:46:57 +00001695 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1696 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1697 DAG.getRegister(PPC::X2, MVT::i64));
1698 }
1699
Chris Lattnerdd6df842010-11-15 03:13:19 +00001700 unsigned MOHiFlag, MOLoFlag;
1701 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
Chris Lattneredb9d842010-11-15 02:46:57 +00001702
Chris Lattnerdd6df842010-11-15 03:13:19 +00001703 SDValue GAHi =
1704 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1705 SDValue GALo =
1706 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
Wesley Peck527da1b2010-11-23 03:31:01 +00001707
Chris Lattnerdd6df842010-11-15 03:13:19 +00001708 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
Bob Wilsonf84f7102009-11-04 21:31:18 +00001709
Chris Lattnerdd6df842010-11-15 03:13:19 +00001710 // If the global reference is actually to a non-lazy-pointer, we have to do an
1711 // extra load to get the address of the global.
1712 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1713 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00001714 false, false, false, 0);
Chris Lattnerdd6df842010-11-15 03:13:19 +00001715 return Ptr;
Chris Lattner4211ca92006-04-14 06:01:58 +00001716}
1717
Dan Gohman21cea8a2010-04-17 15:26:15 +00001718SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
Chris Lattner4211ca92006-04-14 06:01:58 +00001719 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
Andrew Trickef9de2a2013-05-25 02:42:55 +00001720 SDLoc dl(Op);
Scott Michelcf0da6c2009-02-17 22:15:04 +00001721
Hal Finkel777c9dd2014-03-29 16:04:40 +00001722 if (Op.getValueType() == MVT::v2i64) {
1723 // When the operands themselves are v2i64 values, we need to do something
1724 // special because VSX has no underlying comparison operations for these.
1725 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1726 // Equality can be handled by casting to the legal type for Altivec
1727 // comparisons, everything else needs to be expanded.
1728 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1729 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1730 DAG.getSetCC(dl, MVT::v4i32,
1731 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1732 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1733 CC));
1734 }
1735
1736 return SDValue();
1737 }
1738
1739 // We handle most of these in the usual way.
1740 return Op;
1741 }
1742
Chris Lattner4211ca92006-04-14 06:01:58 +00001743 // If we're comparing for equality to zero, expose the fact that this is
1744 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1745 // fold the new nodes.
1746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1747 if (C->isNullValue() && CC == ISD::SETEQ) {
Owen Anderson53aa7a92009-08-10 22:56:29 +00001748 EVT VT = Op.getOperand(0).getValueType();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001749 SDValue Zext = Op.getOperand(0);
Owen Anderson9f944592009-08-11 20:47:22 +00001750 if (VT.bitsLT(MVT::i32)) {
1751 VT = MVT::i32;
Dale Johannesenf2bb6f02009-02-04 01:48:28 +00001752 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
Scott Michelcf0da6c2009-02-17 22:15:04 +00001753 }
Duncan Sands13237ac2008-06-06 12:08:01 +00001754 unsigned Log2b = Log2_32(VT.getSizeInBits());
Dale Johannesenf2bb6f02009-02-04 01:48:28 +00001755 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1756 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
Owen Anderson9f944592009-08-11 20:47:22 +00001757 DAG.getConstant(Log2b, MVT::i32));
1758 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
Chris Lattner4211ca92006-04-14 06:01:58 +00001759 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00001760 // Leave comparisons against 0 and -1 alone for now, since they're usually
Chris Lattner4211ca92006-04-14 06:01:58 +00001761 // optimized. FIXME: revisit this when we can custom lower all setcc
1762 // optimizations.
1763 if (C->isAllOnesValue() || C->isNullValue())
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001764 return SDValue();
Chris Lattner4211ca92006-04-14 06:01:58 +00001765 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00001766
Chris Lattner4211ca92006-04-14 06:01:58 +00001767 // If we have an integer seteq/setne, turn it into a compare against zero
Chris Lattner97ff46b2006-11-14 05:28:08 +00001768 // by xor'ing the rhs with the lhs, which is faster than setting a
1769 // condition register, reading it back out, and masking the correct bit. The
1770 // normal approach here uses sub to do this instead of xor. Using xor exposes
1771 // the result to other bit-twiddling opportunities.
Owen Anderson53aa7a92009-08-10 22:56:29 +00001772 EVT LHSVT = Op.getOperand(0).getValueType();
Duncan Sands13237ac2008-06-06 12:08:01 +00001773 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
Owen Anderson53aa7a92009-08-10 22:56:29 +00001774 EVT VT = Op.getValueType();
Scott Michelcf0da6c2009-02-17 22:15:04 +00001775 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
Chris Lattner4211ca92006-04-14 06:01:58 +00001776 Op.getOperand(1));
Dale Johannesenf2bb6f02009-02-04 01:48:28 +00001777 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
Chris Lattner4211ca92006-04-14 06:01:58 +00001778 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001779 return SDValue();
Chris Lattner4211ca92006-04-14 06:01:58 +00001780}
1781
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001782SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +00001783 const PPCSubtarget &Subtarget) const {
Roman Divacky4394e682011-06-28 15:30:42 +00001784 SDNode *Node = Op.getNode();
1785 EVT VT = Node->getValueType(0);
1786 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1787 SDValue InChain = Node->getOperand(0);
1788 SDValue VAListPtr = Node->getOperand(1);
1789 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
Andrew Trickef9de2a2013-05-25 02:42:55 +00001790 SDLoc dl(Node);
Scott Michelcf0da6c2009-02-17 22:15:04 +00001791
Roman Divacky4394e682011-06-28 15:30:42 +00001792 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1793
1794 // gpr_index
1795 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1796 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1797 false, false, 0);
1798 InChain = GprIndex.getValue(1);
1799
1800 if (VT == MVT::i64) {
1801 // Check if GprIndex is even
1802 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1803 DAG.getConstant(1, MVT::i32));
1804 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1805 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1806 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1807 DAG.getConstant(1, MVT::i32));
1808 // Align GprIndex to be even if it isn't
1809 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1810 GprIndex);
1811 }
1812
1813 // fpr index is 1 byte after gpr
1814 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1815 DAG.getConstant(1, MVT::i32));
1816
1817 // fpr
1818 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1819 FprPtr, MachinePointerInfo(SV), MVT::i8,
1820 false, false, 0);
1821 InChain = FprIndex.getValue(1);
1822
1823 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1824 DAG.getConstant(8, MVT::i32));
1825
1826 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1827 DAG.getConstant(4, MVT::i32));
1828
1829 // areas
1830 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
Pete Cooper82cd9e82011-11-08 18:42:53 +00001831 MachinePointerInfo(), false, false,
1832 false, 0);
Roman Divacky4394e682011-06-28 15:30:42 +00001833 InChain = OverflowArea.getValue(1);
1834
1835 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
Pete Cooper82cd9e82011-11-08 18:42:53 +00001836 MachinePointerInfo(), false, false,
1837 false, 0);
Roman Divacky4394e682011-06-28 15:30:42 +00001838 InChain = RegSaveArea.getValue(1);
1839
1840 // select overflow_area if index > 8
1841 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1842 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1843
Roman Divacky4394e682011-06-28 15:30:42 +00001844 // adjustment constant gpr_index * 4/8
1845 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1846 VT.isInteger() ? GprIndex : FprIndex,
1847 DAG.getConstant(VT.isInteger() ? 4 : 8,
1848 MVT::i32));
1849
1850 // OurReg = RegSaveArea + RegConstant
1851 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1852 RegConstant);
1853
1854 // Floating types are 32 bytes into RegSaveArea
1855 if (VT.isFloatingPoint())
1856 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1857 DAG.getConstant(32, MVT::i32));
1858
1859 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1860 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1861 VT.isInteger() ? GprIndex : FprIndex,
1862 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1863 MVT::i32));
1864
1865 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1866 VT.isInteger() ? VAListPtr : FprPtr,
1867 MachinePointerInfo(SV),
1868 MVT::i8, false, false, 0);
1869
1870 // determine if we should load from reg_save_area or overflow_area
1871 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1872
1873 // increase overflow_area by 4/8 if gpr/fpr > 8
1874 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1875 DAG.getConstant(VT.isInteger() ? 4 : 8,
1876 MVT::i32));
1877
1878 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1879 OverflowAreaPlusN);
1880
1881 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1882 OverflowAreaPtr,
1883 MachinePointerInfo(),
1884 MVT::i32, false, false, 0);
1885
NAKAMURA Takumi8ad54e02012-08-30 15:52:23 +00001886 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00001887 false, false, false, 0);
Nicolas Geoffray23710a72007-04-03 13:59:52 +00001888}
1889
Roman Divackyc3825df2013-07-25 21:36:47 +00001890SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1891 const PPCSubtarget &Subtarget) const {
1892 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1893
1894 // We have to copy the entire va_list struct:
1895 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1896 return DAG.getMemcpy(Op.getOperand(0), Op,
1897 Op.getOperand(1), Op.getOperand(2),
1898 DAG.getConstant(12, MVT::i32), 8, false, true,
1899 MachinePointerInfo(), MachinePointerInfo());
1900}
1901
Duncan Sandsa0984362011-09-06 13:37:06 +00001902SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1903 SelectionDAG &DAG) const {
1904 return Op.getOperand(0);
1905}
1906
1907SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1908 SelectionDAG &DAG) const {
Bill Wendling95e1af22008-09-17 00:30:57 +00001909 SDValue Chain = Op.getOperand(0);
1910 SDValue Trmp = Op.getOperand(1); // trampoline
1911 SDValue FPtr = Op.getOperand(2); // nested function
1912 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
Andrew Trickef9de2a2013-05-25 02:42:55 +00001913 SDLoc dl(Op);
Bill Wendling95e1af22008-09-17 00:30:57 +00001914
Owen Anderson53aa7a92009-08-10 22:56:29 +00001915 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Owen Anderson9f944592009-08-11 20:47:22 +00001916 bool isPPC64 = (PtrVT == MVT::i64);
Chris Lattner229907c2011-07-18 04:54:35 +00001917 Type *IntPtrTy =
Micah Villmowcdfe20b2012-10-08 16:38:25 +00001918 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
Chandler Carruth7ec50852012-11-01 08:07:29 +00001919 *DAG.getContext());
Bill Wendling95e1af22008-09-17 00:30:57 +00001920
Scott Michelcf0da6c2009-02-17 22:15:04 +00001921 TargetLowering::ArgListTy Args;
Bill Wendling95e1af22008-09-17 00:30:57 +00001922 TargetLowering::ArgListEntry Entry;
1923
1924 Entry.Ty = IntPtrTy;
1925 Entry.Node = Trmp; Args.push_back(Entry);
1926
1927 // TrampSize == (isPPC64 ? 48 : 40);
1928 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
Owen Anderson9f944592009-08-11 20:47:22 +00001929 isPPC64 ? MVT::i64 : MVT::i32);
Bill Wendling95e1af22008-09-17 00:30:57 +00001930 Args.push_back(Entry);
1931
1932 Entry.Node = FPtr; Args.push_back(Entry);
1933 Entry.Node = Nest; Args.push_back(Entry);
Scott Michelcf0da6c2009-02-17 22:15:04 +00001934
Bill Wendling95e1af22008-09-17 00:30:57 +00001935 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
Saleem Abdulrasoolf3a5a5c2014-05-17 21:50:17 +00001936 TargetLowering::CallLoweringInfo CLI(DAG);
1937 CLI.setDebugLoc(dl).setChain(Chain)
1938 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
Juergen Ributzka3bd03c72014-07-01 22:01:54 +00001939 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1940 std::move(Args), 0);
Bill Wendling95e1af22008-09-17 00:30:57 +00001941
Saleem Abdulrasoolf3a5a5c2014-05-17 21:50:17 +00001942 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
Duncan Sandsa0984362011-09-06 13:37:06 +00001943 return CallResult.second;
Bill Wendling95e1af22008-09-17 00:30:57 +00001944}
1945
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00001946SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +00001947 const PPCSubtarget &Subtarget) const {
Dan Gohman31ae5862010-04-17 14:41:14 +00001948 MachineFunction &MF = DAG.getMachineFunction();
1949 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1950
Andrew Trickef9de2a2013-05-25 02:42:55 +00001951 SDLoc dl(Op);
Nicolas Geoffray23710a72007-04-03 13:59:52 +00001952
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00001953 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
Nicolas Geoffray23710a72007-04-03 13:59:52 +00001954 // vastart just stores the address of the VarArgsFrameIndex slot into the
1955 // memory location argument.
Owen Anderson53aa7a92009-08-10 22:56:29 +00001956 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Dan Gohman31ae5862010-04-17 14:41:14 +00001957 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
Dan Gohman2d489b52008-02-06 22:27:42 +00001958 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Chris Lattner676c61d2010-09-21 18:41:36 +00001959 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1960 MachinePointerInfo(SV),
David Greene87a5abe2010-02-15 16:56:53 +00001961 false, false, 0);
Nicolas Geoffray23710a72007-04-03 13:59:52 +00001962 }
1963
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00001964 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
Nicolas Geoffray23710a72007-04-03 13:59:52 +00001965 // We suppose the given va_list is already allocated.
1966 //
1967 // typedef struct {
1968 // char gpr; /* index into the array of 8 GPRs
1969 // * stored in the register save area
1970 // * gpr=0 corresponds to r3,
1971 // * gpr=1 to r4, etc.
1972 // */
1973 // char fpr; /* index into the array of 8 FPRs
1974 // * stored in the register save area
1975 // * fpr=0 corresponds to f1,
1976 // * fpr=1 to f2, etc.
1977 // */
1978 // char *overflow_arg_area;
1979 // /* location on stack that holds
1980 // * the next overflow argument
1981 // */
1982 // char *reg_save_area;
1983 // /* where r3:r10 and f1:f8 (if saved)
1984 // * are stored
1985 // */
1986 // } va_list[1];
1987
1988
Dan Gohman31ae5862010-04-17 14:41:14 +00001989 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1990 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
Scott Michelcf0da6c2009-02-17 22:15:04 +00001991
Nicolas Geoffray23710a72007-04-03 13:59:52 +00001992
Owen Anderson53aa7a92009-08-10 22:56:29 +00001993 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Scott Michelcf0da6c2009-02-17 22:15:04 +00001994
Dan Gohman31ae5862010-04-17 14:41:14 +00001995 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1996 PtrVT);
1997 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1998 PtrVT);
Scott Michelcf0da6c2009-02-17 22:15:04 +00001999
Duncan Sands13237ac2008-06-06 12:08:01 +00002000 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002001 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
Dan Gohman2d489b52008-02-06 22:27:42 +00002002
Duncan Sands13237ac2008-06-06 12:08:01 +00002003 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002004 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
Dan Gohman2d489b52008-02-06 22:27:42 +00002005
2006 uint64_t FPROffset = 1;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002007 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
Scott Michelcf0da6c2009-02-17 22:15:04 +00002008
Dan Gohman2d489b52008-02-06 22:27:42 +00002009 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Scott Michelcf0da6c2009-02-17 22:15:04 +00002010
Nicolas Geoffray23710a72007-04-03 13:59:52 +00002011 // Store first byte : number of int regs
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002012 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
Chris Lattner6963c1f2010-09-21 17:42:31 +00002013 Op.getOperand(1),
2014 MachinePointerInfo(SV),
2015 MVT::i8, false, false, 0);
Dan Gohman2d489b52008-02-06 22:27:42 +00002016 uint64_t nextOffset = FPROffset;
Dale Johannesen021052a2009-02-04 20:06:27 +00002017 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
Nicolas Geoffray23710a72007-04-03 13:59:52 +00002018 ConstFPROffset);
Scott Michelcf0da6c2009-02-17 22:15:04 +00002019
Nicolas Geoffray23710a72007-04-03 13:59:52 +00002020 // Store second byte : number of float regs
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002021 SDValue secondStore =
Chris Lattner6963c1f2010-09-21 17:42:31 +00002022 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2023 MachinePointerInfo(SV, nextOffset), MVT::i8,
David Greene87a5abe2010-02-15 16:56:53 +00002024 false, false, 0);
Dan Gohman2d489b52008-02-06 22:27:42 +00002025 nextOffset += StackOffset;
Dale Johannesen021052a2009-02-04 20:06:27 +00002026 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
Scott Michelcf0da6c2009-02-17 22:15:04 +00002027
Nicolas Geoffray23710a72007-04-03 13:59:52 +00002028 // Store second word : arguments given on stack
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002029 SDValue thirdStore =
Chris Lattner676c61d2010-09-21 18:41:36 +00002030 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2031 MachinePointerInfo(SV, nextOffset),
David Greene87a5abe2010-02-15 16:56:53 +00002032 false, false, 0);
Dan Gohman2d489b52008-02-06 22:27:42 +00002033 nextOffset += FrameOffset;
Dale Johannesen021052a2009-02-04 20:06:27 +00002034 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
Nicolas Geoffray23710a72007-04-03 13:59:52 +00002035
2036 // Store third word : arguments given in registers
Chris Lattner676c61d2010-09-21 18:41:36 +00002037 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2038 MachinePointerInfo(SV, nextOffset),
David Greene87a5abe2010-02-15 16:56:53 +00002039 false, false, 0);
Nicolas Geoffray23710a72007-04-03 13:59:52 +00002040
Chris Lattner4211ca92006-04-14 06:01:58 +00002041}
2042
Chris Lattner4f2e4e02007-03-06 00:59:59 +00002043#include "PPCGenCallingConv.inc"
2044
Bill Schmidt8c3976e2013-08-26 20:11:46 +00002045// Function whose sole purpose is to kill compiler warnings
2046// stemming from unused functions included from PPCGenCallingConv.inc.
2047CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
Bill Schmidt8470b0f2013-08-30 22:18:55 +00002048 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
Bill Schmidt8c3976e2013-08-26 20:11:46 +00002049}
2050
Bill Schmidt230b4512013-06-12 16:39:22 +00002051bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2052 CCValAssign::LocInfo &LocInfo,
2053 ISD::ArgFlagsTy &ArgFlags,
2054 CCState &State) {
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002055 return true;
2056}
2057
Bill Schmidt230b4512013-06-12 16:39:22 +00002058bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2059 MVT &LocVT,
2060 CCValAssign::LocInfo &LocInfo,
2061 ISD::ArgFlagsTy &ArgFlags,
2062 CCState &State) {
Craig Topper840beec2014-04-04 05:16:06 +00002063 static const MCPhysReg ArgRegs[] = {
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002064 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2065 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2066 };
2067 const unsigned NumArgRegs = array_lengthof(ArgRegs);
Wesley Peck527da1b2010-11-23 03:31:01 +00002068
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002069 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2070
2071 // Skip one register if the first unallocated register has an even register
2072 // number and there are still argument registers available which have not been
2073 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2074 // need to skip a register if RegNum is odd.
2075 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2076 State.AllocateReg(ArgRegs[RegNum]);
2077 }
Wesley Peck527da1b2010-11-23 03:31:01 +00002078
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002079 // Always return false here, as this function only makes sure that the first
2080 // unallocated register has an odd register number and does not actually
2081 // allocate a register for the current argument.
2082 return false;
2083}
2084
Bill Schmidt230b4512013-06-12 16:39:22 +00002085bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2086 MVT &LocVT,
2087 CCValAssign::LocInfo &LocInfo,
2088 ISD::ArgFlagsTy &ArgFlags,
2089 CCState &State) {
Craig Topper840beec2014-04-04 05:16:06 +00002090 static const MCPhysReg ArgRegs[] = {
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002091 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2092 PPC::F8
2093 };
2094
2095 const unsigned NumArgRegs = array_lengthof(ArgRegs);
Wesley Peck527da1b2010-11-23 03:31:01 +00002096
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002097 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2098
2099 // If there is only one Floating-point register left we need to put both f64
2100 // values of a split ppc_fp128 value on the stack.
2101 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2102 State.AllocateReg(ArgRegs[RegNum]);
2103 }
Wesley Peck527da1b2010-11-23 03:31:01 +00002104
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002105 // Always return false here, as this function only makes sure that the two f64
2106 // values a ppc_fp128 value is split into are both passed in registers or both
2107 // passed on the stack and does not actually allocate a register for the
2108 // current argument.
2109 return false;
2110}
2111
Chris Lattner43df5b32007-02-25 05:34:32 +00002112/// GetFPR - Get the set of FP registers that should be allocated for arguments,
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00002113/// on Darwin.
Craig Topper840beec2014-04-04 05:16:06 +00002114static const MCPhysReg *GetFPR() {
2115 static const MCPhysReg FPR[] = {
Chris Lattner43df5b32007-02-25 05:34:32 +00002116 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00002117 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
Chris Lattner43df5b32007-02-25 05:34:32 +00002118 };
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00002119
Chris Lattner43df5b32007-02-25 05:34:32 +00002120 return FPR;
2121}
2122
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00002123/// CalculateStackSlotSize - Calculates the size reserved for this argument on
2124/// the stack.
Owen Anderson53aa7a92009-08-10 22:56:29 +00002125static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
Tilmann Scheller98bdaaa2009-07-03 06:43:35 +00002126 unsigned PtrByteSize) {
Hal Finkel940ab932014-02-28 00:27:01 +00002127 unsigned ArgSize = ArgVT.getStoreSize();
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00002128 if (Flags.isByVal())
2129 ArgSize = Flags.getByValSize();
2130 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2131
2132 return ArgSize;
2133}
Ulrich Weigand2bffb952014-06-23 13:08:27 +00002134/// EnsureStackAlignment - Round stack frame size up from NumBytes to
2135/// ensure minimum alignment required for target.
2136static unsigned EnsureStackAlignment(const TargetMachine &Target,
2137 unsigned NumBytes) {
2138 unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment();
2139 unsigned AlignMask = TargetAlign - 1;
2140 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2141 return NumBytes;
2142}
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00002143
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002144SDValue
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002145PPCTargetLowering::LowerFormalArguments(SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +00002146 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002147 const SmallVectorImpl<ISD::InputArg>
2148 &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +00002149 SDLoc dl, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +00002150 SmallVectorImpl<SDValue> &InVals)
2151 const {
Eric Christopherb1aaebe2014-06-12 22:38:18 +00002152 if (Subtarget.isSVR4ABI()) {
2153 if (Subtarget.isPPC64())
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002154 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2155 dl, DAG, InVals);
2156 else
2157 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2158 dl, DAG, InVals);
Bill Schmidt019cc6f2012-09-19 15:42:13 +00002159 } else {
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002160 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2161 dl, DAG, InVals);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002162 }
2163}
2164
2165SDValue
Bill Schmidt019cc6f2012-09-19 15:42:13 +00002166PPCTargetLowering::LowerFormalArguments_32SVR4(
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002167 SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +00002168 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002169 const SmallVectorImpl<ISD::InputArg>
2170 &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +00002171 SDLoc dl, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +00002172 SmallVectorImpl<SDValue> &InVals) const {
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002173
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00002174 // 32-bit SVR4 ABI Stack Frame Layout:
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002175 // +-----------------------------------+
2176 // +--> | Back chain |
2177 // | +-----------------------------------+
2178 // | | Floating-point register save area |
2179 // | +-----------------------------------+
2180 // | | General register save area |
2181 // | +-----------------------------------+
2182 // | | CR save word |
2183 // | +-----------------------------------+
2184 // | | VRSAVE save word |
2185 // | +-----------------------------------+
2186 // | | Alignment padding |
2187 // | +-----------------------------------+
2188 // | | Vector register save area |
2189 // | +-----------------------------------+
2190 // | | Local variable space |
2191 // | +-----------------------------------+
2192 // | | Parameter list area |
2193 // | +-----------------------------------+
2194 // | | LR save word |
2195 // | +-----------------------------------+
2196 // SP--> +--- | Back chain |
2197 // +-----------------------------------+
2198 //
2199 // Specifications:
2200 // System V Application Binary Interface PowerPC Processor Supplement
2201 // AltiVec Technology Programming Interface Manual
Wesley Peck527da1b2010-11-23 03:31:01 +00002202
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002203 MachineFunction &MF = DAG.getMachineFunction();
2204 MachineFrameInfo *MFI = MF.getFrameInfo();
Dan Gohman31ae5862010-04-17 14:41:14 +00002205 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002206
Owen Anderson53aa7a92009-08-10 22:56:29 +00002207 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002208 // Potential tail calls could cause overwriting of argument stack slots.
Nick Lewycky50f02cb2011-12-02 22:16:29 +00002209 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2210 (CallConv == CallingConv::Fast));
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002211 unsigned PtrByteSize = 4;
2212
2213 // Assign locations to all of the incoming arguments.
2214 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher0713a9d2011-06-08 23:55:35 +00002215 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Gabor Greif180c4442012-04-19 15:16:31 +00002216 getTargetMachine(), ArgLocs, *DAG.getContext());
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002217
2218 // Reserve space for the linkage area on the stack.
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00002219 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false);
2220 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002221
Bill Schmidtef17c142013-02-06 17:33:58 +00002222 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
Wesley Peck527da1b2010-11-23 03:31:01 +00002223
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002224 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2225 CCValAssign &VA = ArgLocs[i];
Wesley Peck527da1b2010-11-23 03:31:01 +00002226
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002227 // Arguments stored in registers.
2228 if (VA.isRegLoc()) {
Craig Topper760b1342012-02-22 05:59:10 +00002229 const TargetRegisterClass *RC;
Owen Anderson53aa7a92009-08-10 22:56:29 +00002230 EVT ValVT = VA.getValVT();
Wesley Peck527da1b2010-11-23 03:31:01 +00002231
Owen Anderson9f944592009-08-11 20:47:22 +00002232 switch (ValVT.getSimpleVT().SimpleTy) {
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002233 default:
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002234 llvm_unreachable("ValVT not supported by formal arguments Lowering");
Hal Finkel940ab932014-02-28 00:27:01 +00002235 case MVT::i1:
Owen Anderson9f944592009-08-11 20:47:22 +00002236 case MVT::i32:
Craig Topperabadc662012-04-20 06:31:50 +00002237 RC = &PPC::GPRCRegClass;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002238 break;
Owen Anderson9f944592009-08-11 20:47:22 +00002239 case MVT::f32:
Craig Topperabadc662012-04-20 06:31:50 +00002240 RC = &PPC::F4RCRegClass;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002241 break;
Owen Anderson9f944592009-08-11 20:47:22 +00002242 case MVT::f64:
Eric Christopherb1aaebe2014-06-12 22:38:18 +00002243 if (Subtarget.hasVSX())
Hal Finkel19be5062014-03-29 05:29:01 +00002244 RC = &PPC::VSFRCRegClass;
2245 else
2246 RC = &PPC::F8RCRegClass;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002247 break;
Owen Anderson9f944592009-08-11 20:47:22 +00002248 case MVT::v16i8:
2249 case MVT::v8i16:
2250 case MVT::v4i32:
2251 case MVT::v4f32:
Hal Finkel7811c612014-03-28 19:58:11 +00002252 RC = &PPC::VRRCRegClass;
2253 break;
Hal Finkel27774d92014-03-13 07:58:58 +00002254 case MVT::v2f64:
Hal Finkela6c8b512014-03-26 16:12:58 +00002255 case MVT::v2i64:
Hal Finkel7811c612014-03-28 19:58:11 +00002256 RC = &PPC::VSHRCRegClass;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002257 break;
2258 }
Wesley Peck527da1b2010-11-23 03:31:01 +00002259
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002260 // Transform the arguments stored in physical registers into virtual ones.
Devang Patelf3292b22011-02-21 23:21:26 +00002261 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
Hal Finkel940ab932014-02-28 00:27:01 +00002262 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2263 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2264
2265 if (ValVT == MVT::i1)
2266 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002267
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002268 InVals.push_back(ArgValue);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002269 } else {
2270 // Argument stored in memory.
2271 assert(VA.isMemLoc());
2272
Hal Finkel940ab932014-02-28 00:27:01 +00002273 unsigned ArgSize = VA.getLocVT().getStoreSize();
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002274 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
Evan Cheng0664a672010-07-03 00:40:23 +00002275 isImmutable);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002276
2277 // Create load nodes to retrieve arguments from the stack.
2278 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
Chris Lattner7727d052010-09-21 06:44:06 +00002279 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2280 MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00002281 false, false, false, 0));
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002282 }
2283 }
2284
2285 // Assign locations to all of the incoming aggregate by value arguments.
2286 // Aggregates passed by value are stored in the local variable space of the
2287 // caller's stack frame, right above the parameter list area.
2288 SmallVector<CCValAssign, 16> ByValArgLocs;
Eric Christopher0713a9d2011-06-08 23:55:35 +00002289 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Gabor Greif180c4442012-04-19 15:16:31 +00002290 getTargetMachine(), ByValArgLocs, *DAG.getContext());
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002291
2292 // Reserve stack space for the allocations in CCInfo.
2293 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2294
Bill Schmidtef17c142013-02-06 17:33:58 +00002295 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002296
2297 // Area that is at least reserved in the caller of this function.
2298 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00002299 MinReservedArea = std::max(MinReservedArea, LinkageSize);
Wesley Peck527da1b2010-11-23 03:31:01 +00002300
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002301 // Set the size that is at least reserved in caller of this function. Tail
2302 // call optimized function's reserved stack space needs to be aligned so that
2303 // taking the difference between two stack areas will result in an aligned
2304 // stack.
Ulrich Weigand2bffb952014-06-23 13:08:27 +00002305 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2306 FuncInfo->setMinReservedArea(MinReservedArea);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002307
2308 SmallVector<SDValue, 8> MemOps;
Wesley Peck527da1b2010-11-23 03:31:01 +00002309
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002310 // If the function takes variable number of arguments, make a frame index for
2311 // the start of the first vararg value... for expansion of llvm.va_start.
2312 if (isVarArg) {
Craig Topper840beec2014-04-04 05:16:06 +00002313 static const MCPhysReg GPArgRegs[] = {
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002314 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2315 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2316 };
2317 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2318
Craig Topper840beec2014-04-04 05:16:06 +00002319 static const MCPhysReg FPArgRegs[] = {
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002320 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2321 PPC::F8
2322 };
2323 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2324
Dan Gohman31ae5862010-04-17 14:41:14 +00002325 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2326 NumGPArgRegs));
2327 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2328 NumFPArgRegs));
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002329
2330 // Make room for NumGPArgRegs and NumFPArgRegs.
2331 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
Owen Anderson9f944592009-08-11 20:47:22 +00002332 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002333
Dan Gohman31ae5862010-04-17 14:41:14 +00002334 FuncInfo->setVarArgsStackOffset(
2335 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
Evan Cheng0664a672010-07-03 00:40:23 +00002336 CCInfo.getNextStackOffset(), true));
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002337
Dan Gohman31ae5862010-04-17 14:41:14 +00002338 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2339 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002340
Jakob Stoklund Olesen6c4353e2010-10-11 20:43:09 +00002341 // The fixed integer arguments of a variadic function are stored to the
2342 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2343 // the result of va_next.
2344 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2345 // Get an existing live-in vreg, or add a new one.
2346 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2347 if (!VReg)
Devang Patelf3292b22011-02-21 23:21:26 +00002348 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002349
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002350 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
Chris Lattner676c61d2010-09-21 18:41:36 +00002351 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2352 MachinePointerInfo(), false, false, 0);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002353 MemOps.push_back(Store);
2354 // Increment the address by four for the next argument to store
2355 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2356 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2357 }
2358
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00002359 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2360 // is set.
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002361 // The double arguments are stored to the VarArgsFrameIndex
2362 // on the stack.
Jakob Stoklund Olesen6c4353e2010-10-11 20:43:09 +00002363 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2364 // Get an existing live-in vreg, or add a new one.
2365 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2366 if (!VReg)
Devang Patelf3292b22011-02-21 23:21:26 +00002367 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002368
Owen Anderson9f944592009-08-11 20:47:22 +00002369 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
Chris Lattner676c61d2010-09-21 18:41:36 +00002370 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2371 MachinePointerInfo(), false, false, 0);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002372 MemOps.push_back(Store);
2373 // Increment the address by eight for the next argument to store
Owen Anderson9f944592009-08-11 20:47:22 +00002374 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002375 PtrVT);
2376 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2377 }
2378 }
2379
2380 if (!MemOps.empty())
Craig Topper48d114b2014-04-26 18:35:24 +00002381 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002382
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002383 return Chain;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002384}
2385
Bill Schmidt57d6de52012-10-23 15:51:16 +00002386// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2387// value to MVT::i64 and then truncate to the correct register size.
2388SDValue
2389PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2390 SelectionDAG &DAG, SDValue ArgVal,
Andrew Trickef9de2a2013-05-25 02:42:55 +00002391 SDLoc dl) const {
Bill Schmidt57d6de52012-10-23 15:51:16 +00002392 if (Flags.isSExt())
2393 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2394 DAG.getValueType(ObjectVT));
2395 else if (Flags.isZExt())
2396 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2397 DAG.getValueType(ObjectVT));
Matt Arsenault758659232013-05-18 00:21:46 +00002398
Hal Finkel940ab932014-02-28 00:27:01 +00002399 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
Bill Schmidt57d6de52012-10-23 15:51:16 +00002400}
2401
Tilmann Schellerb93960d2009-07-03 06:45:56 +00002402SDValue
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002403PPCTargetLowering::LowerFormalArguments_64SVR4(
2404 SDValue Chain,
2405 CallingConv::ID CallConv, bool isVarArg,
2406 const SmallVectorImpl<ISD::InputArg>
2407 &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +00002408 SDLoc dl, SelectionDAG &DAG,
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002409 SmallVectorImpl<SDValue> &InVals) const {
2410 // TODO: add description of PPC stack frame format, or at least some docs.
2411 //
Ulrich Weigand59c6ab22014-06-20 16:34:05 +00002412 bool isLittleEndian = Subtarget.isLittleEndian();
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002413 MachineFunction &MF = DAG.getMachineFunction();
2414 MachineFrameInfo *MFI = MF.getFrameInfo();
2415 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2416
2417 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2418 // Potential tail calls could cause overwriting of argument stack slots.
2419 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2420 (CallConv == CallingConv::Fast));
2421 unsigned PtrByteSize = 8;
2422
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00002423 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false);
2424 unsigned ArgOffset = LinkageSize;
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002425 // Area that is at least reserved in caller of this function.
2426 unsigned MinReservedArea = ArgOffset;
2427
Craig Topper840beec2014-04-04 05:16:06 +00002428 static const MCPhysReg GPR[] = {
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002429 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2430 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2431 };
2432
Craig Topper840beec2014-04-04 05:16:06 +00002433 static const MCPhysReg *FPR = GetFPR();
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002434
Craig Topper840beec2014-04-04 05:16:06 +00002435 static const MCPhysReg VR[] = {
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002436 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2437 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2438 };
Craig Topper840beec2014-04-04 05:16:06 +00002439 static const MCPhysReg VSRH[] = {
Hal Finkel7811c612014-03-28 19:58:11 +00002440 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2441 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2442 };
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002443
2444 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2445 const unsigned Num_FPR_Regs = 13;
2446 const unsigned Num_VR_Regs = array_lengthof(VR);
2447
2448 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2449
2450 // Add DAG nodes to load the arguments or copy them out of registers. On
2451 // entry to a function on PPC, the arguments start after the linkage area,
2452 // although the first ones are often in registers.
2453
2454 SmallVector<SDValue, 8> MemOps;
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002455 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
Bill Schmidt6631e942013-02-20 17:31:41 +00002456 unsigned CurArgIdx = 0;
2457 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002458 SDValue ArgVal;
2459 bool needsLoad = false;
2460 EVT ObjectVT = Ins[ArgNo].VT;
Hal Finkel940ab932014-02-28 00:27:01 +00002461 unsigned ObjSize = ObjectVT.getStoreSize();
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002462 unsigned ArgSize = ObjSize;
2463 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
Bill Schmidt6631e942013-02-20 17:31:41 +00002464 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2465 CurArgIdx = Ins[ArgNo].OrigArgIndex;
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002466
2467 unsigned CurArgOffset = ArgOffset;
2468
Ulrich Weigand9ba552d2014-06-23 12:36:34 +00002469 // Altivec parameters are padded to a 16 byte boundary.
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002470 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
Hal Finkel27774d92014-03-13 07:58:58 +00002471 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8 ||
Ulrich Weigand9ba552d2014-06-23 12:36:34 +00002472 ObjectVT==MVT::v2f64 || ObjectVT==MVT::v2i64)
2473 MinReservedArea = ((MinReservedArea+15)/16)*16;
2474
2475 // Calculate min reserved area.
2476 MinReservedArea += CalculateStackSlotSize(ObjectVT, Flags, PtrByteSize);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002477
2478 // FIXME the codegen can be much improved in some cases.
2479 // We do not have to keep everything in memory.
2480 if (Flags.isByVal()) {
2481 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2482 ObjSize = Flags.getByValSize();
2483 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
Bill Schmidt9953cf22012-10-31 01:15:05 +00002484 // Empty aggregate parameters do not take up registers. Examples:
2485 // struct { } a;
2486 // union { } b;
2487 // int c[0];
2488 // etc. However, we have to provide a place-holder in InVals, so
2489 // pretend we have an 8-byte item at the current address for that
2490 // purpose.
2491 if (!ObjSize) {
2492 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2493 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2494 InVals.push_back(FIN);
2495 continue;
2496 }
Hal Finkel262a2242013-09-12 23:20:06 +00002497
2498 unsigned BVAlign = Flags.getByValAlign();
2499 if (BVAlign > 8) {
2500 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2501 CurArgOffset = ArgOffset;
2502 }
2503
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002504 // All aggregates smaller than 8 bytes must be passed right-justified.
Ulrich Weigand59c6ab22014-06-20 16:34:05 +00002505 if (ObjSize < PtrByteSize && !isLittleEndian)
Bill Schmidt48081ca2012-10-16 13:30:53 +00002506 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002507 // The value of the object is its address.
2508 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2509 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2510 InVals.push_back(FIN);
Bill Schmidt6ed3b992012-10-25 13:38:09 +00002511
2512 if (ObjSize < 8) {
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002513 if (GPR_idx != Num_GPR_Regs) {
Bill Schmidt6ed3b992012-10-25 13:38:09 +00002514 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002515 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
Bill Schmidt6ed3b992012-10-25 13:38:09 +00002516 SDValue Store;
2517
2518 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2519 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2520 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2521 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
Hal Finkel3e4a34c2014-01-21 20:15:58 +00002522 MachinePointerInfo(FuncArg),
Bill Schmidt6ed3b992012-10-25 13:38:09 +00002523 ObjType, false, false, 0);
2524 } else {
2525 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2526 // store the whole register as-is to the parameter save area
2527 // slot. The address of the parameter was already calculated
2528 // above (InVals.push_back(FIN)) to be the right-justified
2529 // offset within the slot. For this store, we need a new
2530 // frame index that points at the beginning of the slot.
2531 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2532 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2533 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
Hal Finkel3e4a34c2014-01-21 20:15:58 +00002534 MachinePointerInfo(FuncArg),
Bill Schmidt6ed3b992012-10-25 13:38:09 +00002535 false, false, 0);
2536 }
2537
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002538 MemOps.push_back(Store);
2539 ++GPR_idx;
2540 }
Bill Schmidt6ed3b992012-10-25 13:38:09 +00002541 // Whether we copied from a register or not, advance the offset
2542 // into the parameter save area by a full doubleword.
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002543 ArgOffset += PtrByteSize;
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002544 continue;
2545 }
Bill Schmidt6ed3b992012-10-25 13:38:09 +00002546
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002547 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2548 // Store whatever pieces of the object are in registers
2549 // to memory. ArgOffset will be the address of the beginning
2550 // of the object.
2551 if (GPR_idx != Num_GPR_Regs) {
2552 unsigned VReg;
2553 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2554 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2555 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2556 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
Bill Schmidt6ed3b992012-10-25 13:38:09 +00002557 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
Hal Finkel3e4a34c2014-01-21 20:15:58 +00002558 MachinePointerInfo(FuncArg, j),
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002559 false, false, 0);
2560 MemOps.push_back(Store);
2561 ++GPR_idx;
2562 ArgOffset += PtrByteSize;
2563 } else {
Bill Schmidt48081ca2012-10-16 13:30:53 +00002564 ArgOffset += ArgSize - j;
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002565 break;
2566 }
2567 }
2568 continue;
2569 }
2570
2571 switch (ObjectVT.getSimpleVT().SimpleTy) {
2572 default: llvm_unreachable("Unhandled argument type!");
Hal Finkel940ab932014-02-28 00:27:01 +00002573 case MVT::i1:
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002574 case MVT::i32:
2575 case MVT::i64:
2576 if (GPR_idx != Num_GPR_Regs) {
2577 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2578 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2579
Hal Finkel940ab932014-02-28 00:27:01 +00002580 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002581 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2582 // value to MVT::i64 and then truncate to the correct register size.
Bill Schmidt57d6de52012-10-23 15:51:16 +00002583 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002584
2585 ++GPR_idx;
2586 } else {
2587 needsLoad = true;
2588 ArgSize = PtrByteSize;
2589 }
2590 ArgOffset += 8;
2591 break;
2592
2593 case MVT::f32:
2594 case MVT::f64:
2595 // Every 8 bytes of argument space consumes one of the GPRs available for
2596 // argument passing.
2597 if (GPR_idx != Num_GPR_Regs) {
2598 ++GPR_idx;
2599 }
2600 if (FPR_idx != Num_FPR_Regs) {
2601 unsigned VReg;
2602
2603 if (ObjectVT == MVT::f32)
2604 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2605 else
Eric Christopherb1aaebe2014-06-12 22:38:18 +00002606 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
Hal Finkel19be5062014-03-29 05:29:01 +00002607 &PPC::VSFRCRegClass :
2608 &PPC::F8RCRegClass);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002609
2610 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2611 ++FPR_idx;
2612 } else {
2613 needsLoad = true;
Bill Schmidt22162472012-10-11 15:38:20 +00002614 ArgSize = PtrByteSize;
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002615 }
2616
2617 ArgOffset += 8;
2618 break;
2619 case MVT::v4f32:
2620 case MVT::v4i32:
2621 case MVT::v8i16:
2622 case MVT::v16i8:
Hal Finkel27774d92014-03-13 07:58:58 +00002623 case MVT::v2f64:
Hal Finkela6c8b512014-03-26 16:12:58 +00002624 case MVT::v2i64:
Ulrich Weigand9ba552d2014-06-23 12:36:34 +00002625 // Vectors are aligned to a 16-byte boundary in the argument save area.
2626 while ((ArgOffset % 16) != 0) {
2627 ArgOffset += PtrByteSize;
2628 if (GPR_idx != Num_GPR_Regs)
2629 GPR_idx++;
2630 }
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002631 if (VR_idx != Num_VR_Regs) {
Hal Finkel7811c612014-03-28 19:58:11 +00002632 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2633 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2634 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002635 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002636 ++VR_idx;
2637 } else {
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002638 CurArgOffset = ArgOffset;
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002639 needsLoad = true;
2640 }
Ulrich Weigand9ba552d2014-06-23 12:36:34 +00002641 ArgOffset += 16;
2642 GPR_idx = std::min(GPR_idx + 2, Num_GPR_Regs);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002643 break;
2644 }
2645
2646 // We need to load the argument to a virtual register if we determined
2647 // above that we ran out of physical registers of the appropriate type.
2648 if (needsLoad) {
Ulrich Weigand59c6ab22014-06-20 16:34:05 +00002649 if (ObjSize < ArgSize && !isLittleEndian)
2650 CurArgOffset += ArgSize - ObjSize;
2651 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002652 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2653 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2654 false, false, false, 0);
2655 }
2656
2657 InVals.push_back(ArgVal);
2658 }
2659
Ulrich Weigand2bffb952014-06-23 13:08:27 +00002660 // Area that is at least reserved in the caller of this function.
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00002661 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
Ulrich Weigand2bffb952014-06-23 13:08:27 +00002662
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002663 // Set the size that is at least reserved in caller of this function. Tail
Bill Schmidt57d6de52012-10-23 15:51:16 +00002664 // call optimized functions' reserved stack space needs to be aligned so that
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002665 // taking the difference between two stack areas will result in an aligned
2666 // stack.
Ulrich Weigand2bffb952014-06-23 13:08:27 +00002667 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2668 FuncInfo->setMinReservedArea(MinReservedArea);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002669
2670 // If the function takes variable number of arguments, make a frame index for
2671 // the start of the first vararg value... for expansion of llvm.va_start.
2672 if (isVarArg) {
2673 int Depth = ArgOffset;
2674
2675 FuncInfo->setVarArgsFrameIndex(
Bill Schmidt57d6de52012-10-23 15:51:16 +00002676 MFI->CreateFixedObject(PtrByteSize, Depth, true));
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002677 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2678
2679 // If this function is vararg, store any remaining integer argument regs
2680 // to their spots on the stack so that they may be loaded by deferencing the
2681 // result of va_next.
2682 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2683 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2684 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2685 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2686 MachinePointerInfo(), false, false, 0);
2687 MemOps.push_back(Store);
2688 // Increment the address by four for the next argument to store
Bill Schmidt57d6de52012-10-23 15:51:16 +00002689 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002690 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2691 }
2692 }
2693
2694 if (!MemOps.empty())
Craig Topper48d114b2014-04-26 18:35:24 +00002695 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002696
2697 return Chain;
2698}
2699
2700SDValue
2701PPCTargetLowering::LowerFormalArguments_Darwin(
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002702 SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +00002703 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002704 const SmallVectorImpl<ISD::InputArg>
2705 &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +00002706 SDLoc dl, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +00002707 SmallVectorImpl<SDValue> &InVals) const {
Chris Lattner4302e8f2006-05-16 18:18:50 +00002708 // TODO: add description of PPC stack frame format, or at least some docs.
2709 //
2710 MachineFunction &MF = DAG.getMachineFunction();
2711 MachineFrameInfo *MFI = MF.getFrameInfo();
Dan Gohman31ae5862010-04-17 14:41:14 +00002712 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
Scott Michelcf0da6c2009-02-17 22:15:04 +00002713
Owen Anderson53aa7a92009-08-10 22:56:29 +00002714 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Owen Anderson9f944592009-08-11 20:47:22 +00002715 bool isPPC64 = PtrVT == MVT::i64;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00002716 // Potential tail calls could cause overwriting of argument stack slots.
Nick Lewycky50f02cb2011-12-02 22:16:29 +00002717 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2718 (CallConv == CallingConv::Fast));
Jim Laskeyf4e2e002006-11-28 14:53:52 +00002719 unsigned PtrByteSize = isPPC64 ? 8 : 4;
Jim Laskey48850c12006-11-16 22:43:37 +00002720
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00002721 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true);
2722 unsigned ArgOffset = LinkageSize;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00002723 // Area that is at least reserved in caller of this function.
2724 unsigned MinReservedArea = ArgOffset;
2725
Craig Topper840beec2014-04-04 05:16:06 +00002726 static const MCPhysReg GPR_32[] = { // 32-bit registers.
Chris Lattner4302e8f2006-05-16 18:18:50 +00002727 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2728 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2729 };
Craig Topper840beec2014-04-04 05:16:06 +00002730 static const MCPhysReg GPR_64[] = { // 64-bit registers.
Chris Lattnerec78cad2006-06-26 22:48:35 +00002731 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2732 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2733 };
Scott Michelcf0da6c2009-02-17 22:15:04 +00002734
Craig Topper840beec2014-04-04 05:16:06 +00002735 static const MCPhysReg *FPR = GetFPR();
Scott Michelcf0da6c2009-02-17 22:15:04 +00002736
Craig Topper840beec2014-04-04 05:16:06 +00002737 static const MCPhysReg VR[] = {
Chris Lattner4302e8f2006-05-16 18:18:50 +00002738 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2739 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2740 };
Chris Lattnerec78cad2006-06-26 22:48:35 +00002741
Owen Andersone2f23a32007-09-07 04:06:50 +00002742 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00002743 const unsigned Num_FPR_Regs = 13;
Owen Andersone2f23a32007-09-07 04:06:50 +00002744 const unsigned Num_VR_Regs = array_lengthof( VR);
Jim Laskey48850c12006-11-16 22:43:37 +00002745
2746 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
Scott Michelcf0da6c2009-02-17 22:15:04 +00002747
Craig Topper840beec2014-04-04 05:16:06 +00002748 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
Scott Michelcf0da6c2009-02-17 22:15:04 +00002749
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002750 // In 32-bit non-varargs functions, the stack space for vectors is after the
2751 // stack space for non-vectors. We do not use this space unless we have
2752 // too many vectors to fit in registers, something that only occurs in
Scott Michelcf0da6c2009-02-17 22:15:04 +00002753 // constructed examples:), but we have to walk the arglist to figure
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002754 // that out...for the pathological case, compute VecArgOffset as the
2755 // start of the vector parameter area. Computing VecArgOffset is the
2756 // entire point of the following loop.
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002757 unsigned VecArgOffset = ArgOffset;
2758 if (!isVarArg && !isPPC64) {
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002759 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002760 ++ArgNo) {
Owen Anderson53aa7a92009-08-10 22:56:29 +00002761 EVT ObjectVT = Ins[ArgNo].VT;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002762 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002763
Duncan Sandsd97eea32008-03-21 09:14:45 +00002764 if (Flags.isByVal()) {
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002765 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
Benjamin Kramer084b9f42012-01-20 14:42:32 +00002766 unsigned ObjSize = Flags.getByValSize();
Scott Michelcf0da6c2009-02-17 22:15:04 +00002767 unsigned ArgSize =
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002768 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2769 VecArgOffset += ArgSize;
2770 continue;
2771 }
2772
Owen Anderson9f944592009-08-11 20:47:22 +00002773 switch(ObjectVT.getSimpleVT().SimpleTy) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00002774 default: llvm_unreachable("Unhandled argument type!");
Hal Finkel5cae2162014-02-28 01:17:25 +00002775 case MVT::i1:
Owen Anderson9f944592009-08-11 20:47:22 +00002776 case MVT::i32:
2777 case MVT::f32:
Bill Schmidt019cc6f2012-09-19 15:42:13 +00002778 VecArgOffset += 4;
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002779 break;
Owen Anderson9f944592009-08-11 20:47:22 +00002780 case MVT::i64: // PPC64
2781 case MVT::f64:
Bill Schmidt019cc6f2012-09-19 15:42:13 +00002782 // FIXME: We are guaranteed to be !isPPC64 at this point.
2783 // Does MVT::i64 apply?
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002784 VecArgOffset += 8;
2785 break;
Owen Anderson9f944592009-08-11 20:47:22 +00002786 case MVT::v4f32:
2787 case MVT::v4i32:
2788 case MVT::v8i16:
2789 case MVT::v16i8:
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002790 // Nothing to do, we're only looking at Nonvector args here.
2791 break;
2792 }
2793 }
2794 }
2795 // We've found where the vector parameter area in memory is. Skip the
2796 // first 12 parameters; these don't use that memory.
2797 VecArgOffset = ((VecArgOffset+15)/16)*16;
2798 VecArgOffset += 12*16;
2799
Chris Lattner4302e8f2006-05-16 18:18:50 +00002800 // Add DAG nodes to load the arguments or copy them out of registers. On
Jim Laskey48850c12006-11-16 22:43:37 +00002801 // entry to a function on PPC, the arguments start after the linkage area,
2802 // although the first ones are often in registers.
Nicolas Geoffray7aad9282007-03-13 15:02:46 +00002803
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002804 SmallVector<SDValue, 8> MemOps;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00002805 unsigned nAltivecParamsAtEnd = 0;
Roman Divackyca103892012-09-24 20:47:19 +00002806 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
Bill Schmidt38b6cb52013-05-08 17:22:33 +00002807 unsigned CurArgIdx = 0;
2808 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002809 SDValue ArgVal;
Chris Lattner4302e8f2006-05-16 18:18:50 +00002810 bool needsLoad = false;
Owen Anderson53aa7a92009-08-10 22:56:29 +00002811 EVT ObjectVT = Ins[ArgNo].VT;
Duncan Sands13237ac2008-06-06 12:08:01 +00002812 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
Jim Laskey152671f2006-11-29 13:37:09 +00002813 unsigned ArgSize = ObjSize;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002814 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
Bill Schmidt38b6cb52013-05-08 17:22:33 +00002815 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2816 CurArgIdx = Ins[ArgNo].OrigArgIndex;
Chris Lattner4302e8f2006-05-16 18:18:50 +00002817
Chris Lattner318f0d22006-05-16 18:51:52 +00002818 unsigned CurArgOffset = ArgOffset;
Dale Johannesenbfa252d2008-03-07 20:27:40 +00002819
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00002820 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
Owen Anderson9f944592009-08-11 20:47:22 +00002821 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2822 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00002823 if (isVarArg || isPPC64) {
2824 MinReservedArea = ((MinReservedArea+15)/16)*16;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002825 MinReservedArea += CalculateStackSlotSize(ObjectVT,
Dan Gohmand3fe1742008-09-13 01:54:27 +00002826 Flags,
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00002827 PtrByteSize);
2828 } else nAltivecParamsAtEnd++;
2829 } else
2830 // Calculate min reserved area.
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002831 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
Dan Gohmand3fe1742008-09-13 01:54:27 +00002832 Flags,
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00002833 PtrByteSize);
2834
Dale Johannesenbfa252d2008-03-07 20:27:40 +00002835 // FIXME the codegen can be much improved in some cases.
2836 // We do not have to keep everything in memory.
Duncan Sandsd97eea32008-03-21 09:14:45 +00002837 if (Flags.isByVal()) {
Dale Johannesenbfa252d2008-03-07 20:27:40 +00002838 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
Duncan Sandsd97eea32008-03-21 09:14:45 +00002839 ObjSize = Flags.getByValSize();
Dale Johannesenbfa252d2008-03-07 20:27:40 +00002840 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002841 // Objects of size 1 and 2 are right justified, everything else is
2842 // left justified. This means the memory address is adjusted forwards.
Dale Johannesen21a8f142008-03-08 01:41:42 +00002843 if (ObjSize==1 || ObjSize==2) {
2844 CurArgOffset = CurArgOffset + (4 - ObjSize);
2845 }
Dale Johannesenbfa252d2008-03-07 20:27:40 +00002846 // The value of the object is its address.
Evan Cheng0664a672010-07-03 00:40:23 +00002847 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002848 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002849 InVals.push_back(FIN);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002850 if (ObjSize==1 || ObjSize==2) {
Dale Johannesen21a8f142008-03-08 01:41:42 +00002851 if (GPR_idx != Num_GPR_Regs) {
Roman Divackyd0419622011-06-17 15:21:10 +00002852 unsigned VReg;
2853 if (isPPC64)
2854 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2855 else
2856 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002857 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
Bill Schmidt57d6de52012-10-23 15:51:16 +00002858 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
Scott Michelcf0da6c2009-02-17 22:15:04 +00002859 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
Hal Finkel3e4a34c2014-01-21 20:15:58 +00002860 MachinePointerInfo(FuncArg),
Bill Schmidt019cc6f2012-09-19 15:42:13 +00002861 ObjType, false, false, 0);
Dale Johannesen21a8f142008-03-08 01:41:42 +00002862 MemOps.push_back(Store);
2863 ++GPR_idx;
Dale Johannesen21a8f142008-03-08 01:41:42 +00002864 }
Wesley Peck527da1b2010-11-23 03:31:01 +00002865
Tilmann Scheller773f14c2009-07-03 06:47:08 +00002866 ArgOffset += PtrByteSize;
Wesley Peck527da1b2010-11-23 03:31:01 +00002867
Dale Johannesen21a8f142008-03-08 01:41:42 +00002868 continue;
2869 }
Dale Johannesenbfa252d2008-03-07 20:27:40 +00002870 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2871 // Store whatever pieces of the object are in registers
Bill Schmidt019cc6f2012-09-19 15:42:13 +00002872 // to memory. ArgOffset will be the address of the beginning
2873 // of the object.
Dale Johannesenbfa252d2008-03-07 20:27:40 +00002874 if (GPR_idx != Num_GPR_Regs) {
Roman Divackyd0419622011-06-17 15:21:10 +00002875 unsigned VReg;
2876 if (isPPC64)
2877 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2878 else
2879 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
Evan Cheng0664a672010-07-03 00:40:23 +00002880 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00002881 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002882 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
Bill Schmidtd1fa36f2012-10-05 21:27:08 +00002883 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
Hal Finkel3e4a34c2014-01-21 20:15:58 +00002884 MachinePointerInfo(FuncArg, j),
David Greene87a5abe2010-02-15 16:56:53 +00002885 false, false, 0);
Dale Johannesenbfa252d2008-03-07 20:27:40 +00002886 MemOps.push_back(Store);
2887 ++GPR_idx;
Tilmann Scheller773f14c2009-07-03 06:47:08 +00002888 ArgOffset += PtrByteSize;
Dale Johannesenbfa252d2008-03-07 20:27:40 +00002889 } else {
2890 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2891 break;
2892 }
2893 }
2894 continue;
2895 }
2896
Owen Anderson9f944592009-08-11 20:47:22 +00002897 switch (ObjectVT.getSimpleVT().SimpleTy) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00002898 default: llvm_unreachable("Unhandled argument type!");
Hal Finkel5cae2162014-02-28 01:17:25 +00002899 case MVT::i1:
Owen Anderson9f944592009-08-11 20:47:22 +00002900 case MVT::i32:
Bill Wendling968f32c2008-03-07 20:49:02 +00002901 if (!isPPC64) {
Bill Wendling968f32c2008-03-07 20:49:02 +00002902 if (GPR_idx != Num_GPR_Regs) {
Devang Patelf3292b22011-02-21 23:21:26 +00002903 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
Owen Anderson9f944592009-08-11 20:47:22 +00002904 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
Hal Finkel7f908e82014-03-06 00:45:19 +00002905
2906 if (ObjectVT == MVT::i1)
2907 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2908
Bill Wendling968f32c2008-03-07 20:49:02 +00002909 ++GPR_idx;
2910 } else {
2911 needsLoad = true;
2912 ArgSize = PtrByteSize;
2913 }
Tilmann Scheller773f14c2009-07-03 06:47:08 +00002914 // All int arguments reserve stack space in the Darwin ABI.
2915 ArgOffset += PtrByteSize;
Bill Wendling968f32c2008-03-07 20:49:02 +00002916 break;
Chris Lattner4302e8f2006-05-16 18:18:50 +00002917 }
Bill Wendling968f32c2008-03-07 20:49:02 +00002918 // FALLTHROUGH
Owen Anderson9f944592009-08-11 20:47:22 +00002919 case MVT::i64: // PPC64
Chris Lattnerec78cad2006-06-26 22:48:35 +00002920 if (GPR_idx != Num_GPR_Regs) {
Devang Patelf3292b22011-02-21 23:21:26 +00002921 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
Owen Anderson9f944592009-08-11 20:47:22 +00002922 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
Bill Wendling968f32c2008-03-07 20:49:02 +00002923
Hal Finkel940ab932014-02-28 00:27:01 +00002924 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
Bill Wendling968f32c2008-03-07 20:49:02 +00002925 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
Owen Anderson9f944592009-08-11 20:47:22 +00002926 // value to MVT::i64 and then truncate to the correct register size.
Bill Schmidt57d6de52012-10-23 15:51:16 +00002927 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
Bill Wendling968f32c2008-03-07 20:49:02 +00002928
Chris Lattnerec78cad2006-06-26 22:48:35 +00002929 ++GPR_idx;
2930 } else {
2931 needsLoad = true;
Evan Cheng0f0aee22008-07-24 08:17:07 +00002932 ArgSize = PtrByteSize;
Chris Lattnerec78cad2006-06-26 22:48:35 +00002933 }
Tilmann Scheller773f14c2009-07-03 06:47:08 +00002934 // All int arguments reserve stack space in the Darwin ABI.
2935 ArgOffset += 8;
Chris Lattnerec78cad2006-06-26 22:48:35 +00002936 break;
Scott Michelcf0da6c2009-02-17 22:15:04 +00002937
Owen Anderson9f944592009-08-11 20:47:22 +00002938 case MVT::f32:
2939 case MVT::f64:
Chris Lattner318f0d22006-05-16 18:51:52 +00002940 // Every 4 bytes of argument space consumes one of the GPRs available for
2941 // argument passing.
Tilmann Scheller773f14c2009-07-03 06:47:08 +00002942 if (GPR_idx != Num_GPR_Regs) {
Chris Lattner26e2fcd2006-05-16 18:58:15 +00002943 ++GPR_idx;
Chris Lattner2cca3852006-11-18 01:57:19 +00002944 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
Chris Lattner26e2fcd2006-05-16 18:58:15 +00002945 ++GPR_idx;
Chris Lattner318f0d22006-05-16 18:51:52 +00002946 }
Chris Lattner26e2fcd2006-05-16 18:58:15 +00002947 if (FPR_idx != Num_FPR_Regs) {
Chris Lattner4302e8f2006-05-16 18:18:50 +00002948 unsigned VReg;
Tilmann Scheller98bdaaa2009-07-03 06:43:35 +00002949
Owen Anderson9f944592009-08-11 20:47:22 +00002950 if (ObjectVT == MVT::f32)
Devang Patelf3292b22011-02-21 23:21:26 +00002951 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
Chris Lattner4302e8f2006-05-16 18:18:50 +00002952 else
Devang Patelf3292b22011-02-21 23:21:26 +00002953 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
Tilmann Scheller98bdaaa2009-07-03 06:43:35 +00002954
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002955 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
Chris Lattner4302e8f2006-05-16 18:18:50 +00002956 ++FPR_idx;
2957 } else {
2958 needsLoad = true;
2959 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00002960
Tilmann Scheller773f14c2009-07-03 06:47:08 +00002961 // All FP arguments reserve stack space in the Darwin ABI.
2962 ArgOffset += isPPC64 ? 8 : ObjSize;
Chris Lattner4302e8f2006-05-16 18:18:50 +00002963 break;
Owen Anderson9f944592009-08-11 20:47:22 +00002964 case MVT::v4f32:
2965 case MVT::v4i32:
2966 case MVT::v8i16:
2967 case MVT::v16i8:
Dale Johannesenb28456e2008-03-12 00:22:17 +00002968 // Note that vector arguments in registers don't reserve stack space,
2969 // except in varargs functions.
Chris Lattner26e2fcd2006-05-16 18:58:15 +00002970 if (VR_idx != Num_VR_Regs) {
Devang Patelf3292b22011-02-21 23:21:26 +00002971 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00002972 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
Dale Johannesenb28456e2008-03-12 00:22:17 +00002973 if (isVarArg) {
2974 while ((ArgOffset % 16) != 0) {
2975 ArgOffset += PtrByteSize;
2976 if (GPR_idx != Num_GPR_Regs)
2977 GPR_idx++;
2978 }
2979 ArgOffset += 16;
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00002980 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
Dale Johannesenb28456e2008-03-12 00:22:17 +00002981 }
Chris Lattner4302e8f2006-05-16 18:18:50 +00002982 ++VR_idx;
2983 } else {
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00002984 if (!isVarArg && !isPPC64) {
2985 // Vectors go after all the nonvectors.
2986 CurArgOffset = VecArgOffset;
2987 VecArgOffset += 16;
2988 } else {
2989 // Vectors are aligned.
2990 ArgOffset = ((ArgOffset+15)/16)*16;
2991 CurArgOffset = ArgOffset;
2992 ArgOffset += 16;
Dale Johannesen0d982562008-03-12 00:49:20 +00002993 }
Chris Lattner4302e8f2006-05-16 18:18:50 +00002994 needsLoad = true;
2995 }
2996 break;
2997 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00002998
Chris Lattner4302e8f2006-05-16 18:18:50 +00002999 // We need to load the argument to a virtual register if we determined above
Chris Lattnerf6518cf2008-02-13 07:35:30 +00003000 // that we ran out of physical registers of the appropriate type.
Chris Lattner4302e8f2006-05-16 18:18:50 +00003001 if (needsLoad) {
Chris Lattnerf6518cf2008-02-13 07:35:30 +00003002 int FI = MFI->CreateFixedObject(ObjSize,
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003003 CurArgOffset + (ArgSize - ObjSize),
Evan Cheng0664a672010-07-03 00:40:23 +00003004 isImmutable);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003005 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
Chris Lattner7727d052010-09-21 06:44:06 +00003006 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003007 false, false, false, 0);
Chris Lattner4302e8f2006-05-16 18:18:50 +00003008 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00003009
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003010 InVals.push_back(ArgVal);
Chris Lattner4302e8f2006-05-16 18:18:50 +00003011 }
Dale Johannesenbfa252d2008-03-07 20:27:40 +00003012
Ulrich Weigand2bffb952014-06-23 13:08:27 +00003013 // Allow for Altivec parameters at the end, if needed.
3014 if (nAltivecParamsAtEnd) {
3015 MinReservedArea = ((MinReservedArea+15)/16)*16;
3016 MinReservedArea += 16*nAltivecParamsAtEnd;
3017 }
3018
3019 // Area that is at least reserved in the caller of this function.
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00003020 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
Ulrich Weigand2bffb952014-06-23 13:08:27 +00003021
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003022 // Set the size that is at least reserved in caller of this function. Tail
Bill Schmidt57d6de52012-10-23 15:51:16 +00003023 // call optimized functions' reserved stack space needs to be aligned so that
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003024 // taking the difference between two stack areas will result in an aligned
3025 // stack.
Ulrich Weigand2bffb952014-06-23 13:08:27 +00003026 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3027 FuncInfo->setMinReservedArea(MinReservedArea);
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003028
Chris Lattner4302e8f2006-05-16 18:18:50 +00003029 // If the function takes variable number of arguments, make a frame index for
3030 // the start of the first vararg value... for expansion of llvm.va_start.
Chris Lattner4302e8f2006-05-16 18:18:50 +00003031 if (isVarArg) {
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003032 int Depth = ArgOffset;
Scott Michelcf0da6c2009-02-17 22:15:04 +00003033
Dan Gohman31ae5862010-04-17 14:41:14 +00003034 FuncInfo->setVarArgsFrameIndex(
3035 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
Evan Cheng0664a672010-07-03 00:40:23 +00003036 Depth, true));
Dan Gohman31ae5862010-04-17 14:41:14 +00003037 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
Scott Michelcf0da6c2009-02-17 22:15:04 +00003038
Chris Lattner4302e8f2006-05-16 18:18:50 +00003039 // If this function is vararg, store any remaining integer argument regs
3040 // to their spots on the stack so that they may be loaded by deferencing the
3041 // result of va_next.
Chris Lattner26e2fcd2006-05-16 18:58:15 +00003042 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
Chris Lattner2cca3852006-11-18 01:57:19 +00003043 unsigned VReg;
Wesley Peck527da1b2010-11-23 03:31:01 +00003044
Chris Lattner2cca3852006-11-18 01:57:19 +00003045 if (isPPC64)
Devang Patelf3292b22011-02-21 23:21:26 +00003046 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
Chris Lattner2cca3852006-11-18 01:57:19 +00003047 else
Devang Patelf3292b22011-02-21 23:21:26 +00003048 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
Chris Lattner2cca3852006-11-18 01:57:19 +00003049
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003050 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
Chris Lattner676c61d2010-09-21 18:41:36 +00003051 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3052 MachinePointerInfo(), false, false, 0);
Chris Lattner4302e8f2006-05-16 18:18:50 +00003053 MemOps.push_back(Store);
3054 // Increment the address by four for the next argument to store
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003055 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
Dale Johannesen679073b2009-02-04 02:34:38 +00003056 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
Chris Lattner4302e8f2006-05-16 18:18:50 +00003057 }
Chris Lattner4302e8f2006-05-16 18:18:50 +00003058 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00003059
Dale Johannesenbfa252d2008-03-07 20:27:40 +00003060 if (!MemOps.empty())
Craig Topper48d114b2014-04-26 18:35:24 +00003061 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
Dale Johannesenbfa252d2008-03-07 20:27:40 +00003062
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003063 return Chain;
Chris Lattner4302e8f2006-05-16 18:18:50 +00003064}
3065
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003066/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
Chris Lattner0ab5e2c2011-04-15 05:18:47 +00003067/// adjusted to accommodate the arguments for the tailcall.
Dale Johannesen86dcae12009-11-24 01:09:07 +00003068static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003069 unsigned ParamSize) {
3070
Dale Johannesen86dcae12009-11-24 01:09:07 +00003071 if (!isTailCall) return 0;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003072
3073 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3074 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3075 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3076 // Remember only if the new adjustement is bigger.
3077 if (SPDiff < FI->getTailCallSPDelta())
3078 FI->setTailCallSPDelta(SPDiff);
3079
3080 return SPDiff;
3081}
3082
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003083/// IsEligibleForTailCallOptimization - Check whether the call is eligible
3084/// for tail call optimization. Targets which want to do tail call
3085/// optimization should implement this function.
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003086bool
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003087PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
Sandeep Patel68c5f472009-09-02 08:44:58 +00003088 CallingConv::ID CalleeCC,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003089 bool isVarArg,
3090 const SmallVectorImpl<ISD::InputArg> &Ins,
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003091 SelectionDAG& DAG) const {
Nick Lewycky50f02cb2011-12-02 22:16:29 +00003092 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
Evan Cheng25217ff2010-01-29 23:05:56 +00003093 return false;
3094
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003095 // Variable argument functions are not supported.
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003096 if (isVarArg)
Dan Gohmaneffb8942008-09-12 16:56:44 +00003097 return false;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003098
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003099 MachineFunction &MF = DAG.getMachineFunction();
Sandeep Patel68c5f472009-09-02 08:44:58 +00003100 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003101 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3102 // Functions containing by val parameters are not supported.
3103 for (unsigned i = 0; i != Ins.size(); i++) {
3104 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3105 if (Flags.isByVal()) return false;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003106 }
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003107
Alp Tokerf907b892013-12-05 05:44:44 +00003108 // Non-PIC/GOT tail calls are supported.
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003109 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3110 return true;
3111
3112 // At the moment we can only do local tail calls (in same module, hidden
3113 // or protected) if we are generating PIC.
3114 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3115 return G->getGlobal()->hasHiddenVisibility()
3116 || G->getGlobal()->hasProtectedVisibility();
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003117 }
3118
3119 return false;
3120}
3121
Chris Lattnereb755fc2006-05-17 19:00:46 +00003122/// isCallCompatibleAddress - Return the immediate to use if the specified
3123/// 32-bit value is representable in the immediate field of a BxA instruction.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003124static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
Chris Lattnereb755fc2006-05-17 19:00:46 +00003125 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
Craig Topper062a2ba2014-04-25 05:30:21 +00003126 if (!C) return nullptr;
Scott Michelcf0da6c2009-02-17 22:15:04 +00003127
Dan Gohmaneffb8942008-09-12 16:56:44 +00003128 int Addr = C->getZExtValue();
Chris Lattnereb755fc2006-05-17 19:00:46 +00003129 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
Richard Smith228e6d42012-08-24 23:29:28 +00003130 SignExtend32<26>(Addr) != Addr)
Craig Topper062a2ba2014-04-25 05:30:21 +00003131 return nullptr; // Top 6 bits have to be sext of immediate.
Scott Michelcf0da6c2009-02-17 22:15:04 +00003132
Dan Gohmaneffb8942008-09-12 16:56:44 +00003133 return DAG.getConstant((int)C->getZExtValue() >> 2,
Gabor Greiff304a7a2008-08-28 21:40:38 +00003134 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
Chris Lattnereb755fc2006-05-17 19:00:46 +00003135}
3136
Dan Gohmand78c4002008-05-13 00:00:25 +00003137namespace {
3138
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003139struct TailCallArgumentInfo {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003140 SDValue Arg;
3141 SDValue FrameIdxOp;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003142 int FrameIdx;
3143
3144 TailCallArgumentInfo() : FrameIdx(0) {}
3145};
3146
Dan Gohmand78c4002008-05-13 00:00:25 +00003147}
3148
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003149/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3150static void
3151StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
Evan Cheng0e9d9ca2009-10-18 18:16:27 +00003152 SDValue Chain,
Craig Topperb94011f2013-07-14 04:42:23 +00003153 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3154 SmallVectorImpl<SDValue> &MemOpChains,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003155 SDLoc dl) {
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003156 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003157 SDValue Arg = TailCallArgs[i].Arg;
3158 SDValue FIN = TailCallArgs[i].FrameIdxOp;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003159 int FI = TailCallArgs[i].FrameIdx;
3160 // Store relative to framepointer.
Dale Johannesen021052a2009-02-04 20:06:27 +00003161 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
Chris Lattner7727d052010-09-21 06:44:06 +00003162 MachinePointerInfo::getFixedStack(FI),
3163 false, false, 0));
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003164 }
3165}
3166
3167/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3168/// the appropriate stack slot for the tail call optimized function call.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003169static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003170 MachineFunction &MF,
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003171 SDValue Chain,
3172 SDValue OldRetAddr,
3173 SDValue OldFP,
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003174 int SPDiff,
3175 bool isPPC64,
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003176 bool isDarwinABI,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003177 SDLoc dl) {
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003178 if (SPDiff) {
3179 // Calculate the new stack slot for the return address.
3180 int SlotSize = isPPC64 ? 8 : 4;
Anton Korobeynikov2f931282011-01-10 12:39:04 +00003181 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003182 isDarwinABI);
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003183 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
Evan Cheng0664a672010-07-03 00:40:23 +00003184 NewRetAddrLoc, true);
Owen Anderson9f944592009-08-11 20:47:22 +00003185 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003186 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
Dale Johannesen021052a2009-02-04 20:06:27 +00003187 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
Chris Lattner7727d052010-09-21 06:44:06 +00003188 MachinePointerInfo::getFixedStack(NewRetAddr),
David Greene87a5abe2010-02-15 16:56:53 +00003189 false, false, 0);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003190
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00003191 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3192 // slot as the FP is never overwritten.
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003193 if (isDarwinABI) {
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003194 int NewFPLoc =
Anton Korobeynikov2f931282011-01-10 12:39:04 +00003195 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
David Greene1fbe0542009-11-12 20:49:22 +00003196 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
Evan Cheng0664a672010-07-03 00:40:23 +00003197 true);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003198 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3199 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
Chris Lattner7727d052010-09-21 06:44:06 +00003200 MachinePointerInfo::getFixedStack(NewFPIdx),
David Greene87a5abe2010-02-15 16:56:53 +00003201 false, false, 0);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003202 }
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003203 }
3204 return Chain;
3205}
3206
3207/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3208/// the position of the argument.
3209static void
3210CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003211 SDValue Arg, int SPDiff, unsigned ArgOffset,
Craig Topperb94011f2013-07-14 04:42:23 +00003212 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003213 int Offset = ArgOffset + SPDiff;
Duncan Sands13237ac2008-06-06 12:08:01 +00003214 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
Evan Cheng0664a672010-07-03 00:40:23 +00003215 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
Owen Anderson9f944592009-08-11 20:47:22 +00003216 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003217 SDValue FIN = DAG.getFrameIndex(FI, VT);
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003218 TailCallArgumentInfo Info;
3219 Info.Arg = Arg;
3220 Info.FrameIdxOp = FIN;
3221 Info.FrameIdx = FI;
3222 TailCallArguments.push_back(Info);
3223}
3224
3225/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3226/// stack slot. Returns the chain as result and the loaded frame pointers in
3227/// LROpOut/FPOpout. Used when tail calling.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003228SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
Dale Johannesen021052a2009-02-04 20:06:27 +00003229 int SPDiff,
3230 SDValue Chain,
3231 SDValue &LROpOut,
3232 SDValue &FPOpOut,
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003233 bool isDarwinABI,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003234 SDLoc dl) const {
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003235 if (SPDiff) {
3236 // Load the LR and FP stack slot for later adjusting.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00003237 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003238 LROpOut = getReturnAddrFrameIndex(DAG);
Chris Lattner7727d052010-09-21 06:44:06 +00003239 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003240 false, false, false, 0);
Gabor Greiff304a7a2008-08-28 21:40:38 +00003241 Chain = SDValue(LROpOut.getNode(), 1);
Wesley Peck527da1b2010-11-23 03:31:01 +00003242
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00003243 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3244 // slot as the FP is never overwritten.
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003245 if (isDarwinABI) {
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003246 FPOpOut = getFramePointerFrameIndex(DAG);
Chris Lattner7727d052010-09-21 06:44:06 +00003247 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00003248 false, false, false, 0);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003249 Chain = SDValue(FPOpOut.getNode(), 1);
3250 }
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003251 }
3252 return Chain;
3253}
3254
Dale Johannesen85d41a12008-03-04 23:17:14 +00003255/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
Scott Michelcf0da6c2009-02-17 22:15:04 +00003256/// by "Src" to address "Dst" of size "Size". Alignment information is
Dale Johannesen85d41a12008-03-04 23:17:14 +00003257/// specified by the specific parameter attribute. The copy will be passed as
3258/// a byval function parameter.
3259/// Sometimes what we are copying is the end of a larger object, the part that
3260/// does not fit in registers.
Scott Michelcf0da6c2009-02-17 22:15:04 +00003261static SDValue
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003262CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
Duncan Sandsd97eea32008-03-21 09:14:45 +00003263 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003264 SDLoc dl) {
Owen Anderson9f944592009-08-11 20:47:22 +00003265 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
Dale Johannesen85263882009-02-04 01:17:06 +00003266 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
Nick Lewyckyaad475b2014-04-15 07:22:52 +00003267 false, false, MachinePointerInfo(),
3268 MachinePointerInfo());
Dale Johannesen85d41a12008-03-04 23:17:14 +00003269}
Chris Lattner43df5b32007-02-25 05:34:32 +00003270
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003271/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3272/// tail calls.
3273static void
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003274LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3275 SDValue Arg, SDValue PtrOff, int SPDiff,
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003276 unsigned ArgOffset, bool isPPC64, bool isTailCall,
Craig Topperb94011f2013-07-14 04:42:23 +00003277 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3278 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003279 SDLoc dl) {
Owen Anderson53aa7a92009-08-10 22:56:29 +00003280 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003281 if (!isTailCall) {
3282 if (isVector) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00003283 SDValue StackPtr;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003284 if (isPPC64)
Owen Anderson9f944592009-08-11 20:47:22 +00003285 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003286 else
Owen Anderson9f944592009-08-11 20:47:22 +00003287 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
Dale Johannesen021052a2009-02-04 20:06:27 +00003288 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003289 DAG.getConstant(ArgOffset, PtrVT));
3290 }
Chris Lattner676c61d2010-09-21 18:41:36 +00003291 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3292 MachinePointerInfo(), false, false, 0));
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00003293 // Calculate and remember argument location.
3294 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3295 TailCallArguments);
3296}
3297
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003298static
3299void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003300 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003301 SDValue LROp, SDValue FPOp, bool isDarwinABI,
Craig Topperb94011f2013-07-14 04:42:23 +00003302 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003303 MachineFunction &MF = DAG.getMachineFunction();
3304
3305 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3306 // might overwrite each other in case of tail call optimization.
3307 SmallVector<SDValue, 8> MemOpChains2;
Chris Lattner0ab5e2c2011-04-15 05:18:47 +00003308 // Do not flag preceding copytoreg stuff together with the following stuff.
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003309 InFlag = SDValue();
3310 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3311 MemOpChains2, dl);
3312 if (!MemOpChains2.empty())
Craig Topper48d114b2014-04-26 18:35:24 +00003313 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003314
3315 // Store the return address to the appropriate stack slot.
3316 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3317 isPPC64, isDarwinABI, dl);
3318
3319 // Emit callseq_end just before tailcall node.
3320 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
Andrew Trickad6d08a2013-05-29 22:03:55 +00003321 DAG.getIntPtrConstant(0, true), InFlag, dl);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003322 InFlag = Chain.getValue(1);
3323}
3324
3325static
3326unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003327 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
Craig Topperb94011f2013-07-14 04:42:23 +00003328 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3329 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
Eric Christopherb1aaebe2014-06-12 22:38:18 +00003330 const PPCSubtarget &Subtarget) {
Wesley Peck527da1b2010-11-23 03:31:01 +00003331
Eric Christopherb1aaebe2014-06-12 22:38:18 +00003332 bool isPPC64 = Subtarget.isPPC64();
3333 bool isSVR4ABI = Subtarget.isSVR4ABI();
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003334
Owen Anderson53aa7a92009-08-10 22:56:29 +00003335 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Owen Anderson9f944592009-08-11 20:47:22 +00003336 NodeTys.push_back(MVT::Other); // Returns a chain
Chris Lattner3e5fbd72010-12-21 02:38:05 +00003337 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003338
Ulrich Weigandf62e83f2013-03-22 15:24:13 +00003339 unsigned CallOpc = PPCISD::CALL;
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003340
Torok Edwin31e90d22010-08-04 20:47:44 +00003341 bool needIndirectCall = true;
Ulrich Weigand9aa09ef2014-06-18 16:14:04 +00003342 if (!isSVR4ABI || !isPPC64)
3343 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3344 // If this is an absolute destination address, use the munged value.
3345 Callee = SDValue(Dest, 0);
3346 needIndirectCall = false;
3347 }
Wesley Peck527da1b2010-11-23 03:31:01 +00003348
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003349 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3350 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3351 // Use indirect calls for ALL functions calls in JIT mode, since the
3352 // far-call stubs may be outside relocation limits for a BL instruction.
3353 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3354 unsigned OpFlags = 0;
3355 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
Eric Christopherb1aaebe2014-06-12 22:38:18 +00003356 (Subtarget.getTargetTriple().isMacOSX() &&
3357 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003358 (G->getGlobal()->isDeclaration() ||
3359 G->getGlobal()->isWeakForLinker())) {
3360 // PC-relative references to external symbols should go through $stub,
3361 // unless we're building with the leopard linker or later, which
3362 // automatically synthesizes these stubs.
3363 OpFlags = PPCII::MO_DARWIN_STUB;
3364 }
Wesley Peck527da1b2010-11-23 03:31:01 +00003365
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003366 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3367 // every direct call is) turn it into a TargetGlobalAddress /
3368 // TargetExternalSymbol node so that legalize doesn't hack it.
Torok Edwin31e90d22010-08-04 20:47:44 +00003369 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003370 Callee.getValueType(),
3371 0, OpFlags);
Torok Edwin31e90d22010-08-04 20:47:44 +00003372 needIndirectCall = false;
Wesley Peck527da1b2010-11-23 03:31:01 +00003373 }
Torok Edwin31e90d22010-08-04 20:47:44 +00003374 }
Wesley Peck527da1b2010-11-23 03:31:01 +00003375
Torok Edwin31e90d22010-08-04 20:47:44 +00003376 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003377 unsigned char OpFlags = 0;
Wesley Peck527da1b2010-11-23 03:31:01 +00003378
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003379 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
Eric Christopherb1aaebe2014-06-12 22:38:18 +00003380 (Subtarget.getTargetTriple().isMacOSX() &&
3381 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003382 // PC-relative references to external symbols should go through $stub,
3383 // unless we're building with the leopard linker or later, which
3384 // automatically synthesizes these stubs.
3385 OpFlags = PPCII::MO_DARWIN_STUB;
3386 }
Wesley Peck527da1b2010-11-23 03:31:01 +00003387
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003388 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3389 OpFlags);
3390 needIndirectCall = false;
Torok Edwin31e90d22010-08-04 20:47:44 +00003391 }
Wesley Peck527da1b2010-11-23 03:31:01 +00003392
Torok Edwin31e90d22010-08-04 20:47:44 +00003393 if (needIndirectCall) {
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003394 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3395 // to do the call, we can't use PPCISD::CALL.
3396 SDValue MTCTROps[] = {Chain, Callee, InFlag};
Tilmann Scheller79fef932009-12-18 13:00:15 +00003397
3398 if (isSVR4ABI && isPPC64) {
3399 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3400 // entry point, but to the function descriptor (the function entry point
3401 // address is part of the function descriptor though).
3402 // The function descriptor is a three doubleword structure with the
3403 // following fields: function entry point, TOC base address and
3404 // environment pointer.
3405 // Thus for a call through a function pointer, the following actions need
3406 // to be performed:
3407 // 1. Save the TOC of the caller in the TOC save area of its stack
Bill Schmidt57d6de52012-10-23 15:51:16 +00003408 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
Tilmann Scheller79fef932009-12-18 13:00:15 +00003409 // 2. Load the address of the function entry point from the function
3410 // descriptor.
3411 // 3. Load the TOC of the callee from the function descriptor into r2.
3412 // 4. Load the environment pointer from the function descriptor into
3413 // r11.
3414 // 5. Branch to the function entry point address.
3415 // 6. On return of the callee, the TOC of the caller needs to be
3416 // restored (this is done in FinishCall()).
3417 //
3418 // All those operations are flagged together to ensure that no other
3419 // operations can be scheduled in between. E.g. without flagging the
3420 // operations together, a TOC access in the caller could be scheduled
3421 // between the load of the callee TOC and the branch to the callee, which
3422 // results in the TOC access going through the TOC of the callee instead
3423 // of going through the TOC of the caller, which leads to incorrect code.
3424
3425 // Load the address of the function entry point from the function
3426 // descriptor.
Chris Lattner3e5fbd72010-12-21 02:38:05 +00003427 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
Craig Topper48d114b2014-04-26 18:35:24 +00003428 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
Craig Topper2d2aa0c2014-04-30 07:17:30 +00003429 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
Tilmann Scheller79fef932009-12-18 13:00:15 +00003430 Chain = LoadFuncPtr.getValue(1);
3431 InFlag = LoadFuncPtr.getValue(2);
3432
3433 // Load environment pointer into r11.
3434 // Offset of the environment pointer within the function descriptor.
3435 SDValue PtrOff = DAG.getIntPtrConstant(16);
3436
3437 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3438 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3439 InFlag);
3440 Chain = LoadEnvPtr.getValue(1);
3441 InFlag = LoadEnvPtr.getValue(2);
3442
3443 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3444 InFlag);
3445 Chain = EnvVal.getValue(0);
3446 InFlag = EnvVal.getValue(1);
3447
3448 // Load TOC of the callee into r2. We are using a target-specific load
3449 // with r2 hard coded, because the result of a target-independent load
3450 // would never go directly into r2, since r2 is a reserved register (which
3451 // prevents the register allocator from allocating it), resulting in an
3452 // additional register being allocated and an unnecessary move instruction
3453 // being generated.
Chris Lattner3e5fbd72010-12-21 02:38:05 +00003454 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
Ulrich Weigandad0cb912014-06-18 17:52:49 +00003455 SDValue TOCOff = DAG.getIntPtrConstant(8);
3456 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
Tilmann Scheller79fef932009-12-18 13:00:15 +00003457 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
Ulrich Weigandad0cb912014-06-18 17:52:49 +00003458 AddTOC, InFlag);
Tilmann Scheller79fef932009-12-18 13:00:15 +00003459 Chain = LoadTOCPtr.getValue(0);
3460 InFlag = LoadTOCPtr.getValue(1);
3461
3462 MTCTROps[0] = Chain;
3463 MTCTROps[1] = LoadFuncPtr;
3464 MTCTROps[2] = InFlag;
3465 }
3466
Craig Topper48d114b2014-04-26 18:35:24 +00003467 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
Craig Topper2d2aa0c2014-04-30 07:17:30 +00003468 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003469 InFlag = Chain.getValue(1);
3470
3471 NodeTys.clear();
Owen Anderson9f944592009-08-11 20:47:22 +00003472 NodeTys.push_back(MVT::Other);
Chris Lattner3e5fbd72010-12-21 02:38:05 +00003473 NodeTys.push_back(MVT::Glue);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003474 Ops.push_back(Chain);
Ulrich Weigandf62e83f2013-03-22 15:24:13 +00003475 CallOpc = PPCISD::BCTRL;
Craig Topper062a2ba2014-04-25 05:30:21 +00003476 Callee.setNode(nullptr);
Ulrich Weigandf62e83f2013-03-22 15:24:13 +00003477 // Add use of X11 (holding environment pointer)
3478 if (isSVR4ABI && isPPC64)
3479 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003480 // Add CTR register as callee so a bctr can be emitted later.
3481 if (isTailCall)
Roman Divackya4a59ae2011-06-03 15:47:49 +00003482 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003483 }
3484
3485 // If this is a direct call, pass the chain and the callee.
3486 if (Callee.getNode()) {
3487 Ops.push_back(Chain);
3488 Ops.push_back(Callee);
3489 }
3490 // If this is a tail call add stack pointer delta.
3491 if (isTailCall)
Owen Anderson9f944592009-08-11 20:47:22 +00003492 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003493
3494 // Add argument registers to the end of the list so that they are known live
3495 // into the call.
3496 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3497 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3498 RegsToPass[i].second.getValueType()));
3499
3500 return CallOpc;
3501}
3502
Roman Divacky76293062012-09-18 16:47:58 +00003503static
3504bool isLocalCall(const SDValue &Callee)
3505{
3506 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
Roman Divacky09adf3d2012-09-18 18:27:49 +00003507 return !G->getGlobal()->isDeclaration() &&
3508 !G->getGlobal()->isWeakForLinker();
Roman Divacky76293062012-09-18 16:47:58 +00003509 return false;
3510}
3511
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003512SDValue
3513PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel68c5f472009-09-02 08:44:58 +00003514 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003515 const SmallVectorImpl<ISD::InputArg> &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003516 SDLoc dl, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +00003517 SmallVectorImpl<SDValue> &InVals) const {
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003518
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003519 SmallVector<CCValAssign, 16> RVLocs;
Eric Christopher0713a9d2011-06-08 23:55:35 +00003520 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Gabor Greif180c4442012-04-19 15:16:31 +00003521 getTargetMachine(), RVLocs, *DAG.getContext());
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003522 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003523
3524 // Copy all of the result registers out of their specified physreg.
3525 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3526 CCValAssign &VA = RVLocs[i];
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003527 assert(VA.isRegLoc() && "Can only return in registers!");
Ulrich Weigand339d0592012-11-05 19:39:45 +00003528
3529 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3530 VA.getLocReg(), VA.getLocVT(), InFlag);
3531 Chain = Val.getValue(1);
3532 InFlag = Val.getValue(2);
3533
3534 switch (VA.getLocInfo()) {
3535 default: llvm_unreachable("Unknown loc info!");
3536 case CCValAssign::Full: break;
3537 case CCValAssign::AExt:
3538 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3539 break;
3540 case CCValAssign::ZExt:
3541 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3542 DAG.getValueType(VA.getValVT()));
3543 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3544 break;
3545 case CCValAssign::SExt:
3546 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3547 DAG.getValueType(VA.getValVT()));
3548 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3549 break;
3550 }
3551
3552 InVals.push_back(Val);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003553 }
3554
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003555 return Chain;
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003556}
3557
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003558SDValue
Andrew Trickef9de2a2013-05-25 02:42:55 +00003559PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
Sandeep Patel68c5f472009-09-02 08:44:58 +00003560 bool isTailCall, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003561 SelectionDAG &DAG,
3562 SmallVector<std::pair<unsigned, SDValue>, 8>
3563 &RegsToPass,
3564 SDValue InFlag, SDValue Chain,
3565 SDValue &Callee,
3566 int SPDiff, unsigned NumBytes,
3567 const SmallVectorImpl<ISD::InputArg> &Ins,
Dan Gohman21cea8a2010-04-17 15:26:15 +00003568 SmallVectorImpl<SDValue> &InVals) const {
Owen Anderson53aa7a92009-08-10 22:56:29 +00003569 std::vector<EVT> NodeTys;
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003570 SmallVector<SDValue, 8> Ops;
3571 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3572 isTailCall, RegsToPass, Ops, NodeTys,
Eric Christopherb1aaebe2014-06-12 22:38:18 +00003573 Subtarget);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003574
Hal Finkel5ab37802012-08-28 02:10:27 +00003575 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
Eric Christopherb1aaebe2014-06-12 22:38:18 +00003576 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
Hal Finkel5ab37802012-08-28 02:10:27 +00003577 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3578
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003579 // When performing tail call optimization the callee pops its arguments off
3580 // the stack. Account for this here so these bytes can be pushed back on in
Eli Bendersky8da87162013-02-21 20:05:00 +00003581 // PPCFrameLowering::eliminateCallFramePseudoInstr.
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003582 int BytesCalleePops =
Nick Lewycky50f02cb2011-12-02 22:16:29 +00003583 (CallConv == CallingConv::Fast &&
3584 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003585
Roman Divackyef21be22012-03-06 16:41:49 +00003586 // Add a register mask operand representing the call-preserved registers.
3587 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3588 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3589 assert(Mask && "Missing call preserved mask for calling convention");
3590 Ops.push_back(DAG.getRegisterMask(Mask));
3591
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003592 if (InFlag.getNode())
3593 Ops.push_back(InFlag);
3594
3595 // Emit tail call.
3596 if (isTailCall) {
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003597 assert(((Callee.getOpcode() == ISD::Register &&
3598 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3599 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3600 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3601 isa<ConstantSDNode>(Callee)) &&
3602 "Expecting an global address, external symbol, absolute value or register");
3603
Craig Topper48d114b2014-04-26 18:35:24 +00003604 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003605 }
3606
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00003607 // Add a NOP immediately after the branch instruction when using the 64-bit
3608 // SVR4 ABI. At link time, if caller and callee are in a different module and
3609 // thus have a different TOC, the call will be replaced with a call to a stub
3610 // function which saves the current TOC, loads the TOC of the callee and
3611 // branches to the callee. The NOP will be replaced with a load instruction
3612 // which restores the TOC of the caller from the TOC save slot of the current
3613 // stack frame. If caller and callee belong to the same module (and have the
3614 // same TOC), the NOP will remain unchanged.
Hal Finkel51861b42012-03-31 14:45:15 +00003615
3616 bool needsTOCRestore = false;
Eric Christopherb1aaebe2014-06-12 22:38:18 +00003617 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
Ulrich Weigandf62e83f2013-03-22 15:24:13 +00003618 if (CallOpc == PPCISD::BCTRL) {
Tilmann Scheller79fef932009-12-18 13:00:15 +00003619 // This is a call through a function pointer.
3620 // Restore the caller TOC from the save area into R2.
3621 // See PrepareCall() for more information about calls through function
3622 // pointers in the 64-bit SVR4 ABI.
3623 // We are using a target-specific load with r2 hard coded, because the
3624 // result of a target-independent load would never go directly into r2,
3625 // since r2 is a reserved register (which prevents the register allocator
3626 // from allocating it), resulting in an additional register being
3627 // allocated and an unnecessary move instruction being generated.
Hal Finkel51861b42012-03-31 14:45:15 +00003628 needsTOCRestore = true;
Bill Schmidtcea15962013-09-26 17:09:28 +00003629 } else if ((CallOpc == PPCISD::CALL) &&
3630 (!isLocalCall(Callee) ||
3631 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
Roman Divacky76293062012-09-18 16:47:58 +00003632 // Otherwise insert NOP for non-local calls.
Ulrich Weigandf62e83f2013-03-22 15:24:13 +00003633 CallOpc = PPCISD::CALL_NOP;
Tilmann Scheller79fef932009-12-18 13:00:15 +00003634 }
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00003635 }
3636
Craig Topper48d114b2014-04-26 18:35:24 +00003637 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
Hal Finkel51861b42012-03-31 14:45:15 +00003638 InFlag = Chain.getValue(1);
3639
3640 if (needsTOCRestore) {
3641 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
Ulrich Weigandad0cb912014-06-18 17:52:49 +00003642 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3643 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3644 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
3645 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3646 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3647 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
Hal Finkel51861b42012-03-31 14:45:15 +00003648 InFlag = Chain.getValue(1);
3649 }
3650
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003651 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3652 DAG.getIntPtrConstant(BytesCalleePops, true),
Andrew Trickad6d08a2013-05-29 22:03:55 +00003653 InFlag, dl);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003654 if (!Ins.empty())
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003655 InFlag = Chain.getValue(1);
3656
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003657 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3658 Ins, dl, DAG, InVals);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003659}
3660
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003661SDValue
Justin Holewinskiaa583972012-05-25 16:35:28 +00003662PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Dan Gohman21cea8a2010-04-17 15:26:15 +00003663 SmallVectorImpl<SDValue> &InVals) const {
Justin Holewinskiaa583972012-05-25 16:35:28 +00003664 SelectionDAG &DAG = CLI.DAG;
Craig Topperb94011f2013-07-14 04:42:23 +00003665 SDLoc &dl = CLI.DL;
3666 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3667 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3668 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
Justin Holewinskiaa583972012-05-25 16:35:28 +00003669 SDValue Chain = CLI.Chain;
3670 SDValue Callee = CLI.Callee;
3671 bool &isTailCall = CLI.IsTailCall;
3672 CallingConv::ID CallConv = CLI.CallConv;
3673 bool isVarArg = CLI.IsVarArg;
3674
Evan Cheng67a69dd2010-01-27 00:07:07 +00003675 if (isTailCall)
3676 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3677 Ins, DAG);
3678
Reid Kleckner5772b772014-04-24 20:14:34 +00003679 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3680 report_fatal_error("failed to perform tail call elimination on a call "
3681 "site marked musttail");
3682
Eric Christopherb1aaebe2014-06-12 22:38:18 +00003683 if (Subtarget.isSVR4ABI()) {
3684 if (Subtarget.isPPC64())
Bill Schmidt57d6de52012-10-23 15:51:16 +00003685 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3686 isTailCall, Outs, OutVals, Ins,
3687 dl, DAG, InVals);
3688 else
3689 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3690 isTailCall, Outs, OutVals, Ins,
3691 dl, DAG, InVals);
3692 }
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003693
Bill Schmidt57d6de52012-10-23 15:51:16 +00003694 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3695 isTailCall, Outs, OutVals, Ins,
3696 dl, DAG, InVals);
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003697}
3698
3699SDValue
Bill Schmidt019cc6f2012-09-19 15:42:13 +00003700PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3701 CallingConv::ID CallConv, bool isVarArg,
3702 bool isTailCall,
3703 const SmallVectorImpl<ISD::OutputArg> &Outs,
3704 const SmallVectorImpl<SDValue> &OutVals,
3705 const SmallVectorImpl<ISD::InputArg> &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003706 SDLoc dl, SelectionDAG &DAG,
Bill Schmidt019cc6f2012-09-19 15:42:13 +00003707 SmallVectorImpl<SDValue> &InVals) const {
3708 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
Tilmann Schellerd1aaa322009-08-15 11:54:46 +00003709 // of the 32-bit SVR4 ABI stack frame layout.
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003710
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003711 assert((CallConv == CallingConv::C ||
3712 CallConv == CallingConv::Fast) && "Unknown calling convention!");
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003713
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003714 unsigned PtrByteSize = 4;
3715
3716 MachineFunction &MF = DAG.getMachineFunction();
3717
3718 // Mark this function as potentially containing a function that contains a
3719 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3720 // and restoring the callers stack pointer in this functions epilog. This is
3721 // done because by tail calling the called function might overwrite the value
3722 // in this function's (MF) stack pointer stack slot 0(SP).
Nick Lewycky50f02cb2011-12-02 22:16:29 +00003723 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3724 CallConv == CallingConv::Fast)
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003725 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
Wesley Peck527da1b2010-11-23 03:31:01 +00003726
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003727 // Count how many bytes are to be pushed on the stack, including the linkage
3728 // area, parameter list area and the part of the local variable space which
3729 // contains copies of aggregates which are passed by value.
3730
3731 // Assign locations to all of the outgoing arguments.
3732 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher0713a9d2011-06-08 23:55:35 +00003733 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Gabor Greif180c4442012-04-19 15:16:31 +00003734 getTargetMachine(), ArgLocs, *DAG.getContext());
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003735
3736 // Reserve space for the linkage area on the stack.
Anton Korobeynikov2f931282011-01-10 12:39:04 +00003737 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003738
3739 if (isVarArg) {
3740 // Handle fixed and variable vector arguments differently.
3741 // Fixed vector arguments go into registers as long as registers are
3742 // available. Variable vector arguments always go into memory.
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003743 unsigned NumArgs = Outs.size();
Wesley Peck527da1b2010-11-23 03:31:01 +00003744
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003745 for (unsigned i = 0; i != NumArgs; ++i) {
Duncan Sandsf5dda012010-11-03 11:35:31 +00003746 MVT ArgVT = Outs[i].VT;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003747 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003748 bool Result;
Wesley Peck527da1b2010-11-23 03:31:01 +00003749
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003750 if (Outs[i].IsFixed) {
Bill Schmidtef17c142013-02-06 17:33:58 +00003751 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3752 CCInfo);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003753 } else {
Bill Schmidtef17c142013-02-06 17:33:58 +00003754 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3755 ArgFlags, CCInfo);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003756 }
Wesley Peck527da1b2010-11-23 03:31:01 +00003757
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003758 if (Result) {
Torok Edwinfb8d6d52009-07-08 20:53:28 +00003759#ifndef NDEBUG
Chris Lattner13626022009-08-23 06:03:38 +00003760 errs() << "Call operand #" << i << " has unhandled type "
Duncan Sandsf5dda012010-11-03 11:35:31 +00003761 << EVT(ArgVT).getEVTString() << "\n";
Torok Edwinfb8d6d52009-07-08 20:53:28 +00003762#endif
Craig Toppere73658d2014-04-28 04:05:08 +00003763 llvm_unreachable(nullptr);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003764 }
3765 }
3766 } else {
3767 // All arguments are treated the same.
Bill Schmidtef17c142013-02-06 17:33:58 +00003768 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003769 }
Wesley Peck527da1b2010-11-23 03:31:01 +00003770
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003771 // Assign locations to all of the outgoing aggregate by value arguments.
3772 SmallVector<CCValAssign, 16> ByValArgLocs;
Eric Christopher0713a9d2011-06-08 23:55:35 +00003773 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Gabor Greif180c4442012-04-19 15:16:31 +00003774 getTargetMachine(), ByValArgLocs, *DAG.getContext());
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003775
3776 // Reserve stack space for the allocations in CCInfo.
3777 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3778
Bill Schmidtef17c142013-02-06 17:33:58 +00003779 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003780
3781 // Size of the linkage area, parameter list area and the part of the local
3782 // space variable where copies of aggregates which are passed by value are
3783 // stored.
3784 unsigned NumBytes = CCByValInfo.getNextStackOffset();
Wesley Peck527da1b2010-11-23 03:31:01 +00003785
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003786 // Calculate by how many bytes the stack has to be adjusted in case of tail
3787 // call optimization.
3788 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3789
3790 // Adjust the stack pointer for the new arguments...
3791 // These operations are automatically eliminated by the prolog/epilog pass
Andrew Trickad6d08a2013-05-29 22:03:55 +00003792 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3793 dl);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003794 SDValue CallSeqStart = Chain;
3795
3796 // Load the return address and frame pointer so it can be moved somewhere else
3797 // later.
3798 SDValue LROp, FPOp;
3799 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3800 dl);
3801
3802 // Set up a copy of the stack pointer for use loading and storing any
3803 // arguments that may not fit in the registers available for argument
3804 // passing.
Owen Anderson9f944592009-08-11 20:47:22 +00003805 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
Wesley Peck527da1b2010-11-23 03:31:01 +00003806
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003807 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3808 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3809 SmallVector<SDValue, 8> MemOpChains;
3810
Roman Divacky71038e72011-08-30 17:04:16 +00003811 bool seenFloatArg = false;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003812 // Walk the register/memloc assignments, inserting copies/loads.
3813 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3814 i != e;
3815 ++i) {
3816 CCValAssign &VA = ArgLocs[i];
Dan Gohmanfe7532a2010-07-07 15:54:55 +00003817 SDValue Arg = OutVals[i];
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003818 ISD::ArgFlagsTy Flags = Outs[i].Flags;
Wesley Peck527da1b2010-11-23 03:31:01 +00003819
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003820 if (Flags.isByVal()) {
3821 // Argument is an aggregate which is passed by value, thus we need to
3822 // create a copy of it in the local variable space of the current stack
3823 // frame (which is the stack frame of the caller) and pass the address of
3824 // this copy to the callee.
3825 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3826 CCValAssign &ByValVA = ByValArgLocs[j++];
3827 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
Wesley Peck527da1b2010-11-23 03:31:01 +00003828
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003829 // Memory reserved in the local variable space of the callers stack frame.
3830 unsigned LocMemOffset = ByValVA.getLocMemOffset();
Wesley Peck527da1b2010-11-23 03:31:01 +00003831
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003832 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3833 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
Wesley Peck527da1b2010-11-23 03:31:01 +00003834
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003835 // Create a copy of the argument in the local area of the current
3836 // stack frame.
3837 SDValue MemcpyCall =
3838 CreateCopyOfByValArgument(Arg, PtrOff,
3839 CallSeqStart.getNode()->getOperand(0),
3840 Flags, DAG, dl);
Wesley Peck527da1b2010-11-23 03:31:01 +00003841
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003842 // This must go outside the CALLSEQ_START..END.
3843 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
Andrew Trickad6d08a2013-05-29 22:03:55 +00003844 CallSeqStart.getNode()->getOperand(1),
3845 SDLoc(MemcpyCall));
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003846 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3847 NewCallSeqStart.getNode());
3848 Chain = CallSeqStart = NewCallSeqStart;
Wesley Peck527da1b2010-11-23 03:31:01 +00003849
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003850 // Pass the address of the aggregate copy on the stack either in a
3851 // physical register or in the parameter list area of the current stack
3852 // frame to the callee.
3853 Arg = PtrOff;
3854 }
Wesley Peck527da1b2010-11-23 03:31:01 +00003855
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003856 if (VA.isRegLoc()) {
Hal Finkel2a9d3182014-03-06 00:23:33 +00003857 if (Arg.getValueType() == MVT::i1)
3858 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3859
Roman Divacky71038e72011-08-30 17:04:16 +00003860 seenFloatArg |= VA.getLocVT().isFloatingPoint();
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003861 // Put argument in a physical register.
3862 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3863 } else {
3864 // Put argument in the parameter list area of the current stack frame.
3865 assert(VA.isMemLoc());
3866 unsigned LocMemOffset = VA.getLocMemOffset();
3867
3868 if (!isTailCall) {
3869 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3870 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3871
3872 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
Chris Lattner676c61d2010-09-21 18:41:36 +00003873 MachinePointerInfo(),
David Greene87a5abe2010-02-15 16:56:53 +00003874 false, false, 0));
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003875 } else {
3876 // Calculate and remember argument location.
3877 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3878 TailCallArguments);
3879 }
3880 }
3881 }
Wesley Peck527da1b2010-11-23 03:31:01 +00003882
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003883 if (!MemOpChains.empty())
Craig Topper48d114b2014-04-26 18:35:24 +00003884 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
Wesley Peck527da1b2010-11-23 03:31:01 +00003885
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003886 // Build a sequence of copy-to-reg nodes chained together with token chain
3887 // and flag operands which copy the outgoing args into the appropriate regs.
3888 SDValue InFlag;
3889 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3890 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3891 RegsToPass[i].second, InFlag);
3892 InFlag = Chain.getValue(1);
3893 }
Wesley Peck527da1b2010-11-23 03:31:01 +00003894
Hal Finkel5ab37802012-08-28 02:10:27 +00003895 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3896 // registers.
3897 if (isVarArg) {
NAKAMURA Takumiac490292012-08-30 15:52:29 +00003898 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3899 SDValue Ops[] = { Chain, InFlag };
3900
Hal Finkel5ab37802012-08-28 02:10:27 +00003901 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
Craig Topper2d2aa0c2014-04-30 07:17:30 +00003902 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
NAKAMURA Takumiac490292012-08-30 15:52:29 +00003903
Hal Finkel5ab37802012-08-28 02:10:27 +00003904 InFlag = Chain.getValue(1);
3905 }
3906
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00003907 if (isTailCall)
Tilmann Scheller773f14c2009-07-03 06:47:08 +00003908 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3909 false, TailCallArguments);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003910
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003911 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3912 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3913 Ins, InVals);
Tilmann Schellerb93960d2009-07-03 06:45:56 +00003914}
3915
Bill Schmidt57d6de52012-10-23 15:51:16 +00003916// Copy an argument into memory, being careful to do this outside the
3917// call sequence for the call to which the argument belongs.
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003918SDValue
Bill Schmidt57d6de52012-10-23 15:51:16 +00003919PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3920 SDValue CallSeqStart,
3921 ISD::ArgFlagsTy Flags,
3922 SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003923 SDLoc dl) const {
Bill Schmidt57d6de52012-10-23 15:51:16 +00003924 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3925 CallSeqStart.getNode()->getOperand(0),
3926 Flags, DAG, dl);
3927 // The MEMCPY must go outside the CALLSEQ_START..END.
3928 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
Andrew Trickad6d08a2013-05-29 22:03:55 +00003929 CallSeqStart.getNode()->getOperand(1),
3930 SDLoc(MemcpyCall));
Bill Schmidt57d6de52012-10-23 15:51:16 +00003931 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3932 NewCallSeqStart.getNode());
3933 return NewCallSeqStart;
3934}
3935
3936SDValue
3937PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
Sandeep Patel68c5f472009-09-02 08:44:58 +00003938 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003939 bool isTailCall,
3940 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +00003941 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003942 const SmallVectorImpl<ISD::InputArg> &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +00003943 SDLoc dl, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +00003944 SmallVectorImpl<SDValue> &InVals) const {
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00003945
Ulrich Weigand59c6ab22014-06-20 16:34:05 +00003946 bool isLittleEndian = Subtarget.isLittleEndian();
Bill Schmidt57d6de52012-10-23 15:51:16 +00003947 unsigned NumOps = Outs.size();
Bill Schmidt019cc6f2012-09-19 15:42:13 +00003948
Bill Schmidt57d6de52012-10-23 15:51:16 +00003949 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3950 unsigned PtrByteSize = 8;
3951
3952 MachineFunction &MF = DAG.getMachineFunction();
3953
3954 // Mark this function as potentially containing a function that contains a
3955 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3956 // and restoring the callers stack pointer in this functions epilog. This is
3957 // done because by tail calling the called function might overwrite the value
3958 // in this function's (MF) stack pointer stack slot 0(SP).
3959 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3960 CallConv == CallingConv::Fast)
3961 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3962
Bill Schmidt57d6de52012-10-23 15:51:16 +00003963 // Count how many bytes are to be pushed on the stack, including the linkage
3964 // area, and parameter passing area. We start with at least 48 bytes, which
3965 // is reserved space for [SP][CR][LR][3 x unused].
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00003966 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false);
3967 unsigned NumBytes = LinkageSize;
Ulrich Weigand2bffb952014-06-23 13:08:27 +00003968
3969 // Add up all the space actually used.
3970 for (unsigned i = 0; i != NumOps; ++i) {
3971 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3972 EVT ArgVT = Outs[i].VT;
3973
3974 // Altivec parameters are padded to a 16 byte boundary.
3975 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3976 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3977 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
3978 NumBytes = ((NumBytes+15)/16)*16;
3979
3980 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3981 }
3982
3983 // The prolog code of the callee may store up to 8 GPR argument registers to
3984 // the stack, allowing va_start to index over them in memory if its varargs.
3985 // Because we cannot tell if this is needed on the caller side, we have to
3986 // conservatively assume that it is needed. As such, make sure we have at
3987 // least enough stack space for the caller to store the 8 GPRs.
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00003988 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
Ulrich Weigand2bffb952014-06-23 13:08:27 +00003989
3990 // Tail call needs the stack to be aligned.
3991 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3992 CallConv == CallingConv::Fast)
3993 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
Bill Schmidt57d6de52012-10-23 15:51:16 +00003994
3995 // Calculate by how many bytes the stack has to be adjusted in case of tail
3996 // call optimization.
3997 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3998
3999 // To protect arguments on the stack from being clobbered in a tail call,
4000 // force all the loads to happen before doing any other lowering.
4001 if (isTailCall)
4002 Chain = DAG.getStackArgumentTokenFactor(Chain);
4003
4004 // Adjust the stack pointer for the new arguments...
4005 // These operations are automatically eliminated by the prolog/epilog pass
Andrew Trickad6d08a2013-05-29 22:03:55 +00004006 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4007 dl);
Bill Schmidt57d6de52012-10-23 15:51:16 +00004008 SDValue CallSeqStart = Chain;
4009
4010 // Load the return address and frame pointer so it can be move somewhere else
4011 // later.
4012 SDValue LROp, FPOp;
4013 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4014 dl);
4015
4016 // Set up a copy of the stack pointer for use loading and storing any
4017 // arguments that may not fit in the registers available for argument
4018 // passing.
4019 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4020
4021 // Figure out which arguments are going to go in registers, and which in
4022 // memory. Also, if this is a vararg function, floating point operations
4023 // must be stored to our stack, and loaded into integer regs as well, if
4024 // any integer regs are available for argument passing.
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00004025 unsigned ArgOffset = LinkageSize;
Bill Schmidt57d6de52012-10-23 15:51:16 +00004026 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4027
Craig Topper840beec2014-04-04 05:16:06 +00004028 static const MCPhysReg GPR[] = {
Bill Schmidt57d6de52012-10-23 15:51:16 +00004029 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4030 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4031 };
Craig Topper840beec2014-04-04 05:16:06 +00004032 static const MCPhysReg *FPR = GetFPR();
Bill Schmidt57d6de52012-10-23 15:51:16 +00004033
Craig Topper840beec2014-04-04 05:16:06 +00004034 static const MCPhysReg VR[] = {
Bill Schmidt57d6de52012-10-23 15:51:16 +00004035 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4036 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4037 };
Craig Topper840beec2014-04-04 05:16:06 +00004038 static const MCPhysReg VSRH[] = {
Hal Finkel7811c612014-03-28 19:58:11 +00004039 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4040 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4041 };
4042
Bill Schmidt57d6de52012-10-23 15:51:16 +00004043 const unsigned NumGPRs = array_lengthof(GPR);
4044 const unsigned NumFPRs = 13;
4045 const unsigned NumVRs = array_lengthof(VR);
4046
4047 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4048 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4049
4050 SmallVector<SDValue, 8> MemOpChains;
4051 for (unsigned i = 0; i != NumOps; ++i) {
4052 SDValue Arg = OutVals[i];
4053 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4054
4055 // PtrOff will be used to store the current argument to the stack if a
4056 // register cannot be found for it.
4057 SDValue PtrOff;
4058
4059 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4060
4061 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4062
4063 // Promote integers to 64-bit values.
Hal Finkel940ab932014-02-28 00:27:01 +00004064 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
Bill Schmidt57d6de52012-10-23 15:51:16 +00004065 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4066 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4067 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4068 }
4069
4070 // FIXME memcpy is used way more than necessary. Correctness first.
4071 // Note: "by value" is code for passing a structure by value, not
4072 // basic types.
4073 if (Flags.isByVal()) {
4074 // Note: Size includes alignment padding, so
4075 // struct x { short a; char b; }
4076 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4077 // These are the proper values we need for right-justifying the
4078 // aggregate in a parameter register.
4079 unsigned Size = Flags.getByValSize();
Bill Schmidt9953cf22012-10-31 01:15:05 +00004080
4081 // An empty aggregate parameter takes up no storage and no
4082 // registers.
4083 if (Size == 0)
4084 continue;
4085
Hal Finkel262a2242013-09-12 23:20:06 +00004086 unsigned BVAlign = Flags.getByValAlign();
4087 if (BVAlign > 8) {
4088 if (BVAlign % PtrByteSize != 0)
4089 llvm_unreachable(
4090 "ByVal alignment is not a multiple of the pointer size");
4091
4092 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
4093 }
4094
Bill Schmidt57d6de52012-10-23 15:51:16 +00004095 // All aggregates smaller than 8 bytes must be passed right-justified.
4096 if (Size==1 || Size==2 || Size==4) {
4097 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4098 if (GPR_idx != NumGPRs) {
4099 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4100 MachinePointerInfo(), VT,
4101 false, false, 0);
4102 MemOpChains.push_back(Load.getValue(1));
4103 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4104
4105 ArgOffset += PtrByteSize;
4106 continue;
4107 }
4108 }
4109
4110 if (GPR_idx == NumGPRs && Size < 8) {
Ulrich Weigand59c6ab22014-06-20 16:34:05 +00004111 SDValue AddPtr = PtrOff;
4112 if (!isLittleEndian) {
4113 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4114 PtrOff.getValueType());
4115 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4116 }
Bill Schmidt57d6de52012-10-23 15:51:16 +00004117 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4118 CallSeqStart,
4119 Flags, DAG, dl);
4120 ArgOffset += PtrByteSize;
4121 continue;
4122 }
4123 // Copy entire object into memory. There are cases where gcc-generated
4124 // code assumes it is there, even if it could be put entirely into
4125 // registers. (This is not what the doc says.)
4126
4127 // FIXME: The above statement is likely due to a misunderstanding of the
4128 // documents. All arguments must be copied into the parameter area BY
4129 // THE CALLEE in the event that the callee takes the address of any
4130 // formal argument. That has not yet been implemented. However, it is
4131 // reasonable to use the stack area as a staging area for the register
4132 // load.
4133
4134 // Skip this for small aggregates, as we will use the same slot for a
4135 // right-justified copy, below.
4136 if (Size >= 8)
4137 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4138 CallSeqStart,
4139 Flags, DAG, dl);
4140
4141 // When a register is available, pass a small aggregate right-justified.
4142 if (Size < 8 && GPR_idx != NumGPRs) {
4143 // The easiest way to get this right-justified in a register
4144 // is to copy the structure into the rightmost portion of a
4145 // local variable slot, then load the whole slot into the
4146 // register.
4147 // FIXME: The memcpy seems to produce pretty awful code for
4148 // small aggregates, particularly for packed ones.
Matt Arsenault758659232013-05-18 00:21:46 +00004149 // FIXME: It would be preferable to use the slot in the
Bill Schmidt57d6de52012-10-23 15:51:16 +00004150 // parameter save area instead of a new local variable.
Ulrich Weigand59c6ab22014-06-20 16:34:05 +00004151 SDValue AddPtr = PtrOff;
4152 if (!isLittleEndian) {
4153 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4154 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4155 }
Bill Schmidt57d6de52012-10-23 15:51:16 +00004156 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4157 CallSeqStart,
4158 Flags, DAG, dl);
4159
4160 // Load the slot into the register.
4161 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4162 MachinePointerInfo(),
4163 false, false, false, 0);
4164 MemOpChains.push_back(Load.getValue(1));
4165 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4166
4167 // Done with this argument.
4168 ArgOffset += PtrByteSize;
4169 continue;
4170 }
4171
4172 // For aggregates larger than PtrByteSize, copy the pieces of the
4173 // object that fit into registers from the parameter save area.
4174 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4175 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4176 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4177 if (GPR_idx != NumGPRs) {
4178 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4179 MachinePointerInfo(),
4180 false, false, false, 0);
4181 MemOpChains.push_back(Load.getValue(1));
4182 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4183 ArgOffset += PtrByteSize;
4184 } else {
4185 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4186 break;
4187 }
4188 }
4189 continue;
4190 }
4191
Craig Topper56710102013-08-15 02:33:50 +00004192 switch (Arg.getSimpleValueType().SimpleTy) {
Bill Schmidt57d6de52012-10-23 15:51:16 +00004193 default: llvm_unreachable("Unexpected ValueType for argument!");
Hal Finkel940ab932014-02-28 00:27:01 +00004194 case MVT::i1:
Bill Schmidt57d6de52012-10-23 15:51:16 +00004195 case MVT::i32:
4196 case MVT::i64:
4197 if (GPR_idx != NumGPRs) {
4198 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4199 } else {
4200 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4201 true, isTailCall, false, MemOpChains,
4202 TailCallArguments, dl);
4203 }
4204 ArgOffset += PtrByteSize;
4205 break;
4206 case MVT::f32:
4207 case MVT::f64:
4208 if (FPR_idx != NumFPRs) {
4209 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4210
4211 if (isVarArg) {
Bill Schmidtbd4ac262012-10-29 21:18:16 +00004212 // A single float or an aggregate containing only a single float
4213 // must be passed right-justified in the stack doubleword, and
4214 // in the GPR, if one is available.
4215 SDValue StoreOff;
Ulrich Weigand59c6ab22014-06-20 16:34:05 +00004216 if (Arg.getSimpleValueType().SimpleTy == MVT::f32 &&
4217 !isLittleEndian) {
Bill Schmidtbd4ac262012-10-29 21:18:16 +00004218 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4219 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4220 } else
4221 StoreOff = PtrOff;
4222
4223 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
Bill Schmidt57d6de52012-10-23 15:51:16 +00004224 MachinePointerInfo(), false, false, 0);
4225 MemOpChains.push_back(Store);
4226
4227 // Float varargs are always shadowed in available integer registers
4228 if (GPR_idx != NumGPRs) {
4229 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4230 MachinePointerInfo(), false, false,
4231 false, 0);
4232 MemOpChains.push_back(Load.getValue(1));
4233 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4234 }
4235 } else if (GPR_idx != NumGPRs)
4236 // If we have any FPRs remaining, we may also have GPRs remaining.
4237 ++GPR_idx;
4238 } else {
4239 // Single-precision floating-point values are mapped to the
4240 // second (rightmost) word of the stack doubleword.
Ulrich Weigand59c6ab22014-06-20 16:34:05 +00004241 if (Arg.getValueType() == MVT::f32 && !isLittleEndian) {
Bill Schmidt57d6de52012-10-23 15:51:16 +00004242 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4243 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4244 }
4245
4246 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4247 true, isTailCall, false, MemOpChains,
4248 TailCallArguments, dl);
4249 }
4250 ArgOffset += 8;
4251 break;
4252 case MVT::v4f32:
4253 case MVT::v4i32:
4254 case MVT::v8i16:
4255 case MVT::v16i8:
Hal Finkel27774d92014-03-13 07:58:58 +00004256 case MVT::v2f64:
Hal Finkela6c8b512014-03-26 16:12:58 +00004257 case MVT::v2i64:
Ulrich Weigand9ba552d2014-06-23 12:36:34 +00004258 // Vectors are aligned to a 16-byte boundary in the argument save area.
4259 while (ArgOffset % 16 !=0) {
4260 ArgOffset += PtrByteSize;
4261 if (GPR_idx != NumGPRs)
4262 GPR_idx++;
4263 }
4264
4265 // For a varargs call, named arguments go into VRs or on the stack as
4266 // usual; unnamed arguments always go to the stack or the corresponding
4267 // GPRs when within range. For now, we always put the value in both
4268 // locations (or even all three).
Bill Schmidt57d6de52012-10-23 15:51:16 +00004269 if (isVarArg) {
Bill Schmidt57d6de52012-10-23 15:51:16 +00004270 // We could elide this store in the case where the object fits
4271 // entirely in R registers. Maybe later.
4272 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4273 DAG.getConstant(ArgOffset, PtrVT));
4274 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4275 MachinePointerInfo(), false, false, 0);
4276 MemOpChains.push_back(Store);
4277 if (VR_idx != NumVRs) {
4278 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4279 MachinePointerInfo(),
4280 false, false, false, 0);
4281 MemOpChains.push_back(Load.getValue(1));
Hal Finkel7811c612014-03-28 19:58:11 +00004282
4283 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4284 Arg.getSimpleValueType() == MVT::v2i64) ?
4285 VSRH[VR_idx] : VR[VR_idx];
4286 ++VR_idx;
4287
4288 RegsToPass.push_back(std::make_pair(VReg, Load));
Bill Schmidt57d6de52012-10-23 15:51:16 +00004289 }
4290 ArgOffset += 16;
4291 for (unsigned i=0; i<16; i+=PtrByteSize) {
4292 if (GPR_idx == NumGPRs)
4293 break;
4294 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4295 DAG.getConstant(i, PtrVT));
4296 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4297 false, false, false, 0);
4298 MemOpChains.push_back(Load.getValue(1));
4299 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4300 }
4301 break;
4302 }
4303
Ulrich Weigand9ba552d2014-06-23 12:36:34 +00004304 // Non-varargs Altivec params go into VRs or on the stack.
Bill Schmidt57d6de52012-10-23 15:51:16 +00004305 if (VR_idx != NumVRs) {
Hal Finkel7811c612014-03-28 19:58:11 +00004306 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4307 Arg.getSimpleValueType() == MVT::v2i64) ?
4308 VSRH[VR_idx] : VR[VR_idx];
4309 ++VR_idx;
4310
4311 RegsToPass.push_back(std::make_pair(VReg, Arg));
Bill Schmidt57d6de52012-10-23 15:51:16 +00004312 } else {
4313 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4314 true, isTailCall, true, MemOpChains,
4315 TailCallArguments, dl);
Bill Schmidt57d6de52012-10-23 15:51:16 +00004316 }
Ulrich Weigand9ba552d2014-06-23 12:36:34 +00004317 ArgOffset += 16;
4318 GPR_idx = std::min(GPR_idx + 2, NumGPRs);
Bill Schmidt57d6de52012-10-23 15:51:16 +00004319 break;
4320 }
4321 }
4322
4323 if (!MemOpChains.empty())
Craig Topper48d114b2014-04-26 18:35:24 +00004324 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
Bill Schmidt57d6de52012-10-23 15:51:16 +00004325
4326 // Check if this is an indirect call (MTCTR/BCTRL).
4327 // See PrepareCall() for more information about calls through function
4328 // pointers in the 64-bit SVR4 ABI.
4329 if (!isTailCall &&
4330 !dyn_cast<GlobalAddressSDNode>(Callee) &&
Ulrich Weigand9aa09ef2014-06-18 16:14:04 +00004331 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
Bill Schmidt57d6de52012-10-23 15:51:16 +00004332 // Load r2 into a virtual register and store it to the TOC save area.
4333 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4334 // TOC save area offset.
Ulrich Weigandad0cb912014-06-18 17:52:49 +00004335 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
4336 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
Bill Schmidt57d6de52012-10-23 15:51:16 +00004337 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4338 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4339 false, false, 0);
Bill Schmidt57d6de52012-10-23 15:51:16 +00004340 }
4341
4342 // Build a sequence of copy-to-reg nodes chained together with token chain
4343 // and flag operands which copy the outgoing args into the appropriate regs.
4344 SDValue InFlag;
4345 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4346 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4347 RegsToPass[i].second, InFlag);
4348 InFlag = Chain.getValue(1);
4349 }
4350
4351 if (isTailCall)
4352 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4353 FPOp, true, TailCallArguments);
4354
4355 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4356 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4357 Ins, InVals);
4358}
4359
4360SDValue
4361PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4362 CallingConv::ID CallConv, bool isVarArg,
4363 bool isTailCall,
4364 const SmallVectorImpl<ISD::OutputArg> &Outs,
4365 const SmallVectorImpl<SDValue> &OutVals,
4366 const SmallVectorImpl<ISD::InputArg> &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +00004367 SDLoc dl, SelectionDAG &DAG,
Bill Schmidt57d6de52012-10-23 15:51:16 +00004368 SmallVectorImpl<SDValue> &InVals) const {
4369
4370 unsigned NumOps = Outs.size();
Scott Michelcf0da6c2009-02-17 22:15:04 +00004371
Owen Anderson53aa7a92009-08-10 22:56:29 +00004372 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Owen Anderson9f944592009-08-11 20:47:22 +00004373 bool isPPC64 = PtrVT == MVT::i64;
Chris Lattnerec78cad2006-06-26 22:48:35 +00004374 unsigned PtrByteSize = isPPC64 ? 8 : 4;
Scott Michelcf0da6c2009-02-17 22:15:04 +00004375
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004376 MachineFunction &MF = DAG.getMachineFunction();
4377
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004378 // Mark this function as potentially containing a function that contains a
4379 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4380 // and restoring the callers stack pointer in this functions epilog. This is
4381 // done because by tail calling the called function might overwrite the value
4382 // in this function's (MF) stack pointer stack slot 0(SP).
Nick Lewycky50f02cb2011-12-02 22:16:29 +00004383 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4384 CallConv == CallingConv::Fast)
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004385 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4386
Chris Lattneraa40ec12006-05-16 22:56:08 +00004387 // Count how many bytes are to be pushed on the stack, including the linkage
Chris Lattnerec78cad2006-06-26 22:48:35 +00004388 // area, and parameter passing area. We start with 24/48 bytes, which is
Chris Lattnerb7552a82006-05-17 00:15:40 +00004389 // prereserved space for [SP][CR][LR][3 x unused].
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00004390 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true);
4391 unsigned NumBytes = LinkageSize;
Ulrich Weigand2bffb952014-06-23 13:08:27 +00004392
4393 // Add up all the space actually used.
4394 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4395 // they all go in registers, but we must reserve stack space for them for
4396 // possible use by the caller. In varargs or 64-bit calls, parameters are
4397 // assigned stack space in order, with padding so Altivec parameters are
4398 // 16-byte aligned.
4399 unsigned nAltivecParamsAtEnd = 0;
4400 for (unsigned i = 0; i != NumOps; ++i) {
4401 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4402 EVT ArgVT = Outs[i].VT;
4403 // Varargs Altivec parameters are padded to a 16 byte boundary.
4404 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4405 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4406 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4407 if (!isVarArg && !isPPC64) {
4408 // Non-varargs Altivec parameters go after all the non-Altivec
4409 // parameters; handle those later so we know how much padding we need.
4410 nAltivecParamsAtEnd++;
4411 continue;
4412 }
4413 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4414 NumBytes = ((NumBytes+15)/16)*16;
4415 }
4416 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4417 }
4418
4419 // Allow for Altivec parameters at the end, if needed.
4420 if (nAltivecParamsAtEnd) {
4421 NumBytes = ((NumBytes+15)/16)*16;
4422 NumBytes += 16*nAltivecParamsAtEnd;
4423 }
4424
4425 // The prolog code of the callee may store up to 8 GPR argument registers to
4426 // the stack, allowing va_start to index over them in memory if its varargs.
4427 // Because we cannot tell if this is needed on the caller side, we have to
4428 // conservatively assume that it is needed. As such, make sure we have at
4429 // least enough stack space for the caller to store the 8 GPRs.
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00004430 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
Ulrich Weigand2bffb952014-06-23 13:08:27 +00004431
4432 // Tail call needs the stack to be aligned.
4433 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4434 CallConv == CallingConv::Fast)
4435 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
Dale Johannesenb28456e2008-03-12 00:22:17 +00004436
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004437 // Calculate by how many bytes the stack has to be adjusted in case of tail
4438 // call optimization.
4439 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004440
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00004441 // To protect arguments on the stack from being clobbered in a tail call,
4442 // force all the loads to happen before doing any other lowering.
4443 if (isTailCall)
4444 Chain = DAG.getStackArgumentTokenFactor(Chain);
4445
Chris Lattnerb7552a82006-05-17 00:15:40 +00004446 // Adjust the stack pointer for the new arguments...
4447 // These operations are automatically eliminated by the prolog/epilog pass
Andrew Trickad6d08a2013-05-29 22:03:55 +00004448 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4449 dl);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004450 SDValue CallSeqStart = Chain;
Scott Michelcf0da6c2009-02-17 22:15:04 +00004451
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004452 // Load the return address and frame pointer so it can be move somewhere else
4453 // later.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004454 SDValue LROp, FPOp;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00004455 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4456 dl);
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004457
Chris Lattnerb7552a82006-05-17 00:15:40 +00004458 // Set up a copy of the stack pointer for use loading and storing any
4459 // arguments that may not fit in the registers available for argument
4460 // passing.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004461 SDValue StackPtr;
Chris Lattnerec78cad2006-06-26 22:48:35 +00004462 if (isPPC64)
Owen Anderson9f944592009-08-11 20:47:22 +00004463 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
Chris Lattnerec78cad2006-06-26 22:48:35 +00004464 else
Owen Anderson9f944592009-08-11 20:47:22 +00004465 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004466
Chris Lattnerb7552a82006-05-17 00:15:40 +00004467 // Figure out which arguments are going to go in registers, and which in
4468 // memory. Also, if this is a vararg function, floating point operations
4469 // must be stored to our stack, and loaded into integer regs as well, if
4470 // any integer regs are available for argument passing.
Ulrich Weigand8ca988f2014-06-23 14:15:53 +00004471 unsigned ArgOffset = LinkageSize;
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004472 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
Scott Michelcf0da6c2009-02-17 22:15:04 +00004473
Craig Topper840beec2014-04-04 05:16:06 +00004474 static const MCPhysReg GPR_32[] = { // 32-bit registers.
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004475 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4476 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4477 };
Craig Topper840beec2014-04-04 05:16:06 +00004478 static const MCPhysReg GPR_64[] = { // 64-bit registers.
Chris Lattnerec78cad2006-06-26 22:48:35 +00004479 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4480 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4481 };
Craig Topper840beec2014-04-04 05:16:06 +00004482 static const MCPhysReg *FPR = GetFPR();
Scott Michelcf0da6c2009-02-17 22:15:04 +00004483
Craig Topper840beec2014-04-04 05:16:06 +00004484 static const MCPhysReg VR[] = {
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004485 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4486 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4487 };
Owen Andersone2f23a32007-09-07 04:06:50 +00004488 const unsigned NumGPRs = array_lengthof(GPR_32);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004489 const unsigned NumFPRs = 13;
Tilmann Scheller98bdaaa2009-07-03 06:43:35 +00004490 const unsigned NumVRs = array_lengthof(VR);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004491
Craig Topper840beec2014-04-04 05:16:06 +00004492 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
Chris Lattnerec78cad2006-06-26 22:48:35 +00004493
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004494 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004495 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4496
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004497 SmallVector<SDValue, 8> MemOpChains;
Evan Chengc2cd4732006-05-25 00:57:32 +00004498 for (unsigned i = 0; i != NumOps; ++i) {
Dan Gohmanfe7532a2010-07-07 15:54:55 +00004499 SDValue Arg = OutVals[i];
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00004500 ISD::ArgFlagsTy Flags = Outs[i].Flags;
Nicolas Geoffray7aad9282007-03-13 15:02:46 +00004501
Chris Lattnerb7552a82006-05-17 00:15:40 +00004502 // PtrOff will be used to store the current argument to the stack if a
4503 // register cannot be found for it.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004504 SDValue PtrOff;
Scott Michelcf0da6c2009-02-17 22:15:04 +00004505
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004506 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
Nicolas Geoffray7aad9282007-03-13 15:02:46 +00004507
Dale Johannesen679073b2009-02-04 02:34:38 +00004508 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
Chris Lattnerec78cad2006-06-26 22:48:35 +00004509
4510 // On PPC64, promote integers to 64-bit values.
Owen Anderson9f944592009-08-11 20:47:22 +00004511 if (isPPC64 && Arg.getValueType() == MVT::i32) {
Duncan Sandsd97eea32008-03-21 09:14:45 +00004512 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4513 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
Owen Anderson9f944592009-08-11 20:47:22 +00004514 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
Chris Lattnerec78cad2006-06-26 22:48:35 +00004515 }
Dale Johannesen85d41a12008-03-04 23:17:14 +00004516
Dale Johannesenbfa252d2008-03-07 20:27:40 +00004517 // FIXME memcpy is used way more than necessary. Correctness first.
Bill Schmidt019cc6f2012-09-19 15:42:13 +00004518 // Note: "by value" is code for passing a structure by value, not
4519 // basic types.
Duncan Sandsd97eea32008-03-21 09:14:45 +00004520 if (Flags.isByVal()) {
4521 unsigned Size = Flags.getByValSize();
Bill Schmidt57d6de52012-10-23 15:51:16 +00004522 // Very small objects are passed right-justified. Everything else is
4523 // passed left-justified.
4524 if (Size==1 || Size==2) {
4525 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
Dale Johannesenbfa252d2008-03-07 20:27:40 +00004526 if (GPR_idx != NumGPRs) {
Stuart Hastings81c43062011-02-16 16:23:55 +00004527 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
Chris Lattner3d178ed2010-09-21 17:04:51 +00004528 MachinePointerInfo(), VT,
4529 false, false, 0);
Dale Johannesenbfa252d2008-03-07 20:27:40 +00004530 MemOpChains.push_back(Load.getValue(1));
4531 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004532
4533 ArgOffset += PtrByteSize;
Dale Johannesenbfa252d2008-03-07 20:27:40 +00004534 } else {
Bill Schmidt48081ca2012-10-16 13:30:53 +00004535 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4536 PtrOff.getValueType());
Dale Johannesen679073b2009-02-04 02:34:38 +00004537 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
Bill Schmidt57d6de52012-10-23 15:51:16 +00004538 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4539 CallSeqStart,
4540 Flags, DAG, dl);
Dale Johannesenbfa252d2008-03-07 20:27:40 +00004541 ArgOffset += PtrByteSize;
4542 }
4543 continue;
4544 }
Dale Johannesen92dcf1e2008-03-17 02:13:43 +00004545 // Copy entire object into memory. There are cases where gcc-generated
4546 // code assumes it is there, even if it could be put entirely into
4547 // registers. (This is not what the doc says.)
Bill Schmidt57d6de52012-10-23 15:51:16 +00004548 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4549 CallSeqStart,
4550 Flags, DAG, dl);
Bill Schmidt019cc6f2012-09-19 15:42:13 +00004551
4552 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4553 // copy the pieces of the object that fit into registers from the
4554 // parameter save area.
Dale Johannesen85d41a12008-03-04 23:17:14 +00004555 for (unsigned j=0; j<Size; j+=PtrByteSize) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004556 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
Dale Johannesen679073b2009-02-04 02:34:38 +00004557 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
Dale Johannesen85d41a12008-03-04 23:17:14 +00004558 if (GPR_idx != NumGPRs) {
Chris Lattner7727d052010-09-21 06:44:06 +00004559 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4560 MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00004561 false, false, false, 0);
Dale Johannesen0d235052008-03-05 23:31:27 +00004562 MemOpChains.push_back(Load.getValue(1));
Dale Johannesen85d41a12008-03-04 23:17:14 +00004563 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004564 ArgOffset += PtrByteSize;
Dale Johannesen85d41a12008-03-04 23:17:14 +00004565 } else {
Dale Johannesen92dcf1e2008-03-17 02:13:43 +00004566 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
Dale Johannesenbfa252d2008-03-07 20:27:40 +00004567 break;
Dale Johannesen85d41a12008-03-04 23:17:14 +00004568 }
4569 }
4570 continue;
4571 }
4572
Craig Topper56710102013-08-15 02:33:50 +00004573 switch (Arg.getSimpleValueType().SimpleTy) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00004574 default: llvm_unreachable("Unexpected ValueType for argument!");
Hal Finkel5cae2162014-02-28 01:17:25 +00004575 case MVT::i1:
Owen Anderson9f944592009-08-11 20:47:22 +00004576 case MVT::i32:
4577 case MVT::i64:
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004578 if (GPR_idx != NumGPRs) {
Hal Finkel7f908e82014-03-06 00:45:19 +00004579 if (Arg.getValueType() == MVT::i1)
4580 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4581
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004582 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
Chris Lattnerb7552a82006-05-17 00:15:40 +00004583 } else {
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004584 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4585 isPPC64, isTailCall, false, MemOpChains,
Dale Johannesen021052a2009-02-04 20:06:27 +00004586 TailCallArguments, dl);
Chris Lattnerb7552a82006-05-17 00:15:40 +00004587 }
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004588 ArgOffset += PtrByteSize;
Chris Lattnerb7552a82006-05-17 00:15:40 +00004589 break;
Owen Anderson9f944592009-08-11 20:47:22 +00004590 case MVT::f32:
4591 case MVT::f64:
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004592 if (FPR_idx != NumFPRs) {
4593 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4594
Chris Lattnerb7552a82006-05-17 00:15:40 +00004595 if (isVarArg) {
Chris Lattner676c61d2010-09-21 18:41:36 +00004596 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4597 MachinePointerInfo(), false, false, 0);
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004598 MemOpChains.push_back(Store);
4599
Chris Lattnerb7552a82006-05-17 00:15:40 +00004600 // Float varargs are always shadowed in available integer registers
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004601 if (GPR_idx != NumGPRs) {
Chris Lattner7727d052010-09-21 06:44:06 +00004602 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
Pete Cooper82cd9e82011-11-08 18:42:53 +00004603 MachinePointerInfo(), false, false,
4604 false, 0);
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004605 MemOpChains.push_back(Load.getValue(1));
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004606 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
Chris Lattnerb7552a82006-05-17 00:15:40 +00004607 }
Owen Anderson9f944592009-08-11 20:47:22 +00004608 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004609 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
Dale Johannesen679073b2009-02-04 02:34:38 +00004610 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
Chris Lattner7727d052010-09-21 06:44:06 +00004611 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4612 MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00004613 false, false, false, 0);
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004614 MemOpChains.push_back(Load.getValue(1));
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004615 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
Chris Lattneraa40ec12006-05-16 22:56:08 +00004616 }
4617 } else {
Chris Lattnerb7552a82006-05-17 00:15:40 +00004618 // If we have any FPRs remaining, we may also have GPRs remaining.
4619 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4620 // GPRs.
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004621 if (GPR_idx != NumGPRs)
4622 ++GPR_idx;
Owen Anderson9f944592009-08-11 20:47:22 +00004623 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004624 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4625 ++GPR_idx;
Chris Lattneraa40ec12006-05-16 22:56:08 +00004626 }
Bill Schmidt57d6de52012-10-23 15:51:16 +00004627 } else
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004628 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4629 isPPC64, isTailCall, false, MemOpChains,
Dale Johannesen021052a2009-02-04 20:06:27 +00004630 TailCallArguments, dl);
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004631 if (isPPC64)
4632 ArgOffset += 8;
4633 else
Owen Anderson9f944592009-08-11 20:47:22 +00004634 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
Chris Lattnerb7552a82006-05-17 00:15:40 +00004635 break;
Owen Anderson9f944592009-08-11 20:47:22 +00004636 case MVT::v4f32:
4637 case MVT::v4i32:
4638 case MVT::v8i16:
4639 case MVT::v16i8:
Dale Johannesenb28456e2008-03-12 00:22:17 +00004640 if (isVarArg) {
4641 // These go aligned on the stack, or in the corresponding R registers
Scott Michelcf0da6c2009-02-17 22:15:04 +00004642 // when within range. The Darwin PPC ABI doc claims they also go in
Dale Johannesenb28456e2008-03-12 00:22:17 +00004643 // V registers; in fact gcc does this only for arguments that are
4644 // prototyped, not for those that match the ... We do it for all
4645 // arguments, seems to work.
4646 while (ArgOffset % 16 !=0) {
4647 ArgOffset += PtrByteSize;
4648 if (GPR_idx != NumGPRs)
4649 GPR_idx++;
4650 }
4651 // We could elide this store in the case where the object fits
4652 // entirely in R registers. Maybe later.
Scott Michelcf0da6c2009-02-17 22:15:04 +00004653 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
Dale Johannesenb28456e2008-03-12 00:22:17 +00004654 DAG.getConstant(ArgOffset, PtrVT));
Chris Lattner676c61d2010-09-21 18:41:36 +00004655 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4656 MachinePointerInfo(), false, false, 0);
Dale Johannesenb28456e2008-03-12 00:22:17 +00004657 MemOpChains.push_back(Store);
4658 if (VR_idx != NumVRs) {
Wesley Peck527da1b2010-11-23 03:31:01 +00004659 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
Chris Lattner7727d052010-09-21 06:44:06 +00004660 MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00004661 false, false, false, 0);
Dale Johannesenb28456e2008-03-12 00:22:17 +00004662 MemOpChains.push_back(Load.getValue(1));
4663 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4664 }
4665 ArgOffset += 16;
4666 for (unsigned i=0; i<16; i+=PtrByteSize) {
4667 if (GPR_idx == NumGPRs)
4668 break;
Dale Johannesen679073b2009-02-04 02:34:38 +00004669 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
Dale Johannesenb28456e2008-03-12 00:22:17 +00004670 DAG.getConstant(i, PtrVT));
Chris Lattner7727d052010-09-21 06:44:06 +00004671 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00004672 false, false, false, 0);
Dale Johannesenb28456e2008-03-12 00:22:17 +00004673 MemOpChains.push_back(Load.getValue(1));
4674 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4675 }
4676 break;
4677 }
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004678
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00004679 // Non-varargs Altivec params generally go in registers, but have
4680 // stack space allocated at the end.
4681 if (VR_idx != NumVRs) {
4682 // Doesn't have GPR space allocated.
4683 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4684 } else if (nAltivecParamsAtEnd==0) {
4685 // We are emitting Altivec params in order.
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004686 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4687 isPPC64, isTailCall, true, MemOpChains,
Dale Johannesen021052a2009-02-04 20:06:27 +00004688 TailCallArguments, dl);
Dale Johannesenb28456e2008-03-12 00:22:17 +00004689 ArgOffset += 16;
Dale Johannesenb28456e2008-03-12 00:22:17 +00004690 }
Chris Lattnerb7552a82006-05-17 00:15:40 +00004691 break;
Chris Lattneraa40ec12006-05-16 22:56:08 +00004692 }
Chris Lattneraa40ec12006-05-16 22:56:08 +00004693 }
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00004694 // If all Altivec parameters fit in registers, as they usually do,
4695 // they get stack space following the non-Altivec parameters. We
4696 // don't track this here because nobody below needs it.
4697 // If there are more Altivec parameters than fit in registers emit
4698 // the stores here.
4699 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4700 unsigned j = 0;
4701 // Offset is aligned; skip 1st 12 params which go in V registers.
4702 ArgOffset = ((ArgOffset+15)/16)*16;
4703 ArgOffset += 12*16;
4704 for (unsigned i = 0; i != NumOps; ++i) {
Dan Gohmanfe7532a2010-07-07 15:54:55 +00004705 SDValue Arg = OutVals[i];
4706 EVT ArgType = Outs[i].VT;
Owen Anderson9f944592009-08-11 20:47:22 +00004707 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4708 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00004709 if (++j > NumVRs) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004710 SDValue PtrOff;
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004711 // We are emitting Altivec params in order.
4712 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4713 isPPC64, isTailCall, true, MemOpChains,
Dale Johannesen021052a2009-02-04 20:06:27 +00004714 TailCallArguments, dl);
Dale Johannesen0dfd3f32008-03-14 17:41:26 +00004715 ArgOffset += 16;
4716 }
4717 }
4718 }
4719 }
4720
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004721 if (!MemOpChains.empty())
Craig Topper48d114b2014-04-26 18:35:24 +00004722 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004723
Dale Johannesen90eab672010-03-09 20:15:42 +00004724 // On Darwin, R12 must contain the address of an indirect callee. This does
4725 // not mean the MTCTR instruction must use R12; it's easier to model this as
4726 // an extra parameter, so do that.
Wesley Peck527da1b2010-11-23 03:31:01 +00004727 if (!isTailCall &&
Dale Johannesen90eab672010-03-09 20:15:42 +00004728 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4729 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4730 !isBLACompatibleAddress(Callee, DAG))
4731 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4732 PPC::R12), Callee));
4733
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004734 // Build a sequence of copy-to-reg nodes chained together with token chain
4735 // and flag operands which copy the outgoing args into the appropriate regs.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004736 SDValue InFlag;
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004737 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Scott Michelcf0da6c2009-02-17 22:15:04 +00004738 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
Dale Johannesen679073b2009-02-04 02:34:38 +00004739 RegsToPass[i].second, InFlag);
Chris Lattnerb1e9e372006-05-17 06:01:33 +00004740 InFlag = Chain.getValue(1);
4741 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00004742
Chris Lattnerdf8e17d2010-11-14 23:42:06 +00004743 if (isTailCall)
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004744 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4745 FPOp, true, TailCallArguments);
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004746
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00004747 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4748 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4749 Ins, InVals);
Chris Lattneraa40ec12006-05-16 22:56:08 +00004750}
4751
Hal Finkel450128a2011-10-14 19:51:36 +00004752bool
4753PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4754 MachineFunction &MF, bool isVarArg,
4755 const SmallVectorImpl<ISD::OutputArg> &Outs,
4756 LLVMContext &Context) const {
4757 SmallVector<CCValAssign, 16> RVLocs;
4758 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4759 RVLocs, Context);
4760 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4761}
4762
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00004763SDValue
4764PPCTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +00004765 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00004766 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +00004767 const SmallVectorImpl<SDValue> &OutVals,
Andrew Trickef9de2a2013-05-25 02:42:55 +00004768 SDLoc dl, SelectionDAG &DAG) const {
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00004769
Chris Lattner4f2e4e02007-03-06 00:59:59 +00004770 SmallVector<CCValAssign, 16> RVLocs;
Eric Christopher0713a9d2011-06-08 23:55:35 +00004771 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Gabor Greif180c4442012-04-19 15:16:31 +00004772 getTargetMachine(), RVLocs, *DAG.getContext());
Dan Gohmanf9bbcd12009-08-05 01:29:28 +00004773 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004774
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004775 SDValue Flag;
Jakob Stoklund Olesen8660a8c2013-02-05 18:12:00 +00004776 SmallVector<SDValue, 4> RetOps(1, Chain);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004777
Chris Lattner4f2e4e02007-03-06 00:59:59 +00004778 // Copy the result values into the output registers.
4779 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4780 CCValAssign &VA = RVLocs[i];
4781 assert(VA.isRegLoc() && "Can only return in registers!");
Ulrich Weigand339d0592012-11-05 19:39:45 +00004782
4783 SDValue Arg = OutVals[i];
4784
4785 switch (VA.getLocInfo()) {
4786 default: llvm_unreachable("Unknown loc info!");
4787 case CCValAssign::Full: break;
4788 case CCValAssign::AExt:
4789 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4790 break;
4791 case CCValAssign::ZExt:
4792 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4793 break;
4794 case CCValAssign::SExt:
4795 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4796 break;
4797 }
4798
4799 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
Chris Lattner4f2e4e02007-03-06 00:59:59 +00004800 Flag = Chain.getValue(1);
Jakob Stoklund Olesen8660a8c2013-02-05 18:12:00 +00004801 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
Chris Lattner4f2e4e02007-03-06 00:59:59 +00004802 }
4803
Jakob Stoklund Olesen8660a8c2013-02-05 18:12:00 +00004804 RetOps[0] = Chain; // Update chain.
4805
4806 // Add the flag if we have it.
Gabor Greiff304a7a2008-08-28 21:40:38 +00004807 if (Flag.getNode())
Jakob Stoklund Olesen8660a8c2013-02-05 18:12:00 +00004808 RetOps.push_back(Flag);
4809
Craig Topper48d114b2014-04-26 18:35:24 +00004810 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
Chris Lattner4211ca92006-04-14 06:01:58 +00004811}
4812
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004813SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +00004814 const PPCSubtarget &Subtarget) const {
Jim Laskeye4f4d042006-12-04 22:04:42 +00004815 // When we pop the dynamic allocation we need to restore the SP link.
Andrew Trickef9de2a2013-05-25 02:42:55 +00004816 SDLoc dl(Op);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004817
Jim Laskeye4f4d042006-12-04 22:04:42 +00004818 // Get the corect type for pointers.
Owen Anderson53aa7a92009-08-10 22:56:29 +00004819 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Jim Laskeye4f4d042006-12-04 22:04:42 +00004820
4821 // Construct the stack pointer operand.
Dale Johannesen86dcae12009-11-24 01:09:07 +00004822 bool isPPC64 = Subtarget.isPPC64();
4823 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004824 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
Jim Laskeye4f4d042006-12-04 22:04:42 +00004825
4826 // Get the operands for the STACKRESTORE.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004827 SDValue Chain = Op.getOperand(0);
4828 SDValue SaveSP = Op.getOperand(1);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004829
Jim Laskeye4f4d042006-12-04 22:04:42 +00004830 // Load the old link SP.
Chris Lattner7727d052010-09-21 06:44:06 +00004831 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4832 MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00004833 false, false, false, 0);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004834
Jim Laskeye4f4d042006-12-04 22:04:42 +00004835 // Restore the stack pointer.
Dale Johannesen021052a2009-02-04 20:06:27 +00004836 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004837
Jim Laskeye4f4d042006-12-04 22:04:42 +00004838 // Store the old link SP.
Chris Lattner676c61d2010-09-21 18:41:36 +00004839 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
David Greene87a5abe2010-02-15 16:56:53 +00004840 false, false, 0);
Jim Laskeye4f4d042006-12-04 22:04:42 +00004841}
4842
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004843
4844
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004845SDValue
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004846PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
Jim Laskey48850c12006-11-16 22:43:37 +00004847 MachineFunction &MF = DAG.getMachineFunction();
Eric Christopherb1aaebe2014-06-12 22:38:18 +00004848 bool isPPC64 = Subtarget.isPPC64();
4849 bool isDarwinABI = Subtarget.isDarwinABI();
Owen Anderson53aa7a92009-08-10 22:56:29 +00004850 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004851
4852 // Get current frame pointer save index. The users of this index will be
4853 // primarily DYNALLOC instructions.
4854 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4855 int RASI = FI->getReturnAddrSaveIndex();
4856
4857 // If the frame pointer save index hasn't been defined yet.
4858 if (!RASI) {
4859 // Find out what the fix offset of the frame pointer save area.
Anton Korobeynikov2f931282011-01-10 12:39:04 +00004860 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004861 // Allocate the frame index for frame pointer save area.
Evan Cheng0664a672010-07-03 00:40:23 +00004862 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004863 // Save the result.
4864 FI->setReturnAddrSaveIndex(RASI);
4865 }
4866 return DAG.getFrameIndex(RASI, PtrVT);
4867}
4868
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004869SDValue
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004870PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4871 MachineFunction &MF = DAG.getMachineFunction();
Eric Christopherb1aaebe2014-06-12 22:38:18 +00004872 bool isPPC64 = Subtarget.isPPC64();
4873 bool isDarwinABI = Subtarget.isDarwinABI();
Owen Anderson53aa7a92009-08-10 22:56:29 +00004874 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Jim Laskey48850c12006-11-16 22:43:37 +00004875
4876 // Get current frame pointer save index. The users of this index will be
4877 // primarily DYNALLOC instructions.
4878 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4879 int FPSI = FI->getFramePointerSaveIndex();
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004880
Jim Laskey48850c12006-11-16 22:43:37 +00004881 // If the frame pointer save index hasn't been defined yet.
4882 if (!FPSI) {
4883 // Find out what the fix offset of the frame pointer save area.
Anton Korobeynikov2f931282011-01-10 12:39:04 +00004884 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
Tilmann Scheller773f14c2009-07-03 06:47:08 +00004885 isDarwinABI);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004886
Jim Laskey48850c12006-11-16 22:43:37 +00004887 // Allocate the frame index for frame pointer save area.
Evan Cheng0664a672010-07-03 00:40:23 +00004888 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
Jim Laskey48850c12006-11-16 22:43:37 +00004889 // Save the result.
Scott Michelcf0da6c2009-02-17 22:15:04 +00004890 FI->setFramePointerSaveIndex(FPSI);
Jim Laskey48850c12006-11-16 22:43:37 +00004891 }
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004892 return DAG.getFrameIndex(FPSI, PtrVT);
4893}
Jim Laskey48850c12006-11-16 22:43:37 +00004894
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004895SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
Arnold Schwaighoferbe0de342008-04-30 09:16:33 +00004896 SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +00004897 const PPCSubtarget &Subtarget) const {
Jim Laskey48850c12006-11-16 22:43:37 +00004898 // Get the inputs.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004899 SDValue Chain = Op.getOperand(0);
4900 SDValue Size = Op.getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +00004901 SDLoc dl(Op);
Scott Michelcf0da6c2009-02-17 22:15:04 +00004902
Jim Laskey48850c12006-11-16 22:43:37 +00004903 // Get the corect type for pointers.
Owen Anderson53aa7a92009-08-10 22:56:29 +00004904 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Jim Laskey48850c12006-11-16 22:43:37 +00004905 // Negate the size.
Dale Johannesen400dc2e2009-02-06 21:50:26 +00004906 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
Jim Laskey48850c12006-11-16 22:43:37 +00004907 DAG.getConstant(0, PtrVT), Size);
4908 // Construct a node for the frame pointer save index.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004909 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
Jim Laskey48850c12006-11-16 22:43:37 +00004910 // Build a DYNALLOC node.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004911 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
Owen Anderson9f944592009-08-11 20:47:22 +00004912 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
Craig Topper48d114b2014-04-26 18:35:24 +00004913 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
Jim Laskey48850c12006-11-16 22:43:37 +00004914}
4915
Hal Finkel756810f2013-03-21 21:37:52 +00004916SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4917 SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00004918 SDLoc DL(Op);
Hal Finkel756810f2013-03-21 21:37:52 +00004919 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4920 DAG.getVTList(MVT::i32, MVT::Other),
4921 Op.getOperand(0), Op.getOperand(1));
4922}
4923
4924SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4925 SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00004926 SDLoc DL(Op);
Hal Finkel756810f2013-03-21 21:37:52 +00004927 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4928 Op.getOperand(0), Op.getOperand(1));
4929}
4930
Hal Finkel940ab932014-02-28 00:27:01 +00004931SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4932 assert(Op.getValueType() == MVT::i1 &&
4933 "Custom lowering only for i1 loads");
4934
4935 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4936
4937 SDLoc dl(Op);
4938 LoadSDNode *LD = cast<LoadSDNode>(Op);
4939
4940 SDValue Chain = LD->getChain();
4941 SDValue BasePtr = LD->getBasePtr();
4942 MachineMemOperand *MMO = LD->getMemOperand();
4943
4944 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4945 BasePtr, MVT::i8, MMO);
4946 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4947
4948 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
Craig Topper64941d92014-04-27 19:20:57 +00004949 return DAG.getMergeValues(Ops, dl);
Hal Finkel940ab932014-02-28 00:27:01 +00004950}
4951
4952SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4953 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4954 "Custom lowering only for i1 stores");
4955
4956 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4957
4958 SDLoc dl(Op);
4959 StoreSDNode *ST = cast<StoreSDNode>(Op);
4960
4961 SDValue Chain = ST->getChain();
4962 SDValue BasePtr = ST->getBasePtr();
4963 SDValue Value = ST->getValue();
4964 MachineMemOperand *MMO = ST->getMemOperand();
4965
4966 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4967 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4968}
4969
4970// FIXME: Remove this once the ANDI glue bug is fixed:
4971SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4972 assert(Op.getValueType() == MVT::i1 &&
4973 "Custom lowering only for i1 results");
4974
4975 SDLoc DL(Op);
4976 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
4977 Op.getOperand(0));
4978}
4979
Chris Lattner4211ca92006-04-14 06:01:58 +00004980/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4981/// possible.
Dan Gohman21cea8a2010-04-17 15:26:15 +00004982SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
Chris Lattner4211ca92006-04-14 06:01:58 +00004983 // Not FP? Not a fsel.
Duncan Sands13237ac2008-06-06 12:08:01 +00004984 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4985 !Op.getOperand(2).getValueType().isFloatingPoint())
Eli Friedman5806e182009-05-28 04:31:08 +00004986 return Op;
Scott Michelcf0da6c2009-02-17 22:15:04 +00004987
Hal Finkel81f87992013-04-07 22:11:09 +00004988 // We might be able to do better than this under some circumstances, but in
4989 // general, fsel-based lowering of select is a finite-math-only optimization.
4990 // For more information, see section F.3 of the 2.06 ISA specification.
4991 if (!DAG.getTarget().Options.NoInfsFPMath ||
4992 !DAG.getTarget().Options.NoNaNsFPMath)
4993 return Op;
Scott Michelcf0da6c2009-02-17 22:15:04 +00004994
Hal Finkel81f87992013-04-07 22:11:09 +00004995 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
Scott Michelcf0da6c2009-02-17 22:15:04 +00004996
Owen Anderson53aa7a92009-08-10 22:56:29 +00004997 EVT ResVT = Op.getValueType();
4998 EVT CmpVT = Op.getOperand(0).getValueType();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00004999 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5000 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
Andrew Trickef9de2a2013-05-25 02:42:55 +00005001 SDLoc dl(Op);
Scott Michelcf0da6c2009-02-17 22:15:04 +00005002
Chris Lattner4211ca92006-04-14 06:01:58 +00005003 // If the RHS of the comparison is a 0.0, we don't need to do the
5004 // subtraction at all.
Hal Finkel81f87992013-04-07 22:11:09 +00005005 SDValue Sel1;
Chris Lattner4211ca92006-04-14 06:01:58 +00005006 if (isFloatingPointZero(RHS))
5007 switch (CC) {
5008 default: break; // SETUO etc aren't handled by fsel.
Hal Finkel81f87992013-04-07 22:11:09 +00005009 case ISD::SETNE:
5010 std::swap(TV, FV);
5011 case ISD::SETEQ:
5012 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5013 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5014 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5015 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5016 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5017 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5018 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
Chris Lattner4211ca92006-04-14 06:01:58 +00005019 case ISD::SETULT:
5020 case ISD::SETLT:
5021 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
Chris Lattnerb56d22c2006-05-24 00:06:44 +00005022 case ISD::SETOGE:
Chris Lattner4211ca92006-04-14 06:01:58 +00005023 case ISD::SETGE:
Owen Anderson9f944592009-08-11 20:47:22 +00005024 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5025 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
Dale Johannesen400dc2e2009-02-06 21:50:26 +00005026 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
Chris Lattner4211ca92006-04-14 06:01:58 +00005027 case ISD::SETUGT:
5028 case ISD::SETGT:
5029 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
Chris Lattnerb56d22c2006-05-24 00:06:44 +00005030 case ISD::SETOLE:
Chris Lattner4211ca92006-04-14 06:01:58 +00005031 case ISD::SETLE:
Owen Anderson9f944592009-08-11 20:47:22 +00005032 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5033 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
Dale Johannesen400dc2e2009-02-06 21:50:26 +00005034 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
Owen Anderson9f944592009-08-11 20:47:22 +00005035 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
Chris Lattner4211ca92006-04-14 06:01:58 +00005036 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005037
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005038 SDValue Cmp;
Chris Lattner4211ca92006-04-14 06:01:58 +00005039 switch (CC) {
5040 default: break; // SETUO etc aren't handled by fsel.
Hal Finkel81f87992013-04-07 22:11:09 +00005041 case ISD::SETNE:
5042 std::swap(TV, FV);
5043 case ISD::SETEQ:
5044 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5045 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5046 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5047 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5048 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5049 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5050 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5051 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
Chris Lattner4211ca92006-04-14 06:01:58 +00005052 case ISD::SETULT:
5053 case ISD::SETLT:
Dale Johannesen400dc2e2009-02-06 21:50:26 +00005054 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
Owen Anderson9f944592009-08-11 20:47:22 +00005055 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5056 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
Hal Finkel81f87992013-04-07 22:11:09 +00005057 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
Chris Lattnerb56d22c2006-05-24 00:06:44 +00005058 case ISD::SETOGE:
Chris Lattner4211ca92006-04-14 06:01:58 +00005059 case ISD::SETGE:
Dale Johannesen400dc2e2009-02-06 21:50:26 +00005060 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
Owen Anderson9f944592009-08-11 20:47:22 +00005061 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5062 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
Hal Finkel81f87992013-04-07 22:11:09 +00005063 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
Chris Lattner4211ca92006-04-14 06:01:58 +00005064 case ISD::SETUGT:
5065 case ISD::SETGT:
Dale Johannesen400dc2e2009-02-06 21:50:26 +00005066 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
Owen Anderson9f944592009-08-11 20:47:22 +00005067 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5068 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
Hal Finkel81f87992013-04-07 22:11:09 +00005069 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
Chris Lattnerb56d22c2006-05-24 00:06:44 +00005070 case ISD::SETOLE:
Chris Lattner4211ca92006-04-14 06:01:58 +00005071 case ISD::SETLE:
Dale Johannesen400dc2e2009-02-06 21:50:26 +00005072 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
Owen Anderson9f944592009-08-11 20:47:22 +00005073 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5074 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
Hal Finkel81f87992013-04-07 22:11:09 +00005075 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
Chris Lattner4211ca92006-04-14 06:01:58 +00005076 }
Eli Friedman5806e182009-05-28 04:31:08 +00005077 return Op;
Chris Lattner4211ca92006-04-14 06:01:58 +00005078}
5079
Chris Lattner57ee7c62007-11-28 18:44:47 +00005080// FIXME: Split this code up when LegalizeDAGTypes lands.
Dale Johannesen37bc85f2009-06-04 20:53:52 +00005081SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00005082 SDLoc dl) const {
Duncan Sands13237ac2008-06-06 12:08:01 +00005083 assert(Op.getOperand(0).getValueType().isFloatingPoint());
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005084 SDValue Src = Op.getOperand(0);
Owen Anderson9f944592009-08-11 20:47:22 +00005085 if (Src.getValueType() == MVT::f32)
5086 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
Duncan Sands2a287912008-07-19 16:26:02 +00005087
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005088 SDValue Tmp;
Craig Topper56710102013-08-15 02:33:50 +00005089 switch (Op.getSimpleValueType().SimpleTy) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00005090 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
Owen Anderson9f944592009-08-11 20:47:22 +00005091 case MVT::i32:
Dale Johannesen37bc85f2009-06-04 20:53:52 +00005092 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005093 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
Hal Finkelf6d45f22013-04-01 17:52:07 +00005094 PPCISD::FCTIDZ),
Owen Anderson9f944592009-08-11 20:47:22 +00005095 dl, MVT::f64, Src);
Chris Lattner4211ca92006-04-14 06:01:58 +00005096 break;
Owen Anderson9f944592009-08-11 20:47:22 +00005097 case MVT::i64:
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005098 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
Hal Finkel3f88d082013-04-01 18:42:58 +00005099 "i64 FP_TO_UINT is supported only with FPCVT");
Hal Finkelf6d45f22013-04-01 17:52:07 +00005100 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5101 PPCISD::FCTIDUZ,
5102 dl, MVT::f64, Src);
Chris Lattner4211ca92006-04-14 06:01:58 +00005103 break;
5104 }
Duncan Sands2a287912008-07-19 16:26:02 +00005105
Chris Lattner4211ca92006-04-14 06:01:58 +00005106 // Convert the FP value to an int value through memory.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005107 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5108 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
Hal Finkelf6d45f22013-04-01 17:52:07 +00005109 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5110 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5111 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
Duncan Sands2a287912008-07-19 16:26:02 +00005112
Chris Lattner06a49542007-10-15 20:14:52 +00005113 // Emit a store to the stack slot.
Hal Finkelf6d45f22013-04-01 17:52:07 +00005114 SDValue Chain;
5115 if (i32Stack) {
5116 MachineFunction &MF = DAG.getMachineFunction();
5117 MachineMemOperand *MMO =
5118 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5119 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5120 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
Craig Topper206fcd42014-04-26 19:29:41 +00005121 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
Hal Finkelf6d45f22013-04-01 17:52:07 +00005122 } else
5123 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5124 MPI, false, false, 0);
Chris Lattner06a49542007-10-15 20:14:52 +00005125
5126 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5127 // add in a bias.
Hal Finkelf6d45f22013-04-01 17:52:07 +00005128 if (Op.getValueType() == MVT::i32 && !i32Stack) {
Dale Johannesen021052a2009-02-04 20:06:27 +00005129 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
Chris Lattner06a49542007-10-15 20:14:52 +00005130 DAG.getConstant(4, FIPtr.getValueType()));
Hal Finkelf6d45f22013-04-01 17:52:07 +00005131 MPI = MachinePointerInfo();
5132 }
5133
5134 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
Pete Cooper82cd9e82011-11-08 18:42:53 +00005135 false, false, false, 0);
Chris Lattner4211ca92006-04-14 06:01:58 +00005136}
5137
Hal Finkelf6d45f22013-04-01 17:52:07 +00005138SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
Dan Gohman21cea8a2010-04-17 15:26:15 +00005139 SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00005140 SDLoc dl(Op);
Dan Gohmand6819da2008-03-11 01:59:03 +00005141 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
Owen Anderson9f944592009-08-11 20:47:22 +00005142 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005143 return SDValue();
Dan Gohmand6819da2008-03-11 01:59:03 +00005144
Hal Finkel6a56b212014-03-05 22:14:00 +00005145 if (Op.getOperand(0).getValueType() == MVT::i1)
5146 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5147 DAG.getConstantFP(1.0, Op.getValueType()),
5148 DAG.getConstantFP(0.0, Op.getValueType()));
5149
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005150 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
Hal Finkelf6d45f22013-04-01 17:52:07 +00005151 "UINT_TO_FP is supported only with FPCVT");
5152
5153 // If we have FCFIDS, then use it when converting to single-precision.
Hal Finkel93d75ea2013-04-02 03:29:51 +00005154 // Otherwise, convert to double-precision and then round.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005155 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
Hal Finkelf6d45f22013-04-01 17:52:07 +00005156 (Op.getOpcode() == ISD::UINT_TO_FP ?
5157 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5158 (Op.getOpcode() == ISD::UINT_TO_FP ?
5159 PPCISD::FCFIDU : PPCISD::FCFID);
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005160 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
Hal Finkelf6d45f22013-04-01 17:52:07 +00005161 MVT::f32 : MVT::f64;
5162
Owen Anderson9f944592009-08-11 20:47:22 +00005163 if (Op.getOperand(0).getValueType() == MVT::i64) {
Ulrich Weigandd34b5bd2012-10-18 13:16:11 +00005164 SDValue SINT = Op.getOperand(0);
5165 // When converting to single-precision, we actually need to convert
5166 // to double-precision first and then round to single-precision.
5167 // To avoid double-rounding effects during that operation, we have
5168 // to prepare the input operand. Bits that might be truncated when
5169 // converting to double-precision are replaced by a bit that won't
5170 // be lost at this stage, but is below the single-precision rounding
5171 // position.
5172 //
5173 // However, if -enable-unsafe-fp-math is in effect, accept double
5174 // rounding to avoid the extra overhead.
5175 if (Op.getValueType() == MVT::f32 &&
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005176 !Subtarget.hasFPCVT() &&
Ulrich Weigandd34b5bd2012-10-18 13:16:11 +00005177 !DAG.getTarget().Options.UnsafeFPMath) {
5178
5179 // Twiddle input to make sure the low 11 bits are zero. (If this
5180 // is the case, we are guaranteed the value will fit into the 53 bit
5181 // mantissa of an IEEE double-precision value without rounding.)
5182 // If any of those low 11 bits were not zero originally, make sure
5183 // bit 12 (value 2048) is set instead, so that the final rounding
5184 // to single-precision gets the correct result.
5185 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5186 SINT, DAG.getConstant(2047, MVT::i64));
5187 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5188 Round, DAG.getConstant(2047, MVT::i64));
5189 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5190 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5191 Round, DAG.getConstant(-2048, MVT::i64));
5192
5193 // However, we cannot use that value unconditionally: if the magnitude
5194 // of the input value is small, the bit-twiddling we did above might
5195 // end up visibly changing the output. Fortunately, in that case, we
5196 // don't need to twiddle bits since the original input will convert
5197 // exactly to double-precision floating-point already. Therefore,
5198 // construct a conditional to use the original value if the top 11
5199 // bits are all sign-bit copies, and use the rounded value computed
5200 // above otherwise.
5201 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5202 SINT, DAG.getConstant(53, MVT::i32));
5203 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5204 Cond, DAG.getConstant(1, MVT::i64));
5205 Cond = DAG.getSetCC(dl, MVT::i32,
5206 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5207
5208 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5209 }
Hal Finkelf6d45f22013-04-01 17:52:07 +00005210
Ulrich Weigandd34b5bd2012-10-18 13:16:11 +00005211 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
Hal Finkelf6d45f22013-04-01 17:52:07 +00005212 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5213
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005214 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
Scott Michelcf0da6c2009-02-17 22:15:04 +00005215 FP = DAG.getNode(ISD::FP_ROUND, dl,
Owen Anderson9f944592009-08-11 20:47:22 +00005216 MVT::f32, FP, DAG.getIntPtrConstant(0));
Chris Lattner4211ca92006-04-14 06:01:58 +00005217 return FP;
5218 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005219
Owen Anderson9f944592009-08-11 20:47:22 +00005220 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
Hal Finkelf6d45f22013-04-01 17:52:07 +00005221 "Unhandled INT_TO_FP type in custom expander!");
Chris Lattner4211ca92006-04-14 06:01:58 +00005222 // Since we only generate this in 64-bit mode, we can take advantage of
5223 // 64-bit registers. In particular, sign extend the input value into the
5224 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5225 // then lfd it and fcfid it.
Dan Gohman48b185d2009-09-25 20:36:54 +00005226 MachineFunction &MF = DAG.getMachineFunction();
5227 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
Owen Anderson53aa7a92009-08-10 22:56:29 +00005228 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Scott Michelcf0da6c2009-02-17 22:15:04 +00005229
Hal Finkelbeb296b2013-03-31 10:12:51 +00005230 SDValue Ld;
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005231 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
Hal Finkelbeb296b2013-03-31 10:12:51 +00005232 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5233 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
Scott Michelcf0da6c2009-02-17 22:15:04 +00005234
Hal Finkelbeb296b2013-03-31 10:12:51 +00005235 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5236 MachinePointerInfo::getFixedStack(FrameIdx),
5237 false, false, 0);
Hal Finkele53429a2013-03-31 01:58:02 +00005238
Hal Finkelbeb296b2013-03-31 10:12:51 +00005239 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5240 "Expected an i32 store");
5241 MachineMemOperand *MMO =
5242 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5243 MachineMemOperand::MOLoad, 4, 4);
5244 SDValue Ops[] = { Store, FIdx };
Hal Finkelf6d45f22013-04-01 17:52:07 +00005245 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5246 PPCISD::LFIWZX : PPCISD::LFIWAX,
5247 dl, DAG.getVTList(MVT::f64, MVT::Other),
Craig Topper206fcd42014-04-26 19:29:41 +00005248 Ops, MVT::i32, MMO);
Hal Finkelbeb296b2013-03-31 10:12:51 +00005249 } else {
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005250 assert(Subtarget.isPPC64() &&
Hal Finkelf6d45f22013-04-01 17:52:07 +00005251 "i32->FP without LFIWAX supported only on PPC64");
5252
Hal Finkelbeb296b2013-03-31 10:12:51 +00005253 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5254 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5255
5256 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5257 Op.getOperand(0));
5258
5259 // STD the extended value into the stack slot.
5260 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5261 MachinePointerInfo::getFixedStack(FrameIdx),
5262 false, false, 0);
5263
5264 // Load the value as a double.
5265 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5266 MachinePointerInfo::getFixedStack(FrameIdx),
5267 false, false, false, 0);
5268 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005269
Chris Lattner4211ca92006-04-14 06:01:58 +00005270 // FCFID it and return it.
Hal Finkelf6d45f22013-04-01 17:52:07 +00005271 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005272 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
Owen Anderson9f944592009-08-11 20:47:22 +00005273 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
Chris Lattner4211ca92006-04-14 06:01:58 +00005274 return FP;
5275}
5276
Dan Gohman21cea8a2010-04-17 15:26:15 +00005277SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5278 SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00005279 SDLoc dl(Op);
Dale Johannesen5c94cb32008-01-18 19:55:37 +00005280 /*
5281 The rounding mode is in bits 30:31 of FPSR, and has the following
5282 settings:
5283 00 Round to nearest
5284 01 Round to 0
5285 10 Round to +inf
5286 11 Round to -inf
5287
5288 FLT_ROUNDS, on the other hand, expects the following:
5289 -1 Undefined
5290 0 Round to 0
5291 1 Round to nearest
5292 2 Round to +inf
5293 3 Round to -inf
5294
5295 To perform the conversion, we do:
5296 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5297 */
5298
5299 MachineFunction &MF = DAG.getMachineFunction();
Owen Anderson53aa7a92009-08-10 22:56:29 +00005300 EVT VT = Op.getValueType();
5301 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Dale Johannesen5c94cb32008-01-18 19:55:37 +00005302
5303 // Save FP Control Word to register
Benjamin Kramerfdf362b2013-03-07 20:33:29 +00005304 EVT NodeTys[] = {
5305 MVT::f64, // return register
5306 MVT::Glue // unused in this context
5307 };
Craig Topper2d2aa0c2014-04-30 07:17:30 +00005308 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
Dale Johannesen5c94cb32008-01-18 19:55:37 +00005309
5310 // Save FP register to stack slot
David Greene1fbe0542009-11-12 20:49:22 +00005311 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005312 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
Dale Johannesen021052a2009-02-04 20:06:27 +00005313 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
Chris Lattner676c61d2010-09-21 18:41:36 +00005314 StackSlot, MachinePointerInfo(), false, false,0);
Dale Johannesen5c94cb32008-01-18 19:55:37 +00005315
5316 // Load FP Control Word from low 32 bits of stack slot.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005317 SDValue Four = DAG.getConstant(4, PtrVT);
Dale Johannesen021052a2009-02-04 20:06:27 +00005318 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
Chris Lattner7727d052010-09-21 06:44:06 +00005319 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00005320 false, false, false, 0);
Dale Johannesen5c94cb32008-01-18 19:55:37 +00005321
5322 // Transform as necessary
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005323 SDValue CWD1 =
Owen Anderson9f944592009-08-11 20:47:22 +00005324 DAG.getNode(ISD::AND, dl, MVT::i32,
5325 CWD, DAG.getConstant(3, MVT::i32));
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005326 SDValue CWD2 =
Owen Anderson9f944592009-08-11 20:47:22 +00005327 DAG.getNode(ISD::SRL, dl, MVT::i32,
5328 DAG.getNode(ISD::AND, dl, MVT::i32,
5329 DAG.getNode(ISD::XOR, dl, MVT::i32,
5330 CWD, DAG.getConstant(3, MVT::i32)),
5331 DAG.getConstant(3, MVT::i32)),
5332 DAG.getConstant(1, MVT::i32));
Dale Johannesen5c94cb32008-01-18 19:55:37 +00005333
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005334 SDValue RetVal =
Owen Anderson9f944592009-08-11 20:47:22 +00005335 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
Dale Johannesen5c94cb32008-01-18 19:55:37 +00005336
Duncan Sands13237ac2008-06-06 12:08:01 +00005337 return DAG.getNode((VT.getSizeInBits() < 16 ?
Dale Johannesen021052a2009-02-04 20:06:27 +00005338 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
Dale Johannesen5c94cb32008-01-18 19:55:37 +00005339}
5340
Dan Gohman21cea8a2010-04-17 15:26:15 +00005341SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
Owen Anderson53aa7a92009-08-10 22:56:29 +00005342 EVT VT = Op.getValueType();
Duncan Sands13237ac2008-06-06 12:08:01 +00005343 unsigned BitWidth = VT.getSizeInBits();
Andrew Trickef9de2a2013-05-25 02:42:55 +00005344 SDLoc dl(Op);
Dan Gohman8d2ead22008-03-07 20:36:53 +00005345 assert(Op.getNumOperands() == 3 &&
5346 VT == Op.getOperand(1).getValueType() &&
5347 "Unexpected SHL!");
Scott Michelcf0da6c2009-02-17 22:15:04 +00005348
Chris Lattner601b8652006-09-20 03:47:40 +00005349 // Expand into a bunch of logical ops. Note that these ops
Chris Lattner4211ca92006-04-14 06:01:58 +00005350 // depend on the PPC behavior for oversized shift amounts.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005351 SDValue Lo = Op.getOperand(0);
5352 SDValue Hi = Op.getOperand(1);
5353 SDValue Amt = Op.getOperand(2);
Owen Anderson53aa7a92009-08-10 22:56:29 +00005354 EVT AmtVT = Amt.getValueType();
Scott Michelcf0da6c2009-02-17 22:15:04 +00005355
Dale Johannesen7ae8c8b2009-02-05 00:20:09 +00005356 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
Duncan Sands13105742008-10-30 19:28:32 +00005357 DAG.getConstant(BitWidth, AmtVT), Amt);
Dale Johannesen7ae8c8b2009-02-05 00:20:09 +00005358 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5359 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5360 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5361 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
Duncan Sands13105742008-10-30 19:28:32 +00005362 DAG.getConstant(-BitWidth, AmtVT));
Dale Johannesen7ae8c8b2009-02-05 00:20:09 +00005363 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5364 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5365 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005366 SDValue OutOps[] = { OutLo, OutHi };
Craig Topper64941d92014-04-27 19:20:57 +00005367 return DAG.getMergeValues(OutOps, dl);
Chris Lattner4211ca92006-04-14 06:01:58 +00005368}
5369
Dan Gohman21cea8a2010-04-17 15:26:15 +00005370SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
Owen Anderson53aa7a92009-08-10 22:56:29 +00005371 EVT VT = Op.getValueType();
Andrew Trickef9de2a2013-05-25 02:42:55 +00005372 SDLoc dl(Op);
Duncan Sands13237ac2008-06-06 12:08:01 +00005373 unsigned BitWidth = VT.getSizeInBits();
Dan Gohman8d2ead22008-03-07 20:36:53 +00005374 assert(Op.getNumOperands() == 3 &&
5375 VT == Op.getOperand(1).getValueType() &&
5376 "Unexpected SRL!");
Scott Michelcf0da6c2009-02-17 22:15:04 +00005377
Dan Gohman8d2ead22008-03-07 20:36:53 +00005378 // Expand into a bunch of logical ops. Note that these ops
Chris Lattner4211ca92006-04-14 06:01:58 +00005379 // depend on the PPC behavior for oversized shift amounts.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005380 SDValue Lo = Op.getOperand(0);
5381 SDValue Hi = Op.getOperand(1);
5382 SDValue Amt = Op.getOperand(2);
Owen Anderson53aa7a92009-08-10 22:56:29 +00005383 EVT AmtVT = Amt.getValueType();
Scott Michelcf0da6c2009-02-17 22:15:04 +00005384
Dale Johannesen7ae8c8b2009-02-05 00:20:09 +00005385 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
Duncan Sands13105742008-10-30 19:28:32 +00005386 DAG.getConstant(BitWidth, AmtVT), Amt);
Dale Johannesen7ae8c8b2009-02-05 00:20:09 +00005387 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5388 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5389 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5390 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
Duncan Sands13105742008-10-30 19:28:32 +00005391 DAG.getConstant(-BitWidth, AmtVT));
Dale Johannesen7ae8c8b2009-02-05 00:20:09 +00005392 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5393 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5394 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005395 SDValue OutOps[] = { OutLo, OutHi };
Craig Topper64941d92014-04-27 19:20:57 +00005396 return DAG.getMergeValues(OutOps, dl);
Chris Lattner4211ca92006-04-14 06:01:58 +00005397}
5398
Dan Gohman21cea8a2010-04-17 15:26:15 +00005399SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00005400 SDLoc dl(Op);
Owen Anderson53aa7a92009-08-10 22:56:29 +00005401 EVT VT = Op.getValueType();
Duncan Sands13237ac2008-06-06 12:08:01 +00005402 unsigned BitWidth = VT.getSizeInBits();
Dan Gohman8d2ead22008-03-07 20:36:53 +00005403 assert(Op.getNumOperands() == 3 &&
5404 VT == Op.getOperand(1).getValueType() &&
5405 "Unexpected SRA!");
Scott Michelcf0da6c2009-02-17 22:15:04 +00005406
Dan Gohman8d2ead22008-03-07 20:36:53 +00005407 // Expand into a bunch of logical ops, followed by a select_cc.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005408 SDValue Lo = Op.getOperand(0);
5409 SDValue Hi = Op.getOperand(1);
5410 SDValue Amt = Op.getOperand(2);
Owen Anderson53aa7a92009-08-10 22:56:29 +00005411 EVT AmtVT = Amt.getValueType();
Scott Michelcf0da6c2009-02-17 22:15:04 +00005412
Dale Johannesenf2bb6f02009-02-04 01:48:28 +00005413 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
Duncan Sands13105742008-10-30 19:28:32 +00005414 DAG.getConstant(BitWidth, AmtVT), Amt);
Dale Johannesenf2bb6f02009-02-04 01:48:28 +00005415 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5416 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5417 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5418 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
Duncan Sands13105742008-10-30 19:28:32 +00005419 DAG.getConstant(-BitWidth, AmtVT));
Dale Johannesenf2bb6f02009-02-04 01:48:28 +00005420 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5421 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5422 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
Duncan Sands13105742008-10-30 19:28:32 +00005423 Tmp4, Tmp6, ISD::SETLE);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005424 SDValue OutOps[] = { OutLo, OutHi };
Craig Topper64941d92014-04-27 19:20:57 +00005425 return DAG.getMergeValues(OutOps, dl);
Chris Lattner4211ca92006-04-14 06:01:58 +00005426}
5427
5428//===----------------------------------------------------------------------===//
5429// Vector related lowering.
5430//
5431
Chris Lattner2a099c02006-04-17 06:00:21 +00005432/// BuildSplatI - Build a canonical splati of Val with an element size of
5433/// SplatSize. Cast the result to VT.
Owen Anderson53aa7a92009-08-10 22:56:29 +00005434static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
Andrew Trickef9de2a2013-05-25 02:42:55 +00005435 SelectionDAG &DAG, SDLoc dl) {
Chris Lattner2a099c02006-04-17 06:00:21 +00005436 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
Chris Lattner09ed0ff2006-12-01 01:45:39 +00005437
Owen Anderson53aa7a92009-08-10 22:56:29 +00005438 static const EVT VTys[] = { // canonical VT to use for each size.
Owen Anderson9f944592009-08-11 20:47:22 +00005439 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
Chris Lattner2a099c02006-04-17 06:00:21 +00005440 };
Chris Lattner09ed0ff2006-12-01 01:45:39 +00005441
Owen Anderson9f944592009-08-11 20:47:22 +00005442 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
Scott Michelcf0da6c2009-02-17 22:15:04 +00005443
Chris Lattner09ed0ff2006-12-01 01:45:39 +00005444 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5445 if (Val == -1)
5446 SplatSize = 1;
Scott Michelcf0da6c2009-02-17 22:15:04 +00005447
Owen Anderson53aa7a92009-08-10 22:56:29 +00005448 EVT CanonicalVT = VTys[SplatSize-1];
Scott Michelcf0da6c2009-02-17 22:15:04 +00005449
Chris Lattner2a099c02006-04-17 06:00:21 +00005450 // Build a canonical splat for this value.
Owen Anderson9f944592009-08-11 20:47:22 +00005451 SDValue Elt = DAG.getConstant(Val, MVT::i32);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005452 SmallVector<SDValue, 8> Ops;
Duncan Sands13237ac2008-06-06 12:08:01 +00005453 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
Craig Topper48d114b2014-04-26 18:35:24 +00005454 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
Wesley Peck527da1b2010-11-23 03:31:01 +00005455 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
Chris Lattner2a099c02006-04-17 06:00:21 +00005456}
5457
Hal Finkelcf2e9082013-05-24 23:00:14 +00005458/// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5459/// specified intrinsic ID.
5460static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
Andrew Trickef9de2a2013-05-25 02:42:55 +00005461 SelectionDAG &DAG, SDLoc dl,
Hal Finkelcf2e9082013-05-24 23:00:14 +00005462 EVT DestVT = MVT::Other) {
5463 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5464 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5465 DAG.getConstant(IID, MVT::i32), Op);
5466}
5467
Chris Lattnera2cae1b2006-04-18 03:24:30 +00005468/// BuildIntrinsicOp - Return a binary operator intrinsic node with the
Chris Lattner1b3806a2006-04-17 06:58:41 +00005469/// specified intrinsic ID.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005470static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
Andrew Trickef9de2a2013-05-25 02:42:55 +00005471 SelectionDAG &DAG, SDLoc dl,
Owen Anderson9f944592009-08-11 20:47:22 +00005472 EVT DestVT = MVT::Other) {
5473 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00005474 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
Owen Anderson9f944592009-08-11 20:47:22 +00005475 DAG.getConstant(IID, MVT::i32), LHS, RHS);
Chris Lattner1b3806a2006-04-17 06:58:41 +00005476}
5477
Chris Lattnera2cae1b2006-04-18 03:24:30 +00005478/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5479/// specified intrinsic ID.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005480static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00005481 SDValue Op2, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00005482 SDLoc dl, EVT DestVT = MVT::Other) {
Owen Anderson9f944592009-08-11 20:47:22 +00005483 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00005484 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
Owen Anderson9f944592009-08-11 20:47:22 +00005485 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
Chris Lattnera2cae1b2006-04-18 03:24:30 +00005486}
5487
5488
Chris Lattner264c9082006-04-17 17:55:10 +00005489/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5490/// amount. The result has the specified value type.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005491static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
Andrew Trickef9de2a2013-05-25 02:42:55 +00005492 EVT VT, SelectionDAG &DAG, SDLoc dl) {
Chris Lattner264c9082006-04-17 17:55:10 +00005493 // Force LHS/RHS to be the right type.
Wesley Peck527da1b2010-11-23 03:31:01 +00005494 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5495 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
Duncan Sandsb0e39382008-07-21 10:20:31 +00005496
Nate Begeman8d6d4b92009-04-27 18:41:29 +00005497 int Ops[16];
Chris Lattner264c9082006-04-17 17:55:10 +00005498 for (unsigned i = 0; i != 16; ++i)
Nate Begeman8d6d4b92009-04-27 18:41:29 +00005499 Ops[i] = i + Amt;
Owen Anderson9f944592009-08-11 20:47:22 +00005500 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
Wesley Peck527da1b2010-11-23 03:31:01 +00005501 return DAG.getNode(ISD::BITCAST, dl, VT, T);
Chris Lattner264c9082006-04-17 17:55:10 +00005502}
5503
Chris Lattner19e90552006-04-14 05:19:18 +00005504// If this is a case we can't handle, return null and let the default
5505// expansion code take care of it. If we CAN select this case, and if it
5506// selects to a single instruction, return Op. Otherwise, if we can codegen
5507// this case more efficiently than a constant pool load, lower it to the
5508// sequence of ops that should be used.
Dan Gohman21cea8a2010-04-17 15:26:15 +00005509SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5510 SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00005511 SDLoc dl(Op);
Bob Wilsond8ea0e12009-03-01 01:13:55 +00005512 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
Craig Toppere73658d2014-04-28 04:05:08 +00005513 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
Scott Michelbb878282009-02-25 03:12:50 +00005514
Bob Wilson85cefe82009-03-02 23:24:16 +00005515 // Check if this is a splat of a constant value.
5516 APInt APSplatBits, APSplatUndef;
5517 unsigned SplatBitSize;
Bob Wilsond8ea0e12009-03-01 01:13:55 +00005518 bool HasAnyUndefs;
Bob Wilson530e0382009-03-03 19:26:27 +00005519 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
Dale Johannesen5f4eecf2009-11-13 01:45:18 +00005520 HasAnyUndefs, 0, true) || SplatBitSize > 32)
Bob Wilson530e0382009-03-03 19:26:27 +00005521 return SDValue();
Evan Chenga49de9d2009-02-25 22:49:59 +00005522
Bob Wilson530e0382009-03-03 19:26:27 +00005523 unsigned SplatBits = APSplatBits.getZExtValue();
5524 unsigned SplatUndef = APSplatUndef.getZExtValue();
5525 unsigned SplatSize = SplatBitSize / 8;
Scott Michelcf0da6c2009-02-17 22:15:04 +00005526
Bob Wilson530e0382009-03-03 19:26:27 +00005527 // First, handle single instruction cases.
5528
5529 // All zeros?
5530 if (SplatBits == 0) {
5531 // Canonicalize all zero vectors to be v4i32.
Owen Anderson9f944592009-08-11 20:47:22 +00005532 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5533 SDValue Z = DAG.getConstant(0, MVT::i32);
5534 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
Wesley Peck527da1b2010-11-23 03:31:01 +00005535 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
Chris Lattner19e90552006-04-14 05:19:18 +00005536 }
Bob Wilson530e0382009-03-03 19:26:27 +00005537 return Op;
5538 }
Chris Lattnerfa5aa392006-04-16 01:01:29 +00005539
Bob Wilson530e0382009-03-03 19:26:27 +00005540 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5541 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5542 (32-SplatBitSize));
5543 if (SextVal >= -16 && SextVal <= 15)
5544 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
Scott Michelcf0da6c2009-02-17 22:15:04 +00005545
5546
Bob Wilson530e0382009-03-03 19:26:27 +00005547 // Two instruction sequences.
Scott Michelcf0da6c2009-02-17 22:15:04 +00005548
Bob Wilson530e0382009-03-03 19:26:27 +00005549 // If this value is in the range [-32,30] and is even, use:
Bill Schmidtc6cbecc2013-02-20 20:41:42 +00005550 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5551 // If this value is in the range [17,31] and is odd, use:
5552 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5553 // If this value is in the range [-31,-17] and is odd, use:
5554 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5555 // Note the last two are three-instruction sequences.
5556 if (SextVal >= -32 && SextVal <= 31) {
5557 // To avoid having these optimizations undone by constant folding,
5558 // we convert to a pseudo that will be expanded later into one of
5559 // the above forms.
5560 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
Bill Schmidt71dddd52014-05-27 15:57:51 +00005561 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5562 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5563 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5564 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5565 if (VT == Op.getValueType())
5566 return RetVal;
5567 else
5568 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
Bob Wilson530e0382009-03-03 19:26:27 +00005569 }
5570
5571 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5572 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5573 // for fneg/fabs.
5574 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5575 // Make -1 and vspltisw -1:
Owen Anderson9f944592009-08-11 20:47:22 +00005576 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
Bob Wilson530e0382009-03-03 19:26:27 +00005577
5578 // Make the VSLW intrinsic, computing 0x8000_0000.
5579 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5580 OnesV, DAG, dl);
5581
5582 // xor by OnesV to invert it.
Owen Anderson9f944592009-08-11 20:47:22 +00005583 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
Wesley Peck527da1b2010-11-23 03:31:01 +00005584 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
Bob Wilson530e0382009-03-03 19:26:27 +00005585 }
5586
Bill Schmidt4aedff82014-06-06 14:06:26 +00005587 // The remaining cases assume either big endian element order or
5588 // a splat-size that equates to the element size of the vector
5589 // to be built. An example that doesn't work for little endian is
5590 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5591 // and a vector element size of 16 bits. The code below will
5592 // produce the vector in big endian element order, which for little
5593 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5594
5595 // For now, just avoid these optimizations in that case.
5596 // FIXME: Develop correct optimizations for LE with mismatched
5597 // splat and element sizes.
5598
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005599 if (Subtarget.isLittleEndian() &&
Bill Schmidt4aedff82014-06-06 14:06:26 +00005600 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5601 return SDValue();
5602
Bob Wilson530e0382009-03-03 19:26:27 +00005603 // Check to see if this is a wide variety of vsplti*, binop self cases.
5604 static const signed char SplatCsts[] = {
5605 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5606 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5607 };
5608
5609 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5610 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5611 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5612 int i = SplatCsts[idx];
5613
5614 // Figure out what shift amount will be used by altivec if shifted by i in
5615 // this splat size.
5616 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5617
5618 // vsplti + shl self.
Richard Smith228e6d42012-08-24 23:29:28 +00005619 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
Owen Anderson9f944592009-08-11 20:47:22 +00005620 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
Bob Wilson530e0382009-03-03 19:26:27 +00005621 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5622 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5623 Intrinsic::ppc_altivec_vslw
5624 };
5625 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
Wesley Peck527da1b2010-11-23 03:31:01 +00005626 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
Chris Lattner2a099c02006-04-17 06:00:21 +00005627 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005628
Bob Wilson530e0382009-03-03 19:26:27 +00005629 // vsplti + srl self.
5630 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
Owen Anderson9f944592009-08-11 20:47:22 +00005631 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
Bob Wilson530e0382009-03-03 19:26:27 +00005632 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5633 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5634 Intrinsic::ppc_altivec_vsrw
5635 };
5636 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
Wesley Peck527da1b2010-11-23 03:31:01 +00005637 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
Chris Lattner1b3806a2006-04-17 06:58:41 +00005638 }
5639
Bob Wilson530e0382009-03-03 19:26:27 +00005640 // vsplti + sra self.
5641 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
Owen Anderson9f944592009-08-11 20:47:22 +00005642 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
Bob Wilson530e0382009-03-03 19:26:27 +00005643 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5644 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5645 Intrinsic::ppc_altivec_vsraw
5646 };
5647 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
Wesley Peck527da1b2010-11-23 03:31:01 +00005648 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
Chris Lattner1b3806a2006-04-17 06:58:41 +00005649 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005650
Bob Wilson530e0382009-03-03 19:26:27 +00005651 // vsplti + rol self.
5652 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5653 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
Owen Anderson9f944592009-08-11 20:47:22 +00005654 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
Bob Wilson530e0382009-03-03 19:26:27 +00005655 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5656 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5657 Intrinsic::ppc_altivec_vrlw
5658 };
5659 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
Wesley Peck527da1b2010-11-23 03:31:01 +00005660 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
Bob Wilson530e0382009-03-03 19:26:27 +00005661 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005662
Bob Wilson530e0382009-03-03 19:26:27 +00005663 // t = vsplti c, result = vsldoi t, t, 1
Richard Smith228e6d42012-08-24 23:29:28 +00005664 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
Owen Anderson9f944592009-08-11 20:47:22 +00005665 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
Bob Wilson530e0382009-03-03 19:26:27 +00005666 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
Chris Lattnere54133c2006-04-17 18:09:22 +00005667 }
Bob Wilson530e0382009-03-03 19:26:27 +00005668 // t = vsplti c, result = vsldoi t, t, 2
Richard Smith228e6d42012-08-24 23:29:28 +00005669 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
Owen Anderson9f944592009-08-11 20:47:22 +00005670 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
Bob Wilson530e0382009-03-03 19:26:27 +00005671 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
Chris Lattner19e90552006-04-14 05:19:18 +00005672 }
Bob Wilson530e0382009-03-03 19:26:27 +00005673 // t = vsplti c, result = vsldoi t, t, 3
Richard Smith228e6d42012-08-24 23:29:28 +00005674 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
Owen Anderson9f944592009-08-11 20:47:22 +00005675 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
Bob Wilson530e0382009-03-03 19:26:27 +00005676 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5677 }
5678 }
5679
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005680 return SDValue();
Chris Lattner19e90552006-04-14 05:19:18 +00005681}
5682
Chris Lattner071ad012006-04-17 05:28:54 +00005683/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5684/// the specified operations to build the shuffle.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005685static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
Scott Michelcf0da6c2009-02-17 22:15:04 +00005686 SDValue RHS, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00005687 SDLoc dl) {
Chris Lattner071ad012006-04-17 05:28:54 +00005688 unsigned OpNum = (PFEntry >> 26) & 0x0F;
Bill Wendling95e1af22008-09-17 00:30:57 +00005689 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
Chris Lattner071ad012006-04-17 05:28:54 +00005690 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
Scott Michelcf0da6c2009-02-17 22:15:04 +00005691
Chris Lattner071ad012006-04-17 05:28:54 +00005692 enum {
Chris Lattnerd2ca9ab2006-05-16 04:20:24 +00005693 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
Chris Lattner071ad012006-04-17 05:28:54 +00005694 OP_VMRGHW,
5695 OP_VMRGLW,
5696 OP_VSPLTISW0,
5697 OP_VSPLTISW1,
5698 OP_VSPLTISW2,
5699 OP_VSPLTISW3,
5700 OP_VSLDOI4,
5701 OP_VSLDOI8,
Chris Lattneraa2372562006-05-24 17:04:05 +00005702 OP_VSLDOI12
Chris Lattner071ad012006-04-17 05:28:54 +00005703 };
Scott Michelcf0da6c2009-02-17 22:15:04 +00005704
Chris Lattner071ad012006-04-17 05:28:54 +00005705 if (OpNum == OP_COPY) {
5706 if (LHSID == (1*9+2)*9+3) return LHS;
5707 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5708 return RHS;
5709 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005710
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005711 SDValue OpLHS, OpRHS;
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00005712 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5713 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
Scott Michelcf0da6c2009-02-17 22:15:04 +00005714
Nate Begeman8d6d4b92009-04-27 18:41:29 +00005715 int ShufIdxs[16];
Chris Lattner071ad012006-04-17 05:28:54 +00005716 switch (OpNum) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00005717 default: llvm_unreachable("Unknown i32 permute!");
Chris Lattner071ad012006-04-17 05:28:54 +00005718 case OP_VMRGHW:
5719 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5720 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5721 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5722 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5723 break;
5724 case OP_VMRGLW:
5725 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5726 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5727 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5728 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5729 break;
5730 case OP_VSPLTISW0:
5731 for (unsigned i = 0; i != 16; ++i)
5732 ShufIdxs[i] = (i&3)+0;
5733 break;
5734 case OP_VSPLTISW1:
5735 for (unsigned i = 0; i != 16; ++i)
5736 ShufIdxs[i] = (i&3)+4;
5737 break;
5738 case OP_VSPLTISW2:
5739 for (unsigned i = 0; i != 16; ++i)
5740 ShufIdxs[i] = (i&3)+8;
5741 break;
5742 case OP_VSPLTISW3:
5743 for (unsigned i = 0; i != 16; ++i)
5744 ShufIdxs[i] = (i&3)+12;
5745 break;
5746 case OP_VSLDOI4:
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00005747 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
Chris Lattner071ad012006-04-17 05:28:54 +00005748 case OP_VSLDOI8:
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00005749 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
Chris Lattner071ad012006-04-17 05:28:54 +00005750 case OP_VSLDOI12:
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00005751 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
Chris Lattner071ad012006-04-17 05:28:54 +00005752 }
Owen Anderson53aa7a92009-08-10 22:56:29 +00005753 EVT VT = OpLHS.getValueType();
Wesley Peck527da1b2010-11-23 03:31:01 +00005754 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5755 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
Owen Anderson9f944592009-08-11 20:47:22 +00005756 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
Wesley Peck527da1b2010-11-23 03:31:01 +00005757 return DAG.getNode(ISD::BITCAST, dl, VT, T);
Chris Lattner071ad012006-04-17 05:28:54 +00005758}
5759
Chris Lattner19e90552006-04-14 05:19:18 +00005760/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5761/// is a shuffle we can handle in a single instruction, return it. Otherwise,
5762/// return the code it can be lowered into. Worst case, it can always be
5763/// lowered into a vperm.
Scott Michelcf0da6c2009-02-17 22:15:04 +00005764SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
Dan Gohman21cea8a2010-04-17 15:26:15 +00005765 SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00005766 SDLoc dl(Op);
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005767 SDValue V1 = Op.getOperand(0);
5768 SDValue V2 = Op.getOperand(1);
Nate Begeman8d6d4b92009-04-27 18:41:29 +00005769 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
Owen Anderson53aa7a92009-08-10 22:56:29 +00005770 EVT VT = Op.getValueType();
Eric Christopherb1aaebe2014-06-12 22:38:18 +00005771 bool isLittleEndian = Subtarget.isLittleEndian();
Scott Michelcf0da6c2009-02-17 22:15:04 +00005772
Chris Lattner19e90552006-04-14 05:19:18 +00005773 // Cases that are handled by instructions that take permute immediates
5774 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5775 // selected by the instruction selector.
5776 if (V2.getOpcode() == ISD::UNDEF) {
Nate Begeman8d6d4b92009-04-27 18:41:29 +00005777 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5778 PPC::isSplatShuffleMask(SVOp, 2) ||
5779 PPC::isSplatShuffleMask(SVOp, 4) ||
Bill Schmidtf910a062014-06-10 14:35:01 +00005780 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
5781 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
5782 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
5783 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
5784 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
5785 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
5786 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
5787 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
5788 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
Chris Lattner19e90552006-04-14 05:19:18 +00005789 return Op;
5790 }
5791 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005792
Chris Lattner19e90552006-04-14 05:19:18 +00005793 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5794 // and produce a fixed permutation. If any of these match, do not lower to
5795 // VPERM.
Bill Schmidtf910a062014-06-10 14:35:01 +00005796 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
5797 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
5798 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
5799 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
5800 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
5801 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
5802 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
5803 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
5804 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
Chris Lattner19e90552006-04-14 05:19:18 +00005805 return Op;
Scott Michelcf0da6c2009-02-17 22:15:04 +00005806
Chris Lattner071ad012006-04-17 05:28:54 +00005807 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5808 // perfect shuffle table to emit an optimal matching sequence.
Benjamin Kramer339ced42012-01-15 13:16:05 +00005809 ArrayRef<int> PermMask = SVOp->getMask();
Wesley Peck527da1b2010-11-23 03:31:01 +00005810
Chris Lattner071ad012006-04-17 05:28:54 +00005811 unsigned PFIndexes[4];
5812 bool isFourElementShuffle = true;
5813 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5814 unsigned EltNo = 8; // Start out undef.
5815 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
Nate Begeman8d6d4b92009-04-27 18:41:29 +00005816 if (PermMask[i*4+j] < 0)
Chris Lattner071ad012006-04-17 05:28:54 +00005817 continue; // Undef, ignore it.
Scott Michelcf0da6c2009-02-17 22:15:04 +00005818
Nate Begeman8d6d4b92009-04-27 18:41:29 +00005819 unsigned ByteSource = PermMask[i*4+j];
Chris Lattner071ad012006-04-17 05:28:54 +00005820 if ((ByteSource & 3) != j) {
5821 isFourElementShuffle = false;
5822 break;
5823 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005824
Chris Lattner071ad012006-04-17 05:28:54 +00005825 if (EltNo == 8) {
5826 EltNo = ByteSource/4;
5827 } else if (EltNo != ByteSource/4) {
5828 isFourElementShuffle = false;
5829 break;
5830 }
5831 }
5832 PFIndexes[i] = EltNo;
5833 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005834
5835 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
Chris Lattner071ad012006-04-17 05:28:54 +00005836 // perfect shuffle vector to determine if it is cost effective to do this as
5837 // discrete instructions, or whether we should use a vperm.
Bill Schmidtf910a062014-06-10 14:35:01 +00005838 // For now, we skip this for little endian until such time as we have a
5839 // little-endian perfect shuffle table.
5840 if (isFourElementShuffle && !isLittleEndian) {
Chris Lattner071ad012006-04-17 05:28:54 +00005841 // Compute the index in the perfect shuffle table.
Scott Michelcf0da6c2009-02-17 22:15:04 +00005842 unsigned PFTableIndex =
Chris Lattner071ad012006-04-17 05:28:54 +00005843 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
Scott Michelcf0da6c2009-02-17 22:15:04 +00005844
Chris Lattner071ad012006-04-17 05:28:54 +00005845 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5846 unsigned Cost = (PFEntry >> 30);
Scott Michelcf0da6c2009-02-17 22:15:04 +00005847
Chris Lattner071ad012006-04-17 05:28:54 +00005848 // Determining when to avoid vperm is tricky. Many things affect the cost
5849 // of vperm, particularly how many times the perm mask needs to be computed.
5850 // For example, if the perm mask can be hoisted out of a loop or is already
5851 // used (perhaps because there are multiple permutes with the same shuffle
5852 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5853 // the loop requires an extra register.
5854 //
5855 // As a compromise, we only emit discrete instructions if the shuffle can be
Scott Michelcf0da6c2009-02-17 22:15:04 +00005856 // generated in 3 or fewer operations. When we have loop information
Chris Lattner071ad012006-04-17 05:28:54 +00005857 // available, if this block is within a loop, we should avoid using vperm
5858 // for 3-operation perms and use a constant pool load instead.
Scott Michelcf0da6c2009-02-17 22:15:04 +00005859 if (Cost < 3)
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00005860 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
Chris Lattner071ad012006-04-17 05:28:54 +00005861 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005862
Chris Lattner19e90552006-04-14 05:19:18 +00005863 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5864 // vector that will get spilled to the constant pool.
5865 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
Scott Michelcf0da6c2009-02-17 22:15:04 +00005866
Chris Lattner19e90552006-04-14 05:19:18 +00005867 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5868 // that it is in input element units, not in bytes. Convert now.
Bill Schmidt4aedff82014-06-06 14:06:26 +00005869
5870 // For little endian, the order of the input vectors is reversed, and
5871 // the permutation mask is complemented with respect to 31. This is
5872 // necessary to produce proper semantics with the big-endian-biased vperm
5873 // instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +00005874 EVT EltVT = V1.getValueType().getVectorElementType();
Duncan Sands13237ac2008-06-06 12:08:01 +00005875 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
Scott Michelcf0da6c2009-02-17 22:15:04 +00005876
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005877 SmallVector<SDValue, 16> ResultMask;
Nate Begeman8d6d4b92009-04-27 18:41:29 +00005878 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5879 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
Scott Michelcf0da6c2009-02-17 22:15:04 +00005880
Chris Lattner19e90552006-04-14 05:19:18 +00005881 for (unsigned j = 0; j != BytesPerElement; ++j)
Bill Schmidt4aedff82014-06-06 14:06:26 +00005882 if (isLittleEndian)
5883 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
5884 MVT::i32));
5885 else
5886 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5887 MVT::i32));
Chris Lattner19e90552006-04-14 05:19:18 +00005888 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005889
Owen Anderson9f944592009-08-11 20:47:22 +00005890 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
Craig Topper48d114b2014-04-26 18:35:24 +00005891 ResultMask);
Bill Schmidt4aedff82014-06-06 14:06:26 +00005892 if (isLittleEndian)
5893 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5894 V2, V1, VPermMask);
5895 else
5896 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5897 V1, V2, VPermMask);
Chris Lattner19e90552006-04-14 05:19:18 +00005898}
5899
Chris Lattner9754d142006-04-18 17:59:36 +00005900/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5901/// altivec comparison. If it is, return true and fill in Opc/isDot with
5902/// information about the intrinsic.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005903static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
Chris Lattner9754d142006-04-18 17:59:36 +00005904 bool &isDot) {
Dan Gohmaneffb8942008-09-12 16:56:44 +00005905 unsigned IntrinsicID =
5906 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
Chris Lattner9754d142006-04-18 17:59:36 +00005907 CompareOpc = -1;
5908 isDot = false;
5909 switch (IntrinsicID) {
5910 default: return false;
5911 // Comparison predicates.
Chris Lattner4211ca92006-04-14 06:01:58 +00005912 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5913 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5914 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5915 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5916 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5917 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5918 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5919 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5920 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5921 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5922 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5923 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5924 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
Scott Michelcf0da6c2009-02-17 22:15:04 +00005925
Chris Lattner4211ca92006-04-14 06:01:58 +00005926 // Normal Comparisons.
5927 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5928 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5929 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5930 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5931 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5932 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5933 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5934 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5935 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5936 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5937 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5938 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5939 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5940 }
Chris Lattner9754d142006-04-18 17:59:36 +00005941 return true;
5942}
5943
5944/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5945/// lower, do it, otherwise return null.
Scott Michelcf0da6c2009-02-17 22:15:04 +00005946SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
Dan Gohman21cea8a2010-04-17 15:26:15 +00005947 SelectionDAG &DAG) const {
Chris Lattner9754d142006-04-18 17:59:36 +00005948 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5949 // opcode number of the comparison.
Andrew Trickef9de2a2013-05-25 02:42:55 +00005950 SDLoc dl(Op);
Chris Lattner9754d142006-04-18 17:59:36 +00005951 int CompareOpc;
5952 bool isDot;
5953 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005954 return SDValue(); // Don't custom lower most intrinsics.
Scott Michelcf0da6c2009-02-17 22:15:04 +00005955
Chris Lattner9754d142006-04-18 17:59:36 +00005956 // If this is a non-dot comparison, make the VCMP node and we are done.
Chris Lattner4211ca92006-04-14 06:01:58 +00005957 if (!isDot) {
Dale Johannesenf80493b2009-02-05 22:07:54 +00005958 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
Chris Lattner9fa851b2010-03-14 22:44:11 +00005959 Op.getOperand(1), Op.getOperand(2),
5960 DAG.getConstant(CompareOpc, MVT::i32));
Wesley Peck527da1b2010-11-23 03:31:01 +00005961 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
Chris Lattner4211ca92006-04-14 06:01:58 +00005962 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005963
Chris Lattner4211ca92006-04-14 06:01:58 +00005964 // Create the PPCISD altivec 'dot' comparison node.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00005965 SDValue Ops[] = {
Chris Lattnerd66f14e2006-08-11 17:18:05 +00005966 Op.getOperand(2), // LHS
5967 Op.getOperand(3), // RHS
Owen Anderson9f944592009-08-11 20:47:22 +00005968 DAG.getConstant(CompareOpc, MVT::i32)
Chris Lattnerd66f14e2006-08-11 17:18:05 +00005969 };
Benjamin Kramerfdf362b2013-03-07 20:33:29 +00005970 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
Craig Topper48d114b2014-04-26 18:35:24 +00005971 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
Scott Michelcf0da6c2009-02-17 22:15:04 +00005972
Chris Lattner4211ca92006-04-14 06:01:58 +00005973 // Now that we have the comparison, emit a copy from the CR to a GPR.
5974 // This is flagged to the above dot comparison.
Ulrich Weigandd5ebc622013-07-03 17:05:42 +00005975 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
Owen Anderson9f944592009-08-11 20:47:22 +00005976 DAG.getRegister(PPC::CR6, MVT::i32),
Scott Michelcf0da6c2009-02-17 22:15:04 +00005977 CompNode.getValue(1));
5978
Chris Lattner4211ca92006-04-14 06:01:58 +00005979 // Unpack the result based on how the target uses it.
5980 unsigned BitNo; // Bit # of CR6.
5981 bool InvertBit; // Invert result?
Dan Gohmaneffb8942008-09-12 16:56:44 +00005982 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
Chris Lattner4211ca92006-04-14 06:01:58 +00005983 default: // Can't happen, don't crash on invalid number though.
5984 case 0: // Return the value of the EQ bit of CR6.
5985 BitNo = 0; InvertBit = false;
5986 break;
5987 case 1: // Return the inverted value of the EQ bit of CR6.
5988 BitNo = 0; InvertBit = true;
5989 break;
5990 case 2: // Return the value of the LT bit of CR6.
5991 BitNo = 2; InvertBit = false;
5992 break;
5993 case 3: // Return the inverted value of the LT bit of CR6.
5994 BitNo = 2; InvertBit = true;
5995 break;
5996 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00005997
Chris Lattner4211ca92006-04-14 06:01:58 +00005998 // Shift the bit into the low position.
Owen Anderson9f944592009-08-11 20:47:22 +00005999 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6000 DAG.getConstant(8-(3-BitNo), MVT::i32));
Chris Lattner4211ca92006-04-14 06:01:58 +00006001 // Isolate the bit.
Owen Anderson9f944592009-08-11 20:47:22 +00006002 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6003 DAG.getConstant(1, MVT::i32));
Scott Michelcf0da6c2009-02-17 22:15:04 +00006004
Chris Lattner4211ca92006-04-14 06:01:58 +00006005 // If we are supposed to, toggle the bit.
6006 if (InvertBit)
Owen Anderson9f944592009-08-11 20:47:22 +00006007 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6008 DAG.getConstant(1, MVT::i32));
Chris Lattner4211ca92006-04-14 06:01:58 +00006009 return Flags;
6010}
6011
Hal Finkel5c0d1452014-03-30 13:22:59 +00006012SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6013 SelectionDAG &DAG) const {
6014 SDLoc dl(Op);
6015 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6016 // instructions), but for smaller types, we need to first extend up to v2i32
6017 // before doing going farther.
6018 if (Op.getValueType() == MVT::v2i64) {
6019 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6020 if (ExtVT != MVT::v2i32) {
6021 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6022 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6023 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6024 ExtVT.getVectorElementType(), 4)));
6025 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6026 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6027 DAG.getValueType(MVT::v2i32));
6028 }
6029
6030 return Op;
6031 }
6032
6033 return SDValue();
6034}
6035
Scott Michelcf0da6c2009-02-17 22:15:04 +00006036SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
Dan Gohman21cea8a2010-04-17 15:26:15 +00006037 SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00006038 SDLoc dl(Op);
Chris Lattner4211ca92006-04-14 06:01:58 +00006039 // Create a stack slot that is 16-byte aligned.
6040 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
David Greene1fbe0542009-11-12 20:49:22 +00006041 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
Dale Johannesen81bfca72010-05-03 22:59:34 +00006042 EVT PtrVT = getPointerTy();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00006043 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006044
Chris Lattner4211ca92006-04-14 06:01:58 +00006045 // Store the input value into Value#0 of the stack slot.
Dale Johannesen021052a2009-02-04 20:06:27 +00006046 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
Chris Lattner676c61d2010-09-21 18:41:36 +00006047 Op.getOperand(0), FIdx, MachinePointerInfo(),
David Greene87a5abe2010-02-15 16:56:53 +00006048 false, false, 0);
Chris Lattner4211ca92006-04-14 06:01:58 +00006049 // Load it out.
Chris Lattner7727d052010-09-21 06:44:06 +00006050 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00006051 false, false, false, 0);
Chris Lattner4211ca92006-04-14 06:01:58 +00006052}
6053
Dan Gohman21cea8a2010-04-17 15:26:15 +00006054SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00006055 SDLoc dl(Op);
Owen Anderson9f944592009-08-11 20:47:22 +00006056 if (Op.getValueType() == MVT::v4i32) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00006057 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006058
Owen Anderson9f944592009-08-11 20:47:22 +00006059 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6060 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
Scott Michelcf0da6c2009-02-17 22:15:04 +00006061
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00006062 SDValue RHSSwap = // = vrlw RHS, 16
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00006063 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006064
Chris Lattner7e4398742006-04-18 03:43:48 +00006065 // Shrinkify inputs to v8i16.
Wesley Peck527da1b2010-11-23 03:31:01 +00006066 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6067 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6068 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006069
Chris Lattner7e4398742006-04-18 03:43:48 +00006070 // Low parts multiplied together, generating 32-bit results (we ignore the
6071 // top parts).
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00006072 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
Owen Anderson9f944592009-08-11 20:47:22 +00006073 LHS, RHS, DAG, dl, MVT::v4i32);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006074
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00006075 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
Owen Anderson9f944592009-08-11 20:47:22 +00006076 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
Chris Lattner7e4398742006-04-18 03:43:48 +00006077 // Shift the high parts up 16 bits.
Scott Michelcf0da6c2009-02-17 22:15:04 +00006078 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00006079 Neg16, DAG, dl);
Owen Anderson9f944592009-08-11 20:47:22 +00006080 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6081 } else if (Op.getValueType() == MVT::v8i16) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00006082 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006083
Owen Anderson9f944592009-08-11 20:47:22 +00006084 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
Chris Lattner7e4398742006-04-18 03:43:48 +00006085
Chris Lattner96d50482006-04-18 04:28:57 +00006086 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
Dale Johannesen9f3f72f2009-02-06 01:31:28 +00006087 LHS, RHS, Zero, DAG, dl);
Owen Anderson9f944592009-08-11 20:47:22 +00006088 } else if (Op.getValueType() == MVT::v16i8) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00006089 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006090 bool isLittleEndian = Subtarget.isLittleEndian();
Scott Michelcf0da6c2009-02-17 22:15:04 +00006091
Chris Lattnerd6d82aa2006-04-18 03:57:35 +00006092 // Multiply the even 8-bit parts, producing 16-bit sums.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00006093 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
Owen Anderson9f944592009-08-11 20:47:22 +00006094 LHS, RHS, DAG, dl, MVT::v8i16);
Wesley Peck527da1b2010-11-23 03:31:01 +00006095 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006096
Chris Lattnerd6d82aa2006-04-18 03:57:35 +00006097 // Multiply the odd 8-bit parts, producing 16-bit sums.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00006098 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
Owen Anderson9f944592009-08-11 20:47:22 +00006099 LHS, RHS, DAG, dl, MVT::v8i16);
Wesley Peck527da1b2010-11-23 03:31:01 +00006100 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006101
Bill Schmidt42995e82014-06-09 16:06:29 +00006102 // Merge the results together. Because vmuleub and vmuloub are
6103 // instructions with a big-endian bias, we must reverse the
6104 // element numbering and reverse the meaning of "odd" and "even"
6105 // when generating little endian code.
Nate Begeman8d6d4b92009-04-27 18:41:29 +00006106 int Ops[16];
Chris Lattnerd6d82aa2006-04-18 03:57:35 +00006107 for (unsigned i = 0; i != 8; ++i) {
Bill Schmidt42995e82014-06-09 16:06:29 +00006108 if (isLittleEndian) {
6109 Ops[i*2 ] = 2*i;
6110 Ops[i*2+1] = 2*i+16;
6111 } else {
6112 Ops[i*2 ] = 2*i+1;
6113 Ops[i*2+1] = 2*i+1+16;
6114 }
Chris Lattnerd6d82aa2006-04-18 03:57:35 +00006115 }
Bill Schmidt42995e82014-06-09 16:06:29 +00006116 if (isLittleEndian)
6117 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6118 else
6119 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
Chris Lattner7e4398742006-04-18 03:43:48 +00006120 } else {
Torok Edwinfbcc6632009-07-14 16:55:14 +00006121 llvm_unreachable("Unknown mul to lower!");
Chris Lattner7e4398742006-04-18 03:43:48 +00006122 }
Chris Lattnera2cae1b2006-04-18 03:24:30 +00006123}
6124
Chris Lattnerf3d06c62005-08-26 00:52:45 +00006125/// LowerOperation - Provide custom lowering hooks for some operations.
6126///
Dan Gohman21cea8a2010-04-17 15:26:15 +00006127SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Chris Lattnerf3d06c62005-08-26 00:52:45 +00006128 switch (Op.getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00006129 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
Chris Lattner4211ca92006-04-14 06:01:58 +00006130 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
Bob Wilsonf84f7102009-11-04 21:31:18 +00006131 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
Chris Lattner4211ca92006-04-14 06:01:58 +00006132 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Roman Divackye3f15c982012-06-04 17:36:38 +00006133 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
Nate Begeman4ca2ea52006-04-22 18:53:45 +00006134 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Chris Lattner4211ca92006-04-14 06:01:58 +00006135 case ISD::SETCC: return LowerSETCC(Op, DAG);
Duncan Sandsa0984362011-09-06 13:37:06 +00006136 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6137 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006138 case ISD::VASTART:
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006139 return LowerVASTART(Op, DAG, Subtarget);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006140
6141 case ISD::VAARG:
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006142 return LowerVAARG(Op, DAG, Subtarget);
Nicolas Geoffray23710a72007-04-03 13:59:52 +00006143
Roman Divackyc3825df2013-07-25 21:36:47 +00006144 case ISD::VACOPY:
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006145 return LowerVACOPY(Op, DAG, Subtarget);
Roman Divackyc3825df2013-07-25 21:36:47 +00006146
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006147 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
Chris Lattner43df5b32007-02-25 05:34:32 +00006148 case ISD::DYNAMIC_STACKALLOC:
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006149 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
Evan Cheng51096af2008-04-19 01:30:48 +00006150
Hal Finkel756810f2013-03-21 21:37:52 +00006151 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6152 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6153
Hal Finkel940ab932014-02-28 00:27:01 +00006154 case ISD::LOAD: return LowerLOAD(Op, DAG);
6155 case ISD::STORE: return LowerSTORE(Op, DAG);
6156 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
Chris Lattner4211ca92006-04-14 06:01:58 +00006157 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
Dale Johannesen37bc85f2009-06-04 20:53:52 +00006158 case ISD::FP_TO_UINT:
6159 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +00006160 SDLoc(Op));
Hal Finkelf6d45f22013-04-01 17:52:07 +00006161 case ISD::UINT_TO_FP:
6162 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
Dan Gohman9ba4d762008-01-31 00:41:03 +00006163 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
Chris Lattner4a66d692006-03-22 05:30:33 +00006164
Chris Lattner4211ca92006-04-14 06:01:58 +00006165 // Lower 64-bit shifts.
Chris Lattner601b8652006-09-20 03:47:40 +00006166 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6167 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6168 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
Chris Lattner4a66d692006-03-22 05:30:33 +00006169
Chris Lattner4211ca92006-04-14 06:01:58 +00006170 // Vector-related lowering.
6171 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6172 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6173 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6174 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
Hal Finkel5c0d1452014-03-30 13:22:59 +00006175 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
Chris Lattnera2cae1b2006-04-18 03:24:30 +00006176 case ISD::MUL: return LowerMUL(Op, DAG);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006177
Hal Finkel25c19922013-05-15 21:37:41 +00006178 // For counter-based loop handling.
6179 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6180
Chris Lattnerf6a81562007-12-08 06:59:59 +00006181 // Frame & Return address.
6182 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
Nicolas Geoffray75ab9792007-03-01 13:11:38 +00006183 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Chris Lattnere675a082005-08-31 20:23:54 +00006184 }
Chris Lattnerf3d06c62005-08-26 00:52:45 +00006185}
6186
Duncan Sands6ed40142008-12-01 11:39:25 +00006187void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6188 SmallVectorImpl<SDValue>&Results,
Dan Gohman21cea8a2010-04-17 15:26:15 +00006189 SelectionDAG &DAG) const {
Roman Divacky4394e682011-06-28 15:30:42 +00006190 const TargetMachine &TM = getTargetMachine();
Andrew Trickef9de2a2013-05-25 02:42:55 +00006191 SDLoc dl(N);
Chris Lattner57ee7c62007-11-28 18:44:47 +00006192 switch (N->getOpcode()) {
Duncan Sands4068a7f2008-10-28 15:00:32 +00006193 default:
Craig Toppere55c5562012-02-07 02:50:20 +00006194 llvm_unreachable("Do not know how to custom type legalize this operation!");
Hal Finkel25c19922013-05-15 21:37:41 +00006195 case ISD::INTRINSIC_W_CHAIN: {
6196 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6197 Intrinsic::ppc_is_decremented_ctr_nonzero)
6198 break;
6199
6200 assert(N->getValueType(0) == MVT::i1 &&
6201 "Unexpected result type for CTR decrement intrinsic");
Matt Arsenault758659232013-05-18 00:21:46 +00006202 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
Hal Finkel25c19922013-05-15 21:37:41 +00006203 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6204 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6205 N->getOperand(1));
6206
6207 Results.push_back(NewInt);
6208 Results.push_back(NewInt.getValue(1));
6209 break;
6210 }
Roman Divacky4394e682011-06-28 15:30:42 +00006211 case ISD::VAARG: {
6212 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6213 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6214 return;
6215
6216 EVT VT = N->getValueType(0);
6217
6218 if (VT == MVT::i64) {
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006219 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
Roman Divacky4394e682011-06-28 15:30:42 +00006220
6221 Results.push_back(NewNode);
6222 Results.push_back(NewNode.getValue(1));
6223 }
6224 return;
6225 }
Duncan Sands6ed40142008-12-01 11:39:25 +00006226 case ISD::FP_ROUND_INREG: {
Owen Anderson9f944592009-08-11 20:47:22 +00006227 assert(N->getValueType(0) == MVT::ppcf128);
6228 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006229 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
Owen Anderson9f944592009-08-11 20:47:22 +00006230 MVT::f64, N->getOperand(0),
Duncan Sands6ed40142008-12-01 11:39:25 +00006231 DAG.getIntPtrConstant(0));
Dale Johannesenf80493b2009-02-05 22:07:54 +00006232 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
Owen Anderson9f944592009-08-11 20:47:22 +00006233 MVT::f64, N->getOperand(0),
Duncan Sands6ed40142008-12-01 11:39:25 +00006234 DAG.getIntPtrConstant(1));
6235
Ulrich Weigand874fc622013-03-26 10:56:22 +00006236 // Add the two halves of the long double in round-to-zero mode.
6237 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
Duncan Sands6ed40142008-12-01 11:39:25 +00006238
6239 // We know the low half is about to be thrown away, so just use something
6240 // convenient.
Owen Anderson9f944592009-08-11 20:47:22 +00006241 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
Dale Johannesenf80493b2009-02-05 22:07:54 +00006242 FPreg, FPreg));
Duncan Sands6ed40142008-12-01 11:39:25 +00006243 return;
Duncan Sands2a287912008-07-19 16:26:02 +00006244 }
Duncan Sands6ed40142008-12-01 11:39:25 +00006245 case ISD::FP_TO_SINT:
Bill Schmidt41221692013-07-09 18:50:20 +00006246 // LowerFP_TO_INT() can only handle f32 and f64.
6247 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6248 return;
Dale Johannesen37bc85f2009-06-04 20:53:52 +00006249 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
Duncan Sands6ed40142008-12-01 11:39:25 +00006250 return;
Chris Lattner57ee7c62007-11-28 18:44:47 +00006251 }
6252}
6253
6254
Chris Lattner4211ca92006-04-14 06:01:58 +00006255//===----------------------------------------------------------------------===//
6256// Other Lowering Code
6257//===----------------------------------------------------------------------===//
6258
Chris Lattner9b577f12005-08-26 21:23:58 +00006259MachineBasicBlock *
Dale Johannesend4eb0522008-08-25 22:34:37 +00006260PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
Dan Gohman747e55b2009-02-07 16:15:20 +00006261 bool is64bit, unsigned BinOpcode) const {
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006262 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
Dale Johannesend4eb0522008-08-25 22:34:37 +00006263 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6264
6265 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6266 MachineFunction *F = BB->getParent();
6267 MachineFunction::iterator It = BB;
6268 ++It;
6269
6270 unsigned dest = MI->getOperand(0).getReg();
6271 unsigned ptrA = MI->getOperand(1).getReg();
6272 unsigned ptrB = MI->getOperand(2).getReg();
6273 unsigned incr = MI->getOperand(3).getReg();
Dale Johannesene9f623e2009-02-13 02:27:39 +00006274 DebugLoc dl = MI->getDebugLoc();
Dale Johannesend4eb0522008-08-25 22:34:37 +00006275
6276 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6277 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6278 F->insert(It, loopMBB);
6279 F->insert(It, exitMBB);
Dan Gohman34396292010-07-06 20:24:04 +00006280 exitMBB->splice(exitMBB->begin(), BB,
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00006281 std::next(MachineBasicBlock::iterator(MI)), BB->end());
Dan Gohman34396292010-07-06 20:24:04 +00006282 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
Dale Johannesend4eb0522008-08-25 22:34:37 +00006283
6284 MachineRegisterInfo &RegInfo = F->getRegInfo();
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006285 unsigned TmpReg = (!BinOpcode) ? incr :
6286 RegInfo.createVirtualRegister(
Dale Johannesenbc698292008-09-02 20:30:23 +00006287 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6288 (const TargetRegisterClass *) &PPC::GPRCRegClass);
Dale Johannesend4eb0522008-08-25 22:34:37 +00006289
6290 // thisMBB:
6291 // ...
6292 // fallthrough --> loopMBB
6293 BB->addSuccessor(loopMBB);
6294
6295 // loopMBB:
6296 // l[wd]arx dest, ptr
6297 // add r0, dest, incr
6298 // st[wd]cx. r0, ptr
6299 // bne- loopMBB
6300 // fallthrough --> exitMBB
6301 BB = loopMBB;
Dale Johannesene9f623e2009-02-13 02:27:39 +00006302 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
Dale Johannesend4eb0522008-08-25 22:34:37 +00006303 .addReg(ptrA).addReg(ptrB);
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006304 if (BinOpcode)
Dale Johannesene9f623e2009-02-13 02:27:39 +00006305 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6306 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
Dale Johannesend4eb0522008-08-25 22:34:37 +00006307 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006308 BuildMI(BB, dl, TII->get(PPC::BCC))
Scott Michelcf0da6c2009-02-17 22:15:04 +00006309 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
Dale Johannesend4eb0522008-08-25 22:34:37 +00006310 BB->addSuccessor(loopMBB);
6311 BB->addSuccessor(exitMBB);
6312
6313 // exitMBB:
6314 // ...
6315 BB = exitMBB;
6316 return BB;
6317}
6318
6319MachineBasicBlock *
Scott Michelcf0da6c2009-02-17 22:15:04 +00006320PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
Dale Johannesena32affb2008-08-28 17:53:09 +00006321 MachineBasicBlock *BB,
6322 bool is8bit, // operation
Dan Gohman747e55b2009-02-07 16:15:20 +00006323 unsigned BinOpcode) const {
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006324 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
Dale Johannesena32affb2008-08-28 17:53:09 +00006325 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6326 // In 64 bit mode we have to use 64 bits for addresses, even though the
6327 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6328 // registers without caring whether they're 32 or 64, but here we're
6329 // doing actual arithmetic on the addresses.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006330 bool is64bit = Subtarget.isPPC64();
Hal Finkelf70c41e2013-03-21 23:45:03 +00006331 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
Dale Johannesena32affb2008-08-28 17:53:09 +00006332
6333 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6334 MachineFunction *F = BB->getParent();
6335 MachineFunction::iterator It = BB;
6336 ++It;
6337
6338 unsigned dest = MI->getOperand(0).getReg();
6339 unsigned ptrA = MI->getOperand(1).getReg();
6340 unsigned ptrB = MI->getOperand(2).getReg();
6341 unsigned incr = MI->getOperand(3).getReg();
Dale Johannesene9f623e2009-02-13 02:27:39 +00006342 DebugLoc dl = MI->getDebugLoc();
Dale Johannesena32affb2008-08-28 17:53:09 +00006343
6344 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6345 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6346 F->insert(It, loopMBB);
6347 F->insert(It, exitMBB);
Dan Gohman34396292010-07-06 20:24:04 +00006348 exitMBB->splice(exitMBB->begin(), BB,
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00006349 std::next(MachineBasicBlock::iterator(MI)), BB->end());
Dan Gohman34396292010-07-06 20:24:04 +00006350 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
Dale Johannesena32affb2008-08-28 17:53:09 +00006351
6352 MachineRegisterInfo &RegInfo = F->getRegInfo();
Scott Michelcf0da6c2009-02-17 22:15:04 +00006353 const TargetRegisterClass *RC =
Dale Johannesenbc698292008-09-02 20:30:23 +00006354 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6355 (const TargetRegisterClass *) &PPC::GPRCRegClass;
Dale Johannesena32affb2008-08-28 17:53:09 +00006356 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6357 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6358 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6359 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6360 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6361 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6362 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6363 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6364 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6365 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006366 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
Dale Johannesena32affb2008-08-28 17:53:09 +00006367 unsigned Ptr1Reg;
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006368 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
Dale Johannesena32affb2008-08-28 17:53:09 +00006369
6370 // thisMBB:
6371 // ...
6372 // fallthrough --> loopMBB
6373 BB->addSuccessor(loopMBB);
6374
6375 // The 4-byte load must be aligned, while a char or short may be
6376 // anywhere in the word. Hence all this nasty bookkeeping code.
6377 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6378 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
Dale Johannesenbc698292008-09-02 20:30:23 +00006379 // xori shift, shift1, 24 [16]
Dale Johannesena32affb2008-08-28 17:53:09 +00006380 // rlwinm ptr, ptr1, 0, 0, 29
6381 // slw incr2, incr, shift
6382 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6383 // slw mask, mask2, shift
6384 // loopMBB:
Dale Johannesen340d2642008-08-30 00:08:53 +00006385 // lwarx tmpDest, ptr
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006386 // add tmp, tmpDest, incr2
6387 // andc tmp2, tmpDest, mask
Dale Johannesena32affb2008-08-28 17:53:09 +00006388 // and tmp3, tmp, mask
6389 // or tmp4, tmp3, tmp2
Dale Johannesen340d2642008-08-30 00:08:53 +00006390 // stwcx. tmp4, ptr
Dale Johannesena32affb2008-08-28 17:53:09 +00006391 // bne- loopMBB
6392 // fallthrough --> exitMBB
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006393 // srw dest, tmpDest, shift
Jakob Stoklund Olesen7067bff2011-04-04 17:07:06 +00006394 if (ptrA != ZeroReg) {
Dale Johannesena32affb2008-08-28 17:53:09 +00006395 Ptr1Reg = RegInfo.createVirtualRegister(RC);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006396 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
Dale Johannesena32affb2008-08-28 17:53:09 +00006397 .addReg(ptrA).addReg(ptrB);
6398 } else {
6399 Ptr1Reg = ptrB;
6400 }
Dale Johannesene9f623e2009-02-13 02:27:39 +00006401 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
Dale Johannesena32affb2008-08-28 17:53:09 +00006402 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006403 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
Dale Johannesena32affb2008-08-28 17:53:09 +00006404 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6405 if (is64bit)
Dale Johannesene9f623e2009-02-13 02:27:39 +00006406 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
Dale Johannesena32affb2008-08-28 17:53:09 +00006407 .addReg(Ptr1Reg).addImm(0).addImm(61);
6408 else
Dale Johannesene9f623e2009-02-13 02:27:39 +00006409 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
Dale Johannesena32affb2008-08-28 17:53:09 +00006410 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006411 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
Dale Johannesena32affb2008-08-28 17:53:09 +00006412 .addReg(incr).addReg(ShiftReg);
6413 if (is8bit)
Dale Johannesene9f623e2009-02-13 02:27:39 +00006414 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
Dale Johannesena32affb2008-08-28 17:53:09 +00006415 else {
Dale Johannesene9f623e2009-02-13 02:27:39 +00006416 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6417 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
Dale Johannesena32affb2008-08-28 17:53:09 +00006418 }
Dale Johannesene9f623e2009-02-13 02:27:39 +00006419 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
Dale Johannesena32affb2008-08-28 17:53:09 +00006420 .addReg(Mask2Reg).addReg(ShiftReg);
6421
6422 BB = loopMBB;
Dale Johannesene9f623e2009-02-13 02:27:39 +00006423 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
Jakob Stoklund Olesen7067bff2011-04-04 17:07:06 +00006424 .addReg(ZeroReg).addReg(PtrReg);
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006425 if (BinOpcode)
Dale Johannesene9f623e2009-02-13 02:27:39 +00006426 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006427 .addReg(Incr2Reg).addReg(TmpDestReg);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006428 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006429 .addReg(TmpDestReg).addReg(MaskReg);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006430 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
Dale Johannesena32affb2008-08-28 17:53:09 +00006431 .addReg(TmpReg).addReg(MaskReg);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006432 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
Dale Johannesena32affb2008-08-28 17:53:09 +00006433 .addReg(Tmp3Reg).addReg(Tmp2Reg);
Bill Schmidt3581cd42013-04-02 18:37:08 +00006434 BuildMI(BB, dl, TII->get(PPC::STWCX))
Jakob Stoklund Olesen7067bff2011-04-04 17:07:06 +00006435 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006436 BuildMI(BB, dl, TII->get(PPC::BCC))
Scott Michelcf0da6c2009-02-17 22:15:04 +00006437 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
Dale Johannesena32affb2008-08-28 17:53:09 +00006438 BB->addSuccessor(loopMBB);
6439 BB->addSuccessor(exitMBB);
6440
6441 // exitMBB:
6442 // ...
6443 BB = exitMBB;
Jakob Stoklund Olesen13ce2362011-04-04 17:57:29 +00006444 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6445 .addReg(ShiftReg);
Dale Johannesena32affb2008-08-28 17:53:09 +00006446 return BB;
6447}
6448
Hal Finkel756810f2013-03-21 21:37:52 +00006449llvm::MachineBasicBlock*
6450PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6451 MachineBasicBlock *MBB) const {
6452 DebugLoc DL = MI->getDebugLoc();
6453 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6454
6455 MachineFunction *MF = MBB->getParent();
6456 MachineRegisterInfo &MRI = MF->getRegInfo();
6457
6458 const BasicBlock *BB = MBB->getBasicBlock();
6459 MachineFunction::iterator I = MBB;
6460 ++I;
6461
6462 // Memory Reference
6463 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6464 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6465
6466 unsigned DstReg = MI->getOperand(0).getReg();
6467 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6468 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6469 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6470 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6471
6472 MVT PVT = getPointerTy();
6473 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6474 "Invalid Pointer Size!");
6475 // For v = setjmp(buf), we generate
6476 //
6477 // thisMBB:
6478 // SjLjSetup mainMBB
6479 // bl mainMBB
6480 // v_restore = 1
6481 // b sinkMBB
6482 //
6483 // mainMBB:
6484 // buf[LabelOffset] = LR
6485 // v_main = 0
6486 //
6487 // sinkMBB:
6488 // v = phi(main, restore)
6489 //
6490
6491 MachineBasicBlock *thisMBB = MBB;
6492 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6493 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6494 MF->insert(I, mainMBB);
6495 MF->insert(I, sinkMBB);
6496
6497 MachineInstrBuilder MIB;
6498
6499 // Transfer the remainder of BB and its successor edges to sinkMBB.
6500 sinkMBB->splice(sinkMBB->begin(), MBB,
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00006501 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
Hal Finkel756810f2013-03-21 21:37:52 +00006502 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6503
6504 // Note that the structure of the jmp_buf used here is not compatible
6505 // with that used by libc, and is not designed to be. Specifically, it
6506 // stores only those 'reserved' registers that LLVM does not otherwise
6507 // understand how to spill. Also, by convention, by the time this
6508 // intrinsic is called, Clang has already stored the frame address in the
6509 // first slot of the buffer and stack address in the third. Following the
6510 // X86 target code, we'll store the jump address in the second slot. We also
6511 // need to save the TOC pointer (R2) to handle jumps between shared
6512 // libraries, and that will be stored in the fourth slot. The thread
6513 // identifier (R13) is not affected.
6514
6515 // thisMBB:
6516 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6517 const int64_t TOCOffset = 3 * PVT.getStoreSize();
Hal Finkelf05d6c72013-07-17 23:50:51 +00006518 const int64_t BPOffset = 4 * PVT.getStoreSize();
Hal Finkel756810f2013-03-21 21:37:52 +00006519
6520 // Prepare IP either in reg.
6521 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6522 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6523 unsigned BufReg = MI->getOperand(1).getReg();
6524
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006525 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
Hal Finkel756810f2013-03-21 21:37:52 +00006526 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6527 .addReg(PPC::X2)
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00006528 .addImm(TOCOffset)
Hal Finkel756810f2013-03-21 21:37:52 +00006529 .addReg(BufReg);
Hal Finkel756810f2013-03-21 21:37:52 +00006530 MIB.setMemRefs(MMOBegin, MMOEnd);
6531 }
6532
Hal Finkelf05d6c72013-07-17 23:50:51 +00006533 // Naked functions never have a base pointer, and so we use r1. For all
6534 // other functions, this decision must be delayed until during PEI.
6535 unsigned BaseReg;
6536 if (MF->getFunction()->getAttributes().hasAttribute(
6537 AttributeSet::FunctionIndex, Attribute::Naked))
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006538 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
Hal Finkelf05d6c72013-07-17 23:50:51 +00006539 else
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006540 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
Hal Finkelf05d6c72013-07-17 23:50:51 +00006541
6542 MIB = BuildMI(*thisMBB, MI, DL,
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006543 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
Hal Finkelf05d6c72013-07-17 23:50:51 +00006544 .addReg(BaseReg)
6545 .addImm(BPOffset)
6546 .addReg(BufReg);
6547 MIB.setMemRefs(MMOBegin, MMOEnd);
6548
Hal Finkel756810f2013-03-21 21:37:52 +00006549 // Setup
Hal Finkele5680b32013-04-04 22:55:54 +00006550 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
Bill Wendling5e7656b2013-06-07 07:55:53 +00006551 const PPCRegisterInfo *TRI =
6552 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6553 MIB.addRegMask(TRI->getNoPreservedMask());
Hal Finkel756810f2013-03-21 21:37:52 +00006554
6555 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6556
6557 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6558 .addMBB(mainMBB);
6559 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6560
6561 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6562 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6563
6564 // mainMBB:
6565 // mainDstReg = 0
6566 MIB = BuildMI(mainMBB, DL,
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006567 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
Hal Finkel756810f2013-03-21 21:37:52 +00006568
6569 // Store IP
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006570 if (Subtarget.isPPC64()) {
Hal Finkel756810f2013-03-21 21:37:52 +00006571 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6572 .addReg(LabelReg)
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00006573 .addImm(LabelOffset)
Hal Finkel756810f2013-03-21 21:37:52 +00006574 .addReg(BufReg);
6575 } else {
6576 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6577 .addReg(LabelReg)
6578 .addImm(LabelOffset)
6579 .addReg(BufReg);
6580 }
6581
6582 MIB.setMemRefs(MMOBegin, MMOEnd);
6583
6584 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6585 mainMBB->addSuccessor(sinkMBB);
6586
6587 // sinkMBB:
6588 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6589 TII->get(PPC::PHI), DstReg)
6590 .addReg(mainDstReg).addMBB(mainMBB)
6591 .addReg(restoreDstReg).addMBB(thisMBB);
6592
6593 MI->eraseFromParent();
6594 return sinkMBB;
6595}
6596
6597MachineBasicBlock *
6598PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6599 MachineBasicBlock *MBB) const {
6600 DebugLoc DL = MI->getDebugLoc();
6601 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6602
6603 MachineFunction *MF = MBB->getParent();
6604 MachineRegisterInfo &MRI = MF->getRegInfo();
6605
6606 // Memory Reference
6607 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6608 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6609
6610 MVT PVT = getPointerTy();
6611 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6612 "Invalid Pointer Size!");
6613
6614 const TargetRegisterClass *RC =
6615 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6616 unsigned Tmp = MRI.createVirtualRegister(RC);
6617 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6618 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6619 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
Hal Finkelf05d6c72013-07-17 23:50:51 +00006620 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
Hal Finkel756810f2013-03-21 21:37:52 +00006621
6622 MachineInstrBuilder MIB;
6623
6624 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6625 const int64_t SPOffset = 2 * PVT.getStoreSize();
6626 const int64_t TOCOffset = 3 * PVT.getStoreSize();
Hal Finkelf05d6c72013-07-17 23:50:51 +00006627 const int64_t BPOffset = 4 * PVT.getStoreSize();
Hal Finkel756810f2013-03-21 21:37:52 +00006628
6629 unsigned BufReg = MI->getOperand(0).getReg();
6630
6631 // Reload FP (the jumped-to function may not have had a
6632 // frame pointer, and if so, then its r31 will be restored
6633 // as necessary).
6634 if (PVT == MVT::i64) {
6635 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6636 .addImm(0)
6637 .addReg(BufReg);
6638 } else {
6639 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6640 .addImm(0)
6641 .addReg(BufReg);
6642 }
6643 MIB.setMemRefs(MMOBegin, MMOEnd);
6644
6645 // Reload IP
6646 if (PVT == MVT::i64) {
6647 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00006648 .addImm(LabelOffset)
Hal Finkel756810f2013-03-21 21:37:52 +00006649 .addReg(BufReg);
6650 } else {
6651 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6652 .addImm(LabelOffset)
6653 .addReg(BufReg);
6654 }
6655 MIB.setMemRefs(MMOBegin, MMOEnd);
6656
6657 // Reload SP
6658 if (PVT == MVT::i64) {
6659 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00006660 .addImm(SPOffset)
Hal Finkel756810f2013-03-21 21:37:52 +00006661 .addReg(BufReg);
6662 } else {
6663 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6664 .addImm(SPOffset)
6665 .addReg(BufReg);
6666 }
6667 MIB.setMemRefs(MMOBegin, MMOEnd);
6668
Hal Finkelf05d6c72013-07-17 23:50:51 +00006669 // Reload BP
6670 if (PVT == MVT::i64) {
6671 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6672 .addImm(BPOffset)
6673 .addReg(BufReg);
6674 } else {
6675 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6676 .addImm(BPOffset)
6677 .addReg(BufReg);
6678 }
6679 MIB.setMemRefs(MMOBegin, MMOEnd);
Hal Finkel756810f2013-03-21 21:37:52 +00006680
6681 // Reload TOC
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006682 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
Hal Finkel756810f2013-03-21 21:37:52 +00006683 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
Ulrich Weigand9d980cb2013-05-16 17:58:02 +00006684 .addImm(TOCOffset)
Hal Finkel756810f2013-03-21 21:37:52 +00006685 .addReg(BufReg);
6686
6687 MIB.setMemRefs(MMOBegin, MMOEnd);
6688 }
6689
6690 // Jump
6691 BuildMI(*MBB, MI, DL,
6692 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6693 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6694
6695 MI->eraseFromParent();
6696 return MBB;
6697}
6698
Dale Johannesena32affb2008-08-28 17:53:09 +00006699MachineBasicBlock *
Evan Cheng29cfb672008-01-30 18:18:23 +00006700PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohman25c16532010-05-01 00:01:06 +00006701 MachineBasicBlock *BB) const {
Hal Finkel756810f2013-03-21 21:37:52 +00006702 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6703 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6704 return emitEHSjLjSetJmp(MI, BB);
6705 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6706 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6707 return emitEHSjLjLongJmp(MI, BB);
6708 }
6709
Evan Cheng20350c42006-11-27 23:37:22 +00006710 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Evan Cheng32e376f2008-07-12 02:23:19 +00006711
6712 // To "insert" these instructions we actually have to insert their
6713 // control-flow patterns.
Chris Lattner9b577f12005-08-26 21:23:58 +00006714 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Dan Gohman3b460302008-07-07 23:14:23 +00006715 MachineFunction::iterator It = BB;
Chris Lattner9b577f12005-08-26 21:23:58 +00006716 ++It;
Evan Cheng32e376f2008-07-12 02:23:19 +00006717
Dan Gohman3b460302008-07-07 23:14:23 +00006718 MachineFunction *F = BB->getParent();
Evan Cheng32e376f2008-07-12 02:23:19 +00006719
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006720 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
Hal Finkel940ab932014-02-28 00:27:01 +00006721 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6722 MI->getOpcode() == PPC::SELECT_I4 ||
6723 MI->getOpcode() == PPC::SELECT_I8)) {
Hal Finkeled6a2852013-04-05 23:29:01 +00006724 SmallVector<MachineOperand, 2> Cond;
Hal Finkel940ab932014-02-28 00:27:01 +00006725 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6726 MI->getOpcode() == PPC::SELECT_CC_I8)
6727 Cond.push_back(MI->getOperand(4));
6728 else
6729 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
Hal Finkeled6a2852013-04-05 23:29:01 +00006730 Cond.push_back(MI->getOperand(1));
6731
Hal Finkel460e94d2012-06-22 23:10:08 +00006732 DebugLoc dl = MI->getDebugLoc();
Bill Wendling5e7656b2013-06-07 07:55:53 +00006733 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6734 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6735 Cond, MI->getOperand(2).getReg(),
6736 MI->getOperand(3).getReg());
Hal Finkel460e94d2012-06-22 23:10:08 +00006737 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6738 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6739 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6740 MI->getOpcode() == PPC::SELECT_CC_F8 ||
Hal Finkel940ab932014-02-28 00:27:01 +00006741 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6742 MI->getOpcode() == PPC::SELECT_I4 ||
6743 MI->getOpcode() == PPC::SELECT_I8 ||
6744 MI->getOpcode() == PPC::SELECT_F4 ||
6745 MI->getOpcode() == PPC::SELECT_F8 ||
6746 MI->getOpcode() == PPC::SELECT_VRRC) {
Evan Cheng32e376f2008-07-12 02:23:19 +00006747 // The incoming instruction knows the destination vreg to set, the
6748 // condition code register to branch on, the true/false values to
6749 // select between, and a branch opcode to use.
6750
6751 // thisMBB:
6752 // ...
6753 // TrueVal = ...
6754 // cmpTY ccX, r1, r2
6755 // bCC copy1MBB
6756 // fallthrough --> copy0MBB
6757 MachineBasicBlock *thisMBB = BB;
6758 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6759 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006760 DebugLoc dl = MI->getDebugLoc();
Evan Cheng32e376f2008-07-12 02:23:19 +00006761 F->insert(It, copy0MBB);
6762 F->insert(It, sinkMBB);
Dan Gohman34396292010-07-06 20:24:04 +00006763
6764 // Transfer the remainder of BB and its successor edges to sinkMBB.
6765 sinkMBB->splice(sinkMBB->begin(), BB,
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00006766 std::next(MachineBasicBlock::iterator(MI)), BB->end());
Dan Gohman34396292010-07-06 20:24:04 +00006767 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6768
Evan Cheng32e376f2008-07-12 02:23:19 +00006769 // Next, add the true and fallthrough blocks as its successors.
6770 BB->addSuccessor(copy0MBB);
6771 BB->addSuccessor(sinkMBB);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006772
Hal Finkel940ab932014-02-28 00:27:01 +00006773 if (MI->getOpcode() == PPC::SELECT_I4 ||
6774 MI->getOpcode() == PPC::SELECT_I8 ||
6775 MI->getOpcode() == PPC::SELECT_F4 ||
6776 MI->getOpcode() == PPC::SELECT_F8 ||
6777 MI->getOpcode() == PPC::SELECT_VRRC) {
6778 BuildMI(BB, dl, TII->get(PPC::BC))
6779 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6780 } else {
6781 unsigned SelectPred = MI->getOperand(4).getImm();
6782 BuildMI(BB, dl, TII->get(PPC::BCC))
6783 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6784 }
Dan Gohman34396292010-07-06 20:24:04 +00006785
Evan Cheng32e376f2008-07-12 02:23:19 +00006786 // copy0MBB:
6787 // %FalseValue = ...
6788 // # fallthrough to sinkMBB
6789 BB = copy0MBB;
Scott Michelcf0da6c2009-02-17 22:15:04 +00006790
Evan Cheng32e376f2008-07-12 02:23:19 +00006791 // Update machine-CFG edges
6792 BB->addSuccessor(sinkMBB);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006793
Evan Cheng32e376f2008-07-12 02:23:19 +00006794 // sinkMBB:
6795 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6796 // ...
6797 BB = sinkMBB;
Dan Gohman34396292010-07-06 20:24:04 +00006798 BuildMI(*BB, BB->begin(), dl,
6799 TII->get(PPC::PHI), MI->getOperand(0).getReg())
Evan Cheng32e376f2008-07-12 02:23:19 +00006800 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6801 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6802 }
Dale Johannesena32affb2008-08-28 17:53:09 +00006803 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6804 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6805 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6806 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
Dale Johannesend4eb0522008-08-25 22:34:37 +00006807 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6808 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6809 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6810 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
Dale Johannesena32affb2008-08-28 17:53:09 +00006811
6812 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6813 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6814 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6815 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
Dale Johannesend4eb0522008-08-25 22:34:37 +00006816 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6817 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6818 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6819 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
Dale Johannesena32affb2008-08-28 17:53:09 +00006820
6821 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6822 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6823 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6824 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
Dale Johannesend4eb0522008-08-25 22:34:37 +00006825 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6826 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6827 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6828 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
Dale Johannesena32affb2008-08-28 17:53:09 +00006829
6830 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6831 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6832 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6833 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
Dale Johannesend4eb0522008-08-25 22:34:37 +00006834 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6835 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6836 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6837 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
Dale Johannesena32affb2008-08-28 17:53:09 +00006838
6839 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
Dale Johannesene5ca04e2008-09-11 02:15:03 +00006840 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
Dale Johannesena32affb2008-08-28 17:53:09 +00006841 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
Dale Johannesene5ca04e2008-09-11 02:15:03 +00006842 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
Dale Johannesend4eb0522008-08-25 22:34:37 +00006843 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
Dale Johannesene5ca04e2008-09-11 02:15:03 +00006844 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
Dale Johannesend4eb0522008-08-25 22:34:37 +00006845 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
Dale Johannesene5ca04e2008-09-11 02:15:03 +00006846 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
Dale Johannesena32affb2008-08-28 17:53:09 +00006847
6848 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6849 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6850 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6851 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
Dale Johannesend4eb0522008-08-25 22:34:37 +00006852 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6853 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6854 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6855 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
Dale Johannesena32affb2008-08-28 17:53:09 +00006856
Dale Johannesenf0a88d62008-08-29 18:29:46 +00006857 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6858 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6859 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6860 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6861 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6862 BB = EmitAtomicBinary(MI, BB, false, 0);
6863 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6864 BB = EmitAtomicBinary(MI, BB, true, 0);
6865
Evan Cheng32e376f2008-07-12 02:23:19 +00006866 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6867 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6868 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6869
6870 unsigned dest = MI->getOperand(0).getReg();
6871 unsigned ptrA = MI->getOperand(1).getReg();
6872 unsigned ptrB = MI->getOperand(2).getReg();
6873 unsigned oldval = MI->getOperand(3).getReg();
6874 unsigned newval = MI->getOperand(4).getReg();
Dale Johannesene9f623e2009-02-13 02:27:39 +00006875 DebugLoc dl = MI->getDebugLoc();
Evan Cheng32e376f2008-07-12 02:23:19 +00006876
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006877 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6878 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6879 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
Evan Cheng32e376f2008-07-12 02:23:19 +00006880 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006881 F->insert(It, loop1MBB);
6882 F->insert(It, loop2MBB);
6883 F->insert(It, midMBB);
Evan Cheng32e376f2008-07-12 02:23:19 +00006884 F->insert(It, exitMBB);
Dan Gohman34396292010-07-06 20:24:04 +00006885 exitMBB->splice(exitMBB->begin(), BB,
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00006886 std::next(MachineBasicBlock::iterator(MI)), BB->end());
Dan Gohman34396292010-07-06 20:24:04 +00006887 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
Evan Cheng32e376f2008-07-12 02:23:19 +00006888
6889 // thisMBB:
6890 // ...
6891 // fallthrough --> loopMBB
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006892 BB->addSuccessor(loop1MBB);
Evan Cheng32e376f2008-07-12 02:23:19 +00006893
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006894 // loop1MBB:
Evan Cheng32e376f2008-07-12 02:23:19 +00006895 // l[wd]arx dest, ptr
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006896 // cmp[wd] dest, oldval
6897 // bne- midMBB
6898 // loop2MBB:
Evan Cheng32e376f2008-07-12 02:23:19 +00006899 // st[wd]cx. newval, ptr
6900 // bne- loopMBB
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006901 // b exitBB
6902 // midMBB:
6903 // st[wd]cx. dest, ptr
6904 // exitBB:
6905 BB = loop1MBB;
Dale Johannesene9f623e2009-02-13 02:27:39 +00006906 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
Evan Cheng32e376f2008-07-12 02:23:19 +00006907 .addReg(ptrA).addReg(ptrB);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006908 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
Evan Cheng32e376f2008-07-12 02:23:19 +00006909 .addReg(oldval).addReg(dest);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006910 BuildMI(BB, dl, TII->get(PPC::BCC))
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006911 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6912 BB->addSuccessor(loop2MBB);
6913 BB->addSuccessor(midMBB);
6914
6915 BB = loop2MBB;
Dale Johannesene9f623e2009-02-13 02:27:39 +00006916 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
Evan Cheng32e376f2008-07-12 02:23:19 +00006917 .addReg(newval).addReg(ptrA).addReg(ptrB);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006918 BuildMI(BB, dl, TII->get(PPC::BCC))
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006919 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
Dale Johannesene9f623e2009-02-13 02:27:39 +00006920 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006921 BB->addSuccessor(loop1MBB);
Evan Cheng32e376f2008-07-12 02:23:19 +00006922 BB->addSuccessor(exitMBB);
Scott Michelcf0da6c2009-02-17 22:15:04 +00006923
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006924 BB = midMBB;
Dale Johannesene9f623e2009-02-13 02:27:39 +00006925 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
Dale Johannesen166d6cb2008-08-25 18:53:26 +00006926 .addReg(dest).addReg(ptrA).addReg(ptrB);
6927 BB->addSuccessor(exitMBB);
6928
Evan Cheng32e376f2008-07-12 02:23:19 +00006929 // exitMBB:
6930 // ...
6931 BB = exitMBB;
Dale Johannesen340d2642008-08-30 00:08:53 +00006932 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6933 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6934 // We must use 64-bit registers for addresses when targeting 64-bit,
6935 // since we're actually doing arithmetic on them. Other registers
6936 // can be 32-bit.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00006937 bool is64bit = Subtarget.isPPC64();
Dale Johannesen340d2642008-08-30 00:08:53 +00006938 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6939
6940 unsigned dest = MI->getOperand(0).getReg();
6941 unsigned ptrA = MI->getOperand(1).getReg();
6942 unsigned ptrB = MI->getOperand(2).getReg();
6943 unsigned oldval = MI->getOperand(3).getReg();
6944 unsigned newval = MI->getOperand(4).getReg();
Dale Johannesene9f623e2009-02-13 02:27:39 +00006945 DebugLoc dl = MI->getDebugLoc();
Dale Johannesen340d2642008-08-30 00:08:53 +00006946
6947 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6948 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6949 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6950 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6951 F->insert(It, loop1MBB);
6952 F->insert(It, loop2MBB);
6953 F->insert(It, midMBB);
6954 F->insert(It, exitMBB);
Dan Gohman34396292010-07-06 20:24:04 +00006955 exitMBB->splice(exitMBB->begin(), BB,
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00006956 std::next(MachineBasicBlock::iterator(MI)), BB->end());
Dan Gohman34396292010-07-06 20:24:04 +00006957 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
Dale Johannesen340d2642008-08-30 00:08:53 +00006958
6959 MachineRegisterInfo &RegInfo = F->getRegInfo();
Scott Michelcf0da6c2009-02-17 22:15:04 +00006960 const TargetRegisterClass *RC =
Dale Johannesenbc698292008-09-02 20:30:23 +00006961 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6962 (const TargetRegisterClass *) &PPC::GPRCRegClass;
Dale Johannesen340d2642008-08-30 00:08:53 +00006963 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6964 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6965 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6966 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6967 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6968 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6969 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6970 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6971 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6972 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6973 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6974 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6975 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6976 unsigned Ptr1Reg;
6977 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
Hal Finkelf70c41e2013-03-21 23:45:03 +00006978 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
Dale Johannesen340d2642008-08-30 00:08:53 +00006979 // thisMBB:
6980 // ...
6981 // fallthrough --> loopMBB
6982 BB->addSuccessor(loop1MBB);
6983
6984 // The 4-byte load must be aligned, while a char or short may be
6985 // anywhere in the word. Hence all this nasty bookkeeping code.
6986 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6987 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
Dale Johannesenbc698292008-09-02 20:30:23 +00006988 // xori shift, shift1, 24 [16]
Dale Johannesen340d2642008-08-30 00:08:53 +00006989 // rlwinm ptr, ptr1, 0, 0, 29
6990 // slw newval2, newval, shift
6991 // slw oldval2, oldval,shift
6992 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6993 // slw mask, mask2, shift
6994 // and newval3, newval2, mask
6995 // and oldval3, oldval2, mask
6996 // loop1MBB:
6997 // lwarx tmpDest, ptr
6998 // and tmp, tmpDest, mask
6999 // cmpw tmp, oldval3
7000 // bne- midMBB
7001 // loop2MBB:
7002 // andc tmp2, tmpDest, mask
7003 // or tmp4, tmp2, newval3
7004 // stwcx. tmp4, ptr
7005 // bne- loop1MBB
7006 // b exitBB
7007 // midMBB:
7008 // stwcx. tmpDest, ptr
7009 // exitBB:
7010 // srw dest, tmpDest, shift
Jakob Stoklund Olesen7067bff2011-04-04 17:07:06 +00007011 if (ptrA != ZeroReg) {
Dale Johannesen340d2642008-08-30 00:08:53 +00007012 Ptr1Reg = RegInfo.createVirtualRegister(RC);
Dale Johannesene9f623e2009-02-13 02:27:39 +00007013 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
Dale Johannesen340d2642008-08-30 00:08:53 +00007014 .addReg(ptrA).addReg(ptrB);
7015 } else {
7016 Ptr1Reg = ptrB;
7017 }
Dale Johannesene9f623e2009-02-13 02:27:39 +00007018 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
Dale Johannesen340d2642008-08-30 00:08:53 +00007019 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
Dale Johannesene9f623e2009-02-13 02:27:39 +00007020 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
Dale Johannesen340d2642008-08-30 00:08:53 +00007021 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7022 if (is64bit)
Dale Johannesene9f623e2009-02-13 02:27:39 +00007023 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
Dale Johannesen340d2642008-08-30 00:08:53 +00007024 .addReg(Ptr1Reg).addImm(0).addImm(61);
7025 else
Dale Johannesene9f623e2009-02-13 02:27:39 +00007026 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
Dale Johannesen340d2642008-08-30 00:08:53 +00007027 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
Dale Johannesene9f623e2009-02-13 02:27:39 +00007028 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
Dale Johannesen340d2642008-08-30 00:08:53 +00007029 .addReg(newval).addReg(ShiftReg);
Dale Johannesene9f623e2009-02-13 02:27:39 +00007030 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
Dale Johannesen340d2642008-08-30 00:08:53 +00007031 .addReg(oldval).addReg(ShiftReg);
7032 if (is8bit)
Dale Johannesene9f623e2009-02-13 02:27:39 +00007033 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
Dale Johannesen340d2642008-08-30 00:08:53 +00007034 else {
Dale Johannesene9f623e2009-02-13 02:27:39 +00007035 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7036 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7037 .addReg(Mask3Reg).addImm(65535);
Dale Johannesen340d2642008-08-30 00:08:53 +00007038 }
Dale Johannesene9f623e2009-02-13 02:27:39 +00007039 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
Dale Johannesen340d2642008-08-30 00:08:53 +00007040 .addReg(Mask2Reg).addReg(ShiftReg);
Dale Johannesene9f623e2009-02-13 02:27:39 +00007041 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
Dale Johannesen340d2642008-08-30 00:08:53 +00007042 .addReg(NewVal2Reg).addReg(MaskReg);
Dale Johannesene9f623e2009-02-13 02:27:39 +00007043 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
Dale Johannesen340d2642008-08-30 00:08:53 +00007044 .addReg(OldVal2Reg).addReg(MaskReg);
7045
7046 BB = loop1MBB;
Dale Johannesene9f623e2009-02-13 02:27:39 +00007047 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
Jakob Stoklund Olesen7067bff2011-04-04 17:07:06 +00007048 .addReg(ZeroReg).addReg(PtrReg);
Dale Johannesene9f623e2009-02-13 02:27:39 +00007049 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7050 .addReg(TmpDestReg).addReg(MaskReg);
7051 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
Dale Johannesen340d2642008-08-30 00:08:53 +00007052 .addReg(TmpReg).addReg(OldVal3Reg);
Dale Johannesene9f623e2009-02-13 02:27:39 +00007053 BuildMI(BB, dl, TII->get(PPC::BCC))
Dale Johannesen340d2642008-08-30 00:08:53 +00007054 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7055 BB->addSuccessor(loop2MBB);
7056 BB->addSuccessor(midMBB);
7057
7058 BB = loop2MBB;
Dale Johannesene9f623e2009-02-13 02:27:39 +00007059 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7060 .addReg(TmpDestReg).addReg(MaskReg);
7061 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7062 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7063 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
Jakob Stoklund Olesen7067bff2011-04-04 17:07:06 +00007064 .addReg(ZeroReg).addReg(PtrReg);
Dale Johannesene9f623e2009-02-13 02:27:39 +00007065 BuildMI(BB, dl, TII->get(PPC::BCC))
Dale Johannesen340d2642008-08-30 00:08:53 +00007066 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
Dale Johannesene9f623e2009-02-13 02:27:39 +00007067 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
Dale Johannesen340d2642008-08-30 00:08:53 +00007068 BB->addSuccessor(loop1MBB);
7069 BB->addSuccessor(exitMBB);
Scott Michelcf0da6c2009-02-17 22:15:04 +00007070
Dale Johannesen340d2642008-08-30 00:08:53 +00007071 BB = midMBB;
Dale Johannesene9f623e2009-02-13 02:27:39 +00007072 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
Jakob Stoklund Olesen7067bff2011-04-04 17:07:06 +00007073 .addReg(ZeroReg).addReg(PtrReg);
Dale Johannesen340d2642008-08-30 00:08:53 +00007074 BB->addSuccessor(exitMBB);
7075
7076 // exitMBB:
7077 // ...
7078 BB = exitMBB;
Jakob Stoklund Olesen13ce2362011-04-04 17:57:29 +00007079 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7080 .addReg(ShiftReg);
Ulrich Weigand874fc622013-03-26 10:56:22 +00007081 } else if (MI->getOpcode() == PPC::FADDrtz) {
7082 // This pseudo performs an FADD with rounding mode temporarily forced
7083 // to round-to-zero. We emit this via custom inserter since the FPSCR
7084 // is not modeled at the SelectionDAG level.
7085 unsigned Dest = MI->getOperand(0).getReg();
7086 unsigned Src1 = MI->getOperand(1).getReg();
7087 unsigned Src2 = MI->getOperand(2).getReg();
7088 DebugLoc dl = MI->getDebugLoc();
7089
7090 MachineRegisterInfo &RegInfo = F->getRegInfo();
7091 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7092
7093 // Save FPSCR value.
7094 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7095
7096 // Set rounding mode to round-to-zero.
7097 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7098 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7099
7100 // Perform addition.
7101 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7102
7103 // Restore FPSCR value.
7104 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
Hal Finkel940ab932014-02-28 00:27:01 +00007105 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7106 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7107 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7108 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7109 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7110 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7111 PPC::ANDIo8 : PPC::ANDIo;
7112 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7113 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7114
7115 MachineRegisterInfo &RegInfo = F->getRegInfo();
7116 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7117 &PPC::GPRCRegClass :
7118 &PPC::G8RCRegClass);
7119
7120 DebugLoc dl = MI->getDebugLoc();
7121 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7122 .addReg(MI->getOperand(1).getReg()).addImm(1);
7123 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7124 MI->getOperand(0).getReg())
7125 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
Dale Johannesen340d2642008-08-30 00:08:53 +00007126 } else {
Torok Edwinfbcc6632009-07-14 16:55:14 +00007127 llvm_unreachable("Unexpected instr type to insert");
Evan Cheng32e376f2008-07-12 02:23:19 +00007128 }
Chris Lattner9b577f12005-08-26 21:23:58 +00007129
Dan Gohman34396292010-07-06 20:24:04 +00007130 MI->eraseFromParent(); // The pseudo instruction is gone now.
Chris Lattner9b577f12005-08-26 21:23:58 +00007131 return BB;
7132}
7133
Chris Lattner4211ca92006-04-14 06:01:58 +00007134//===----------------------------------------------------------------------===//
7135// Target Optimization Hooks
7136//===----------------------------------------------------------------------===//
7137
Hal Finkelb0c810f2013-04-03 17:44:56 +00007138SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7139 DAGCombinerInfo &DCI) const {
Hal Finkel2e103312013-04-03 04:01:11 +00007140 if (DCI.isAfterLegalizeVectorOps())
7141 return SDValue();
7142
Hal Finkelb0c810f2013-04-03 17:44:56 +00007143 EVT VT = Op.getValueType();
7144
Eric Christopherb1aaebe2014-06-12 22:38:18 +00007145 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7146 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7147 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7148 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
Hal Finkel2e103312013-04-03 04:01:11 +00007149
7150 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7151 // For the reciprocal, we need to find the zero of the function:
7152 // F(X) = A X - 1 [which has a zero at X = 1/A]
7153 // =>
7154 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7155 // does not require additional intermediate precision]
7156
7157 // Convergence is quadratic, so we essentially double the number of digits
7158 // correct after every iteration. The minimum architected relative
7159 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7160 // 23 digits and double has 52 digits.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00007161 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
Hal Finkelb0c810f2013-04-03 17:44:56 +00007162 if (VT.getScalarType() == MVT::f64)
Hal Finkel2e103312013-04-03 04:01:11 +00007163 ++Iterations;
7164
7165 SelectionDAG &DAG = DCI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +00007166 SDLoc dl(Op);
Hal Finkel2e103312013-04-03 04:01:11 +00007167
7168 SDValue FPOne =
Hal Finkelb0c810f2013-04-03 17:44:56 +00007169 DAG.getConstantFP(1.0, VT.getScalarType());
7170 if (VT.isVector()) {
7171 assert(VT.getVectorNumElements() == 4 &&
Hal Finkel2e103312013-04-03 04:01:11 +00007172 "Unknown vector type");
Hal Finkelb0c810f2013-04-03 17:44:56 +00007173 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
Hal Finkel2e103312013-04-03 04:01:11 +00007174 FPOne, FPOne, FPOne, FPOne);
7175 }
7176
Hal Finkelb0c810f2013-04-03 17:44:56 +00007177 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
Hal Finkel2e103312013-04-03 04:01:11 +00007178 DCI.AddToWorklist(Est.getNode());
7179
7180 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7181 for (int i = 0; i < Iterations; ++i) {
Hal Finkelb0c810f2013-04-03 17:44:56 +00007182 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
Hal Finkel2e103312013-04-03 04:01:11 +00007183 DCI.AddToWorklist(NewEst.getNode());
7184
Hal Finkelb0c810f2013-04-03 17:44:56 +00007185 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
Hal Finkel2e103312013-04-03 04:01:11 +00007186 DCI.AddToWorklist(NewEst.getNode());
7187
Hal Finkelb0c810f2013-04-03 17:44:56 +00007188 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
Hal Finkel2e103312013-04-03 04:01:11 +00007189 DCI.AddToWorklist(NewEst.getNode());
7190
Hal Finkelb0c810f2013-04-03 17:44:56 +00007191 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
Hal Finkel2e103312013-04-03 04:01:11 +00007192 DCI.AddToWorklist(Est.getNode());
7193 }
7194
7195 return Est;
7196 }
7197
7198 return SDValue();
7199}
7200
Hal Finkelb0c810f2013-04-03 17:44:56 +00007201SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
Hal Finkel2e103312013-04-03 04:01:11 +00007202 DAGCombinerInfo &DCI) const {
7203 if (DCI.isAfterLegalizeVectorOps())
7204 return SDValue();
7205
Hal Finkelb0c810f2013-04-03 17:44:56 +00007206 EVT VT = Op.getValueType();
7207
Eric Christopherb1aaebe2014-06-12 22:38:18 +00007208 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7209 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7210 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7211 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
Hal Finkel2e103312013-04-03 04:01:11 +00007212
7213 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7214 // For the reciprocal sqrt, we need to find the zero of the function:
7215 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7216 // =>
7217 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7218 // As a result, we precompute A/2 prior to the iteration loop.
7219
7220 // Convergence is quadratic, so we essentially double the number of digits
7221 // correct after every iteration. The minimum architected relative
7222 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7223 // 23 digits and double has 52 digits.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00007224 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
Hal Finkelb0c810f2013-04-03 17:44:56 +00007225 if (VT.getScalarType() == MVT::f64)
Hal Finkel2e103312013-04-03 04:01:11 +00007226 ++Iterations;
7227
7228 SelectionDAG &DAG = DCI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +00007229 SDLoc dl(Op);
Hal Finkel2e103312013-04-03 04:01:11 +00007230
Hal Finkelb0c810f2013-04-03 17:44:56 +00007231 SDValue FPThreeHalves =
7232 DAG.getConstantFP(1.5, VT.getScalarType());
7233 if (VT.isVector()) {
7234 assert(VT.getVectorNumElements() == 4 &&
Hal Finkel2e103312013-04-03 04:01:11 +00007235 "Unknown vector type");
Hal Finkelb0c810f2013-04-03 17:44:56 +00007236 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7237 FPThreeHalves, FPThreeHalves,
7238 FPThreeHalves, FPThreeHalves);
Hal Finkel2e103312013-04-03 04:01:11 +00007239 }
7240
Hal Finkelb0c810f2013-04-03 17:44:56 +00007241 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
Hal Finkel2e103312013-04-03 04:01:11 +00007242 DCI.AddToWorklist(Est.getNode());
7243
7244 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7245 // this entire sequence requires only one FP constant.
Hal Finkelb0c810f2013-04-03 17:44:56 +00007246 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
Hal Finkel2e103312013-04-03 04:01:11 +00007247 DCI.AddToWorklist(HalfArg.getNode());
7248
Hal Finkelb0c810f2013-04-03 17:44:56 +00007249 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
Hal Finkel2e103312013-04-03 04:01:11 +00007250 DCI.AddToWorklist(HalfArg.getNode());
7251
7252 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7253 for (int i = 0; i < Iterations; ++i) {
Hal Finkelb0c810f2013-04-03 17:44:56 +00007254 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
Hal Finkel2e103312013-04-03 04:01:11 +00007255 DCI.AddToWorklist(NewEst.getNode());
7256
Hal Finkelb0c810f2013-04-03 17:44:56 +00007257 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
Hal Finkel2e103312013-04-03 04:01:11 +00007258 DCI.AddToWorklist(NewEst.getNode());
7259
Hal Finkelb0c810f2013-04-03 17:44:56 +00007260 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
Hal Finkel2e103312013-04-03 04:01:11 +00007261 DCI.AddToWorklist(NewEst.getNode());
7262
Hal Finkelb0c810f2013-04-03 17:44:56 +00007263 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
Hal Finkel2e103312013-04-03 04:01:11 +00007264 DCI.AddToWorklist(Est.getNode());
7265 }
7266
7267 return Est;
7268 }
7269
7270 return SDValue();
7271}
7272
Hal Finkel8ebfe6c2013-05-27 02:06:39 +00007273// Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7274// not enforce equality of the chain operands.
7275static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7276 unsigned Bytes, int Dist,
7277 SelectionDAG &DAG) {
7278 EVT VT = LS->getMemoryVT();
7279 if (VT.getSizeInBits() / 8 != Bytes)
7280 return false;
7281
7282 SDValue Loc = LS->getBasePtr();
7283 SDValue BaseLoc = Base->getBasePtr();
7284 if (Loc.getOpcode() == ISD::FrameIndex) {
7285 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7286 return false;
7287 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7288 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7289 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7290 int FS = MFI->getObjectSize(FI);
7291 int BFS = MFI->getObjectSize(BFI);
7292 if (FS != BFS || FS != (int)Bytes) return false;
7293 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7294 }
7295
7296 // Handle X+C
7297 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7298 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7299 return true;
7300
7301 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
Craig Topper062a2ba2014-04-25 05:30:21 +00007302 const GlobalValue *GV1 = nullptr;
7303 const GlobalValue *GV2 = nullptr;
Hal Finkel8ebfe6c2013-05-27 02:06:39 +00007304 int64_t Offset1 = 0;
7305 int64_t Offset2 = 0;
7306 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7307 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7308 if (isGA1 && isGA2 && GV1 == GV2)
7309 return Offset1 == (Offset2 + Dist*Bytes);
7310 return false;
7311}
7312
Hal Finkel7d8a6912013-05-26 18:08:30 +00007313// Return true is there is a nearyby consecutive load to the one provided
7314// (regardless of alignment). We search up and down the chain, looking though
7315// token factors and other loads (but nothing else). As a result, a true
7316// results indicates that it is safe to create a new consecutive load adjacent
7317// to the load provided.
7318static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7319 SDValue Chain = LD->getChain();
7320 EVT VT = LD->getMemoryVT();
7321
7322 SmallSet<SDNode *, 16> LoadRoots;
7323 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7324 SmallSet<SDNode *, 16> Visited;
7325
7326 // First, search up the chain, branching to follow all token-factor operands.
7327 // If we find a consecutive load, then we're done, otherwise, record all
7328 // nodes just above the top-level loads and token factors.
7329 while (!Queue.empty()) {
7330 SDNode *ChainNext = Queue.pop_back_val();
7331 if (!Visited.insert(ChainNext))
7332 continue;
7333
7334 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
Hal Finkel8ebfe6c2013-05-27 02:06:39 +00007335 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
Hal Finkel7d8a6912013-05-26 18:08:30 +00007336 return true;
7337
7338 if (!Visited.count(ChainLD->getChain().getNode()))
7339 Queue.push_back(ChainLD->getChain().getNode());
7340 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
Craig Topper66e588b2014-06-29 00:40:57 +00007341 for (const SDUse &O : ChainNext->ops())
7342 if (!Visited.count(O.getNode()))
7343 Queue.push_back(O.getNode());
Hal Finkel7d8a6912013-05-26 18:08:30 +00007344 } else
7345 LoadRoots.insert(ChainNext);
7346 }
7347
7348 // Second, search down the chain, starting from the top-level nodes recorded
7349 // in the first phase. These top-level nodes are the nodes just above all
7350 // loads and token factors. Starting with their uses, recursively look though
7351 // all loads (just the chain uses) and token factors to find a consecutive
7352 // load.
7353 Visited.clear();
7354 Queue.clear();
7355
7356 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7357 IE = LoadRoots.end(); I != IE; ++I) {
7358 Queue.push_back(*I);
7359
7360 while (!Queue.empty()) {
7361 SDNode *LoadRoot = Queue.pop_back_val();
7362 if (!Visited.insert(LoadRoot))
7363 continue;
7364
7365 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
Hal Finkel8ebfe6c2013-05-27 02:06:39 +00007366 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
Hal Finkel7d8a6912013-05-26 18:08:30 +00007367 return true;
7368
7369 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7370 UE = LoadRoot->use_end(); UI != UE; ++UI)
7371 if (((isa<LoadSDNode>(*UI) &&
7372 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7373 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7374 Queue.push_back(*UI);
7375 }
7376 }
7377
7378 return false;
7379}
7380
Hal Finkel940ab932014-02-28 00:27:01 +00007381SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7382 DAGCombinerInfo &DCI) const {
7383 SelectionDAG &DAG = DCI.DAG;
7384 SDLoc dl(N);
7385
Eric Christopherb1aaebe2014-06-12 22:38:18 +00007386 assert(Subtarget.useCRBits() &&
Hal Finkel940ab932014-02-28 00:27:01 +00007387 "Expecting to be tracking CR bits");
7388 // If we're tracking CR bits, we need to be careful that we don't have:
7389 // trunc(binary-ops(zext(x), zext(y)))
7390 // or
7391 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7392 // such that we're unnecessarily moving things into GPRs when it would be
7393 // better to keep them in CR bits.
7394
7395 // Note that trunc here can be an actual i1 trunc, or can be the effective
7396 // truncation that comes from a setcc or select_cc.
7397 if (N->getOpcode() == ISD::TRUNCATE &&
7398 N->getValueType(0) != MVT::i1)
7399 return SDValue();
7400
7401 if (N->getOperand(0).getValueType() != MVT::i32 &&
7402 N->getOperand(0).getValueType() != MVT::i64)
7403 return SDValue();
7404
7405 if (N->getOpcode() == ISD::SETCC ||
7406 N->getOpcode() == ISD::SELECT_CC) {
7407 // If we're looking at a comparison, then we need to make sure that the
7408 // high bits (all except for the first) don't matter the result.
7409 ISD::CondCode CC =
7410 cast<CondCodeSDNode>(N->getOperand(
7411 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7412 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7413
7414 if (ISD::isSignedIntSetCC(CC)) {
7415 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7416 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7417 return SDValue();
7418 } else if (ISD::isUnsignedIntSetCC(CC)) {
7419 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7420 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7421 !DAG.MaskedValueIsZero(N->getOperand(1),
7422 APInt::getHighBitsSet(OpBits, OpBits-1)))
7423 return SDValue();
7424 } else {
7425 // This is neither a signed nor an unsigned comparison, just make sure
7426 // that the high bits are equal.
7427 APInt Op1Zero, Op1One;
7428 APInt Op2Zero, Op2One;
Jay Foada0653a32014-05-14 21:14:37 +00007429 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7430 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
Hal Finkel940ab932014-02-28 00:27:01 +00007431
7432 // We don't really care about what is known about the first bit (if
7433 // anything), so clear it in all masks prior to comparing them.
7434 Op1Zero.clearBit(0); Op1One.clearBit(0);
7435 Op2Zero.clearBit(0); Op2One.clearBit(0);
7436
7437 if (Op1Zero != Op2Zero || Op1One != Op2One)
7438 return SDValue();
7439 }
7440 }
7441
7442 // We now know that the higher-order bits are irrelevant, we just need to
7443 // make sure that all of the intermediate operations are bit operations, and
7444 // all inputs are extensions.
7445 if (N->getOperand(0).getOpcode() != ISD::AND &&
7446 N->getOperand(0).getOpcode() != ISD::OR &&
7447 N->getOperand(0).getOpcode() != ISD::XOR &&
7448 N->getOperand(0).getOpcode() != ISD::SELECT &&
7449 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7450 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7451 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7452 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7453 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7454 return SDValue();
7455
7456 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7457 N->getOperand(1).getOpcode() != ISD::AND &&
7458 N->getOperand(1).getOpcode() != ISD::OR &&
7459 N->getOperand(1).getOpcode() != ISD::XOR &&
7460 N->getOperand(1).getOpcode() != ISD::SELECT &&
7461 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7462 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7463 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7464 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7465 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7466 return SDValue();
7467
7468 SmallVector<SDValue, 4> Inputs;
7469 SmallVector<SDValue, 8> BinOps, PromOps;
7470 SmallPtrSet<SDNode *, 16> Visited;
7471
7472 for (unsigned i = 0; i < 2; ++i) {
7473 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7474 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7475 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7476 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7477 isa<ConstantSDNode>(N->getOperand(i)))
7478 Inputs.push_back(N->getOperand(i));
7479 else
7480 BinOps.push_back(N->getOperand(i));
7481
7482 if (N->getOpcode() == ISD::TRUNCATE)
7483 break;
7484 }
7485
7486 // Visit all inputs, collect all binary operations (and, or, xor and
7487 // select) that are all fed by extensions.
7488 while (!BinOps.empty()) {
7489 SDValue BinOp = BinOps.back();
7490 BinOps.pop_back();
7491
7492 if (!Visited.insert(BinOp.getNode()))
7493 continue;
7494
7495 PromOps.push_back(BinOp);
7496
7497 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7498 // The condition of the select is not promoted.
7499 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7500 continue;
7501 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7502 continue;
7503
7504 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7505 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7506 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7507 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7508 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7509 Inputs.push_back(BinOp.getOperand(i));
7510 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7511 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7512 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7513 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7514 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7515 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7516 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7517 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7518 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7519 BinOps.push_back(BinOp.getOperand(i));
7520 } else {
7521 // We have an input that is not an extension or another binary
7522 // operation; we'll abort this transformation.
7523 return SDValue();
7524 }
7525 }
7526 }
7527
7528 // Make sure that this is a self-contained cluster of operations (which
7529 // is not quite the same thing as saying that everything has only one
7530 // use).
7531 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7532 if (isa<ConstantSDNode>(Inputs[i]))
7533 continue;
7534
7535 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7536 UE = Inputs[i].getNode()->use_end();
7537 UI != UE; ++UI) {
7538 SDNode *User = *UI;
7539 if (User != N && !Visited.count(User))
7540 return SDValue();
Hal Finkel46043ed2014-03-01 21:36:57 +00007541
7542 // Make sure that we're not going to promote the non-output-value
7543 // operand(s) or SELECT or SELECT_CC.
7544 // FIXME: Although we could sometimes handle this, and it does occur in
7545 // practice that one of the condition inputs to the select is also one of
7546 // the outputs, we currently can't deal with this.
7547 if (User->getOpcode() == ISD::SELECT) {
7548 if (User->getOperand(0) == Inputs[i])
7549 return SDValue();
7550 } else if (User->getOpcode() == ISD::SELECT_CC) {
7551 if (User->getOperand(0) == Inputs[i] ||
7552 User->getOperand(1) == Inputs[i])
7553 return SDValue();
7554 }
Hal Finkel940ab932014-02-28 00:27:01 +00007555 }
7556 }
7557
7558 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7559 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7560 UE = PromOps[i].getNode()->use_end();
7561 UI != UE; ++UI) {
7562 SDNode *User = *UI;
7563 if (User != N && !Visited.count(User))
7564 return SDValue();
Hal Finkel46043ed2014-03-01 21:36:57 +00007565
7566 // Make sure that we're not going to promote the non-output-value
7567 // operand(s) or SELECT or SELECT_CC.
7568 // FIXME: Although we could sometimes handle this, and it does occur in
7569 // practice that one of the condition inputs to the select is also one of
7570 // the outputs, we currently can't deal with this.
7571 if (User->getOpcode() == ISD::SELECT) {
7572 if (User->getOperand(0) == PromOps[i])
7573 return SDValue();
7574 } else if (User->getOpcode() == ISD::SELECT_CC) {
7575 if (User->getOperand(0) == PromOps[i] ||
7576 User->getOperand(1) == PromOps[i])
7577 return SDValue();
7578 }
Hal Finkel940ab932014-02-28 00:27:01 +00007579 }
7580 }
7581
7582 // Replace all inputs with the extension operand.
7583 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7584 // Constants may have users outside the cluster of to-be-promoted nodes,
7585 // and so we need to replace those as we do the promotions.
7586 if (isa<ConstantSDNode>(Inputs[i]))
7587 continue;
7588 else
7589 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7590 }
7591
7592 // Replace all operations (these are all the same, but have a different
7593 // (i1) return type). DAG.getNode will validate that the types of
7594 // a binary operator match, so go through the list in reverse so that
7595 // we've likely promoted both operands first. Any intermediate truncations or
7596 // extensions disappear.
7597 while (!PromOps.empty()) {
7598 SDValue PromOp = PromOps.back();
7599 PromOps.pop_back();
7600
7601 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7602 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7603 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7604 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7605 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7606 PromOp.getOperand(0).getValueType() != MVT::i1) {
7607 // The operand is not yet ready (see comment below).
7608 PromOps.insert(PromOps.begin(), PromOp);
7609 continue;
7610 }
7611
7612 SDValue RepValue = PromOp.getOperand(0);
7613 if (isa<ConstantSDNode>(RepValue))
7614 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7615
7616 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7617 continue;
7618 }
7619
7620 unsigned C;
7621 switch (PromOp.getOpcode()) {
7622 default: C = 0; break;
7623 case ISD::SELECT: C = 1; break;
7624 case ISD::SELECT_CC: C = 2; break;
7625 }
7626
7627 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7628 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7629 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7630 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7631 // The to-be-promoted operands of this node have not yet been
7632 // promoted (this should be rare because we're going through the
7633 // list backward, but if one of the operands has several users in
7634 // this cluster of to-be-promoted nodes, it is possible).
7635 PromOps.insert(PromOps.begin(), PromOp);
7636 continue;
7637 }
7638
7639 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7640 PromOp.getNode()->op_end());
7641
7642 // If there are any constant inputs, make sure they're replaced now.
7643 for (unsigned i = 0; i < 2; ++i)
7644 if (isa<ConstantSDNode>(Ops[C+i]))
7645 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7646
7647 DAG.ReplaceAllUsesOfValueWith(PromOp,
Craig Topper48d114b2014-04-26 18:35:24 +00007648 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
Hal Finkel940ab932014-02-28 00:27:01 +00007649 }
7650
7651 // Now we're left with the initial truncation itself.
7652 if (N->getOpcode() == ISD::TRUNCATE)
7653 return N->getOperand(0);
7654
7655 // Otherwise, this is a comparison. The operands to be compared have just
7656 // changed type (to i1), but everything else is the same.
7657 return SDValue(N, 0);
7658}
7659
7660SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7661 DAGCombinerInfo &DCI) const {
7662 SelectionDAG &DAG = DCI.DAG;
7663 SDLoc dl(N);
7664
Hal Finkel940ab932014-02-28 00:27:01 +00007665 // If we're tracking CR bits, we need to be careful that we don't have:
7666 // zext(binary-ops(trunc(x), trunc(y)))
7667 // or
7668 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7669 // such that we're unnecessarily moving things into CR bits that can more
7670 // efficiently stay in GPRs. Note that if we're not certain that the high
7671 // bits are set as required by the final extension, we still may need to do
7672 // some masking to get the proper behavior.
7673
Hal Finkel46043ed2014-03-01 21:36:57 +00007674 // This same functionality is important on PPC64 when dealing with
7675 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7676 // the return values of functions. Because it is so similar, it is handled
7677 // here as well.
7678
Hal Finkel940ab932014-02-28 00:27:01 +00007679 if (N->getValueType(0) != MVT::i32 &&
7680 N->getValueType(0) != MVT::i64)
7681 return SDValue();
7682
Hal Finkel46043ed2014-03-01 21:36:57 +00007683 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
Eric Christopherb1aaebe2014-06-12 22:38:18 +00007684 Subtarget.useCRBits()) ||
Hal Finkel46043ed2014-03-01 21:36:57 +00007685 (N->getOperand(0).getValueType() == MVT::i32 &&
Eric Christopherb1aaebe2014-06-12 22:38:18 +00007686 Subtarget.isPPC64())))
Hal Finkel940ab932014-02-28 00:27:01 +00007687 return SDValue();
7688
7689 if (N->getOperand(0).getOpcode() != ISD::AND &&
7690 N->getOperand(0).getOpcode() != ISD::OR &&
7691 N->getOperand(0).getOpcode() != ISD::XOR &&
7692 N->getOperand(0).getOpcode() != ISD::SELECT &&
7693 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7694 return SDValue();
7695
7696 SmallVector<SDValue, 4> Inputs;
7697 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7698 SmallPtrSet<SDNode *, 16> Visited;
7699
7700 // Visit all inputs, collect all binary operations (and, or, xor and
7701 // select) that are all fed by truncations.
7702 while (!BinOps.empty()) {
7703 SDValue BinOp = BinOps.back();
7704 BinOps.pop_back();
7705
7706 if (!Visited.insert(BinOp.getNode()))
7707 continue;
7708
7709 PromOps.push_back(BinOp);
7710
7711 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7712 // The condition of the select is not promoted.
7713 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7714 continue;
7715 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7716 continue;
7717
7718 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7719 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7720 Inputs.push_back(BinOp.getOperand(i));
7721 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7722 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7723 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7724 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7725 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7726 BinOps.push_back(BinOp.getOperand(i));
7727 } else {
7728 // We have an input that is not a truncation or another binary
7729 // operation; we'll abort this transformation.
7730 return SDValue();
7731 }
7732 }
7733 }
7734
7735 // Make sure that this is a self-contained cluster of operations (which
7736 // is not quite the same thing as saying that everything has only one
7737 // use).
7738 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7739 if (isa<ConstantSDNode>(Inputs[i]))
7740 continue;
7741
7742 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7743 UE = Inputs[i].getNode()->use_end();
7744 UI != UE; ++UI) {
7745 SDNode *User = *UI;
7746 if (User != N && !Visited.count(User))
7747 return SDValue();
Hal Finkel46043ed2014-03-01 21:36:57 +00007748
7749 // Make sure that we're not going to promote the non-output-value
7750 // operand(s) or SELECT or SELECT_CC.
7751 // FIXME: Although we could sometimes handle this, and it does occur in
7752 // practice that one of the condition inputs to the select is also one of
7753 // the outputs, we currently can't deal with this.
7754 if (User->getOpcode() == ISD::SELECT) {
7755 if (User->getOperand(0) == Inputs[i])
7756 return SDValue();
7757 } else if (User->getOpcode() == ISD::SELECT_CC) {
7758 if (User->getOperand(0) == Inputs[i] ||
7759 User->getOperand(1) == Inputs[i])
7760 return SDValue();
7761 }
Hal Finkel940ab932014-02-28 00:27:01 +00007762 }
7763 }
7764
7765 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7766 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7767 UE = PromOps[i].getNode()->use_end();
7768 UI != UE; ++UI) {
7769 SDNode *User = *UI;
7770 if (User != N && !Visited.count(User))
7771 return SDValue();
Hal Finkel46043ed2014-03-01 21:36:57 +00007772
7773 // Make sure that we're not going to promote the non-output-value
7774 // operand(s) or SELECT or SELECT_CC.
7775 // FIXME: Although we could sometimes handle this, and it does occur in
7776 // practice that one of the condition inputs to the select is also one of
7777 // the outputs, we currently can't deal with this.
7778 if (User->getOpcode() == ISD::SELECT) {
7779 if (User->getOperand(0) == PromOps[i])
7780 return SDValue();
7781 } else if (User->getOpcode() == ISD::SELECT_CC) {
7782 if (User->getOperand(0) == PromOps[i] ||
7783 User->getOperand(1) == PromOps[i])
7784 return SDValue();
7785 }
Hal Finkel940ab932014-02-28 00:27:01 +00007786 }
7787 }
7788
Hal Finkel46043ed2014-03-01 21:36:57 +00007789 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
Hal Finkel940ab932014-02-28 00:27:01 +00007790 bool ReallyNeedsExt = false;
7791 if (N->getOpcode() != ISD::ANY_EXTEND) {
7792 // If all of the inputs are not already sign/zero extended, then
7793 // we'll still need to do that at the end.
7794 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7795 if (isa<ConstantSDNode>(Inputs[i]))
7796 continue;
7797
7798 unsigned OpBits =
7799 Inputs[i].getOperand(0).getValueSizeInBits();
Hal Finkel46043ed2014-03-01 21:36:57 +00007800 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7801
Hal Finkel940ab932014-02-28 00:27:01 +00007802 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7803 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
Hal Finkel46043ed2014-03-01 21:36:57 +00007804 APInt::getHighBitsSet(OpBits,
7805 OpBits-PromBits))) ||
Hal Finkel940ab932014-02-28 00:27:01 +00007806 (N->getOpcode() == ISD::SIGN_EXTEND &&
Hal Finkel46043ed2014-03-01 21:36:57 +00007807 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7808 (OpBits-(PromBits-1)))) {
Hal Finkel940ab932014-02-28 00:27:01 +00007809 ReallyNeedsExt = true;
7810 break;
7811 }
7812 }
7813 }
7814
7815 // Replace all inputs, either with the truncation operand, or a
7816 // truncation or extension to the final output type.
7817 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7818 // Constant inputs need to be replaced with the to-be-promoted nodes that
7819 // use them because they might have users outside of the cluster of
7820 // promoted nodes.
7821 if (isa<ConstantSDNode>(Inputs[i]))
7822 continue;
7823
7824 SDValue InSrc = Inputs[i].getOperand(0);
7825 if (Inputs[i].getValueType() == N->getValueType(0))
7826 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7827 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7828 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7829 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7830 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7831 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7832 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7833 else
7834 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7835 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7836 }
7837
7838 // Replace all operations (these are all the same, but have a different
7839 // (promoted) return type). DAG.getNode will validate that the types of
7840 // a binary operator match, so go through the list in reverse so that
7841 // we've likely promoted both operands first.
7842 while (!PromOps.empty()) {
7843 SDValue PromOp = PromOps.back();
7844 PromOps.pop_back();
7845
7846 unsigned C;
7847 switch (PromOp.getOpcode()) {
7848 default: C = 0; break;
7849 case ISD::SELECT: C = 1; break;
7850 case ISD::SELECT_CC: C = 2; break;
7851 }
7852
7853 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7854 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7855 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7856 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7857 // The to-be-promoted operands of this node have not yet been
7858 // promoted (this should be rare because we're going through the
7859 // list backward, but if one of the operands has several users in
7860 // this cluster of to-be-promoted nodes, it is possible).
7861 PromOps.insert(PromOps.begin(), PromOp);
7862 continue;
7863 }
7864
7865 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7866 PromOp.getNode()->op_end());
7867
7868 // If this node has constant inputs, then they'll need to be promoted here.
7869 for (unsigned i = 0; i < 2; ++i) {
7870 if (!isa<ConstantSDNode>(Ops[C+i]))
7871 continue;
7872 if (Ops[C+i].getValueType() == N->getValueType(0))
7873 continue;
7874
7875 if (N->getOpcode() == ISD::SIGN_EXTEND)
7876 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7877 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7878 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7879 else
7880 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7881 }
7882
7883 DAG.ReplaceAllUsesOfValueWith(PromOp,
Craig Topper48d114b2014-04-26 18:35:24 +00007884 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
Hal Finkel940ab932014-02-28 00:27:01 +00007885 }
7886
7887 // Now we're left with the initial extension itself.
7888 if (!ReallyNeedsExt)
7889 return N->getOperand(0);
7890
Hal Finkel46043ed2014-03-01 21:36:57 +00007891 // To zero extend, just mask off everything except for the first bit (in the
7892 // i1 case).
Hal Finkel940ab932014-02-28 00:27:01 +00007893 if (N->getOpcode() == ISD::ZERO_EXTEND)
7894 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
Hal Finkel46043ed2014-03-01 21:36:57 +00007895 DAG.getConstant(APInt::getLowBitsSet(
7896 N->getValueSizeInBits(0), PromBits),
7897 N->getValueType(0)));
Hal Finkel940ab932014-02-28 00:27:01 +00007898
7899 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7900 "Invalid extension type");
7901 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7902 SDValue ShiftCst =
Hal Finkel46043ed2014-03-01 21:36:57 +00007903 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
Hal Finkel940ab932014-02-28 00:27:01 +00007904 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7905 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7906 N->getOperand(0), ShiftCst), ShiftCst);
7907}
7908
Duncan Sandsdc2dac12008-11-24 14:53:14 +00007909SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7910 DAGCombinerInfo &DCI) const {
Dan Gohman57c732b2010-04-21 01:34:56 +00007911 const TargetMachine &TM = getTargetMachine();
Chris Lattnerf4184352006-03-01 04:57:39 +00007912 SelectionDAG &DAG = DCI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +00007913 SDLoc dl(N);
Chris Lattnerf4184352006-03-01 04:57:39 +00007914 switch (N->getOpcode()) {
7915 default: break;
Chris Lattner3c48ea52006-09-19 05:22:59 +00007916 case PPCISD::SHL:
7917 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
Dan Gohmanf1d83042010-06-18 14:22:04 +00007918 if (C->isNullValue()) // 0 << V -> 0.
Chris Lattner3c48ea52006-09-19 05:22:59 +00007919 return N->getOperand(0);
7920 }
7921 break;
7922 case PPCISD::SRL:
7923 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
Dan Gohmanf1d83042010-06-18 14:22:04 +00007924 if (C->isNullValue()) // 0 >>u V -> 0.
Chris Lattner3c48ea52006-09-19 05:22:59 +00007925 return N->getOperand(0);
7926 }
7927 break;
7928 case PPCISD::SRA:
7929 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
Dan Gohmanf1d83042010-06-18 14:22:04 +00007930 if (C->isNullValue() || // 0 >>s V -> 0.
Chris Lattner3c48ea52006-09-19 05:22:59 +00007931 C->isAllOnesValue()) // -1 >>s V -> -1.
7932 return N->getOperand(0);
7933 }
7934 break;
Hal Finkel940ab932014-02-28 00:27:01 +00007935 case ISD::SIGN_EXTEND:
7936 case ISD::ZERO_EXTEND:
7937 case ISD::ANY_EXTEND:
7938 return DAGCombineExtBoolTrunc(N, DCI);
7939 case ISD::TRUNCATE:
7940 case ISD::SETCC:
7941 case ISD::SELECT_CC:
7942 return DAGCombineTruncBoolExt(N, DCI);
Hal Finkel2e103312013-04-03 04:01:11 +00007943 case ISD::FDIV: {
7944 assert(TM.Options.UnsafeFPMath &&
7945 "Reciprocal estimates require UnsafeFPMath");
Scott Michelcf0da6c2009-02-17 22:15:04 +00007946
Hal Finkel2e103312013-04-03 04:01:11 +00007947 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
Hal Finkelb0c810f2013-04-03 17:44:56 +00007948 SDValue RV =
7949 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
Craig Topper062a2ba2014-04-25 05:30:21 +00007950 if (RV.getNode()) {
Hal Finkel2e103312013-04-03 04:01:11 +00007951 DCI.AddToWorklist(RV.getNode());
7952 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7953 N->getOperand(0), RV);
7954 }
Hal Finkelf96c18e2013-04-04 22:44:12 +00007955 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7956 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7957 SDValue RV =
7958 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7959 DCI);
Craig Topper062a2ba2014-04-25 05:30:21 +00007960 if (RV.getNode()) {
Hal Finkelf96c18e2013-04-04 22:44:12 +00007961 DCI.AddToWorklist(RV.getNode());
Andrew Trickef9de2a2013-05-25 02:42:55 +00007962 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
Hal Finkelf96c18e2013-04-04 22:44:12 +00007963 N->getValueType(0), RV);
7964 DCI.AddToWorklist(RV.getNode());
7965 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7966 N->getOperand(0), RV);
7967 }
7968 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7969 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7970 SDValue RV =
7971 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7972 DCI);
Craig Topper062a2ba2014-04-25 05:30:21 +00007973 if (RV.getNode()) {
Hal Finkelf96c18e2013-04-04 22:44:12 +00007974 DCI.AddToWorklist(RV.getNode());
Andrew Trickef9de2a2013-05-25 02:42:55 +00007975 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
Hal Finkelf96c18e2013-04-04 22:44:12 +00007976 N->getValueType(0), RV,
7977 N->getOperand(1).getOperand(1));
7978 DCI.AddToWorklist(RV.getNode());
7979 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7980 N->getOperand(0), RV);
7981 }
Hal Finkel2e103312013-04-03 04:01:11 +00007982 }
7983
Hal Finkelb0c810f2013-04-03 17:44:56 +00007984 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
Craig Topper062a2ba2014-04-25 05:30:21 +00007985 if (RV.getNode()) {
Hal Finkel2e103312013-04-03 04:01:11 +00007986 DCI.AddToWorklist(RV.getNode());
7987 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7988 N->getOperand(0), RV);
7989 }
7990
7991 }
7992 break;
7993 case ISD::FSQRT: {
7994 assert(TM.Options.UnsafeFPMath &&
7995 "Reciprocal estimates require UnsafeFPMath");
7996
7997 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7998 // reciprocal sqrt.
Hal Finkelb0c810f2013-04-03 17:44:56 +00007999 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
Craig Topper062a2ba2014-04-25 05:30:21 +00008000 if (RV.getNode()) {
Hal Finkel2e103312013-04-03 04:01:11 +00008001 DCI.AddToWorklist(RV.getNode());
Hal Finkelb0c810f2013-04-03 17:44:56 +00008002 RV = DAGCombineFastRecip(RV, DCI);
Craig Topper062a2ba2014-04-25 05:30:21 +00008003 if (RV.getNode()) {
Eric Christopher174c6622014-05-30 22:47:48 +00008004 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8005 // this case and force the answer to 0.
Hal Finkel1e2e3ea2013-09-12 19:04:12 +00008006
8007 EVT VT = RV.getValueType();
8008
8009 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8010 if (VT.isVector()) {
8011 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8012 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8013 }
8014
8015 SDValue ZeroCmp =
8016 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8017 N->getOperand(0), Zero, ISD::SETEQ);
8018 DCI.AddToWorklist(ZeroCmp.getNode());
8019 DCI.AddToWorklist(RV.getNode());
8020
8021 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8022 ZeroCmp, Zero, RV);
Hal Finkel2e103312013-04-03 04:01:11 +00008023 return RV;
Hal Finkel1e2e3ea2013-09-12 19:04:12 +00008024 }
Hal Finkel2e103312013-04-03 04:01:11 +00008025 }
8026
8027 }
8028 break;
Chris Lattnerf4184352006-03-01 04:57:39 +00008029 case ISD::SINT_TO_FP:
Chris Lattnera35f3062006-06-16 17:34:12 +00008030 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
Chris Lattner4a66d692006-03-22 05:30:33 +00008031 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8032 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8033 // We allow the src/dst to be either f32/f64, but the intermediate
8034 // type must be i64.
Owen Anderson9f944592009-08-11 20:47:22 +00008035 if (N->getOperand(0).getValueType() == MVT::i64 &&
8036 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008037 SDValue Val = N->getOperand(0).getOperand(0);
Owen Anderson9f944592009-08-11 20:47:22 +00008038 if (Val.getValueType() == MVT::f32) {
8039 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
Gabor Greiff304a7a2008-08-28 21:40:38 +00008040 DCI.AddToWorklist(Val.getNode());
Chris Lattner4a66d692006-03-22 05:30:33 +00008041 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008042
Owen Anderson9f944592009-08-11 20:47:22 +00008043 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
Gabor Greiff304a7a2008-08-28 21:40:38 +00008044 DCI.AddToWorklist(Val.getNode());
Owen Anderson9f944592009-08-11 20:47:22 +00008045 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
Gabor Greiff304a7a2008-08-28 21:40:38 +00008046 DCI.AddToWorklist(Val.getNode());
Owen Anderson9f944592009-08-11 20:47:22 +00008047 if (N->getValueType(0) == MVT::f32) {
8048 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
Chris Lattner72733e52008-01-17 07:00:52 +00008049 DAG.getIntPtrConstant(0));
Gabor Greiff304a7a2008-08-28 21:40:38 +00008050 DCI.AddToWorklist(Val.getNode());
Chris Lattner4a66d692006-03-22 05:30:33 +00008051 }
8052 return Val;
Owen Anderson9f944592009-08-11 20:47:22 +00008053 } else if (N->getOperand(0).getValueType() == MVT::i32) {
Chris Lattner4a66d692006-03-22 05:30:33 +00008054 // If the intermediate type is i32, we can avoid the load/store here
8055 // too.
Chris Lattnerf4184352006-03-01 04:57:39 +00008056 }
Chris Lattnerf4184352006-03-01 04:57:39 +00008057 }
8058 }
8059 break;
Chris Lattner27f53452006-03-01 05:50:56 +00008060 case ISD::STORE:
8061 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8062 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
Chris Lattnerf5b46f72008-01-18 16:54:56 +00008063 !cast<StoreSDNode>(N)->isTruncatingStore() &&
Chris Lattner27f53452006-03-01 05:50:56 +00008064 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
Owen Anderson9f944592009-08-11 20:47:22 +00008065 N->getOperand(1).getValueType() == MVT::i32 &&
8066 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008067 SDValue Val = N->getOperand(1).getOperand(0);
Owen Anderson9f944592009-08-11 20:47:22 +00008068 if (Val.getValueType() == MVT::f32) {
8069 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
Gabor Greiff304a7a2008-08-28 21:40:38 +00008070 DCI.AddToWorklist(Val.getNode());
Chris Lattner27f53452006-03-01 05:50:56 +00008071 }
Owen Anderson9f944592009-08-11 20:47:22 +00008072 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
Gabor Greiff304a7a2008-08-28 21:40:38 +00008073 DCI.AddToWorklist(Val.getNode());
Chris Lattner27f53452006-03-01 05:50:56 +00008074
Hal Finkel60c75102013-04-01 15:37:53 +00008075 SDValue Ops[] = {
8076 N->getOperand(0), Val, N->getOperand(2),
8077 DAG.getValueType(N->getOperand(1).getValueType())
8078 };
8079
8080 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
Craig Topper206fcd42014-04-26 19:29:41 +00008081 DAG.getVTList(MVT::Other), Ops,
Hal Finkel60c75102013-04-01 15:37:53 +00008082 cast<StoreSDNode>(N)->getMemoryVT(),
8083 cast<StoreSDNode>(N)->getMemOperand());
Gabor Greiff304a7a2008-08-28 21:40:38 +00008084 DCI.AddToWorklist(Val.getNode());
Chris Lattner27f53452006-03-01 05:50:56 +00008085 return Val;
8086 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008087
Chris Lattnera7976d32006-07-10 20:56:58 +00008088 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
Dan Gohman28328db2009-09-25 00:57:30 +00008089 if (cast<StoreSDNode>(N)->isUnindexed() &&
8090 N->getOperand(1).getOpcode() == ISD::BSWAP &&
Gabor Greiff304a7a2008-08-28 21:40:38 +00008091 N->getOperand(1).getNode()->hasOneUse() &&
Owen Anderson9f944592009-08-11 20:47:22 +00008092 (N->getOperand(1).getValueType() == MVT::i32 ||
Hal Finkel31d29562013-03-28 19:25:55 +00008093 N->getOperand(1).getValueType() == MVT::i16 ||
8094 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
Hal Finkel22e41c42013-03-28 20:23:46 +00008095 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
Hal Finkel31d29562013-03-28 19:25:55 +00008096 N->getOperand(1).getValueType() == MVT::i64))) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008097 SDValue BSwapOp = N->getOperand(1).getOperand(0);
Chris Lattnera7976d32006-07-10 20:56:58 +00008098 // Do an any-extend to 32-bits if this is a half-word input.
Owen Anderson9f944592009-08-11 20:47:22 +00008099 if (BSwapOp.getValueType() == MVT::i16)
8100 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
Chris Lattnera7976d32006-07-10 20:56:58 +00008101
Dan Gohman48b185d2009-09-25 20:36:54 +00008102 SDValue Ops[] = {
8103 N->getOperand(0), BSwapOp, N->getOperand(2),
8104 DAG.getValueType(N->getOperand(1).getValueType())
8105 };
8106 return
8107 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
Craig Topper206fcd42014-04-26 19:29:41 +00008108 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
Dan Gohman48b185d2009-09-25 20:36:54 +00008109 cast<StoreSDNode>(N)->getMemOperand());
Chris Lattnera7976d32006-07-10 20:56:58 +00008110 }
8111 break;
Hal Finkelcf2e9082013-05-24 23:00:14 +00008112 case ISD::LOAD: {
8113 LoadSDNode *LD = cast<LoadSDNode>(N);
8114 EVT VT = LD->getValueType(0);
8115 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8116 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8117 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8118 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
Hal Finkel40c34782013-09-15 22:09:58 +00008119 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8120 VT == MVT::v4i32 || VT == MVT::v4f32) &&
Hal Finkelcf2e9082013-05-24 23:00:14 +00008121 LD->getAlignment() < ABIAlignment) {
8122 // This is a type-legal unaligned Altivec load.
8123 SDValue Chain = LD->getChain();
8124 SDValue Ptr = LD->getBasePtr();
Eric Christopherb1aaebe2014-06-12 22:38:18 +00008125 bool isLittleEndian = Subtarget.isLittleEndian();
Hal Finkelcf2e9082013-05-24 23:00:14 +00008126
8127 // This implements the loading of unaligned vectors as described in
8128 // the venerable Apple Velocity Engine overview. Specifically:
8129 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8130 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8131 //
8132 // The general idea is to expand a sequence of one or more unaligned
Bill Schmidt6b5a7df2014-06-09 22:00:52 +00008133 // loads into an alignment-based permutation-control instruction (lvsl
8134 // or lvsr), a series of regular vector loads (which always truncate
8135 // their input address to an aligned address), and a series of
8136 // permutations. The results of these permutations are the requested
8137 // loaded values. The trick is that the last "extra" load is not taken
8138 // from the address you might suspect (sizeof(vector) bytes after the
8139 // last requested load), but rather sizeof(vector) - 1 bytes after the
8140 // last requested vector. The point of this is to avoid a page fault if
8141 // the base address happened to be aligned. This works because if the
8142 // base address is aligned, then adding less than a full vector length
8143 // will cause the last vector in the sequence to be (re)loaded.
8144 // Otherwise, the next vector will be fetched as you might suspect was
8145 // necessary.
Hal Finkelcf2e9082013-05-24 23:00:14 +00008146
Hal Finkelbc2ee4c2013-05-25 04:05:05 +00008147 // We might be able to reuse the permutation generation from
Hal Finkelcf2e9082013-05-24 23:00:14 +00008148 // a different base address offset from this one by an aligned amount.
Hal Finkelbc2ee4c2013-05-25 04:05:05 +00008149 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8150 // optimization later.
Bill Schmidt6b5a7df2014-06-09 22:00:52 +00008151 Intrinsic::ID Intr = (isLittleEndian ?
8152 Intrinsic::ppc_altivec_lvsr :
8153 Intrinsic::ppc_altivec_lvsl);
8154 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
Hal Finkelcf2e9082013-05-24 23:00:14 +00008155
8156 // Refine the alignment of the original load (a "new" load created here
8157 // which was identical to the first except for the alignment would be
8158 // merged with the existing node regardless).
8159 MachineFunction &MF = DAG.getMachineFunction();
8160 MachineMemOperand *MMO =
8161 MF.getMachineMemOperand(LD->getPointerInfo(),
8162 LD->getMemOperand()->getFlags(),
8163 LD->getMemoryVT().getStoreSize(),
8164 ABIAlignment);
8165 LD->refineAlignment(MMO);
8166 SDValue BaseLoad = SDValue(LD, 0);
8167
8168 // Note that the value of IncOffset (which is provided to the next
8169 // load's pointer info offset value, and thus used to calculate the
8170 // alignment), and the value of IncValue (which is actually used to
8171 // increment the pointer value) are different! This is because we
8172 // require the next load to appear to be aligned, even though it
8173 // is actually offset from the base pointer by a lesser amount.
8174 int IncOffset = VT.getSizeInBits() / 8;
Hal Finkel7d8a6912013-05-26 18:08:30 +00008175 int IncValue = IncOffset;
8176
8177 // Walk (both up and down) the chain looking for another load at the real
8178 // (aligned) offset (the alignment of the other load does not matter in
8179 // this case). If found, then do not use the offset reduction trick, as
8180 // that will prevent the loads from being later combined (as they would
8181 // otherwise be duplicates).
8182 if (!findConsecutiveLoad(LD, DAG))
8183 --IncValue;
8184
Hal Finkelcf2e9082013-05-24 23:00:14 +00008185 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8186 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8187
Hal Finkelcf2e9082013-05-24 23:00:14 +00008188 SDValue ExtraLoad =
8189 DAG.getLoad(VT, dl, Chain, Ptr,
8190 LD->getPointerInfo().getWithOffset(IncOffset),
8191 LD->isVolatile(), LD->isNonTemporal(),
8192 LD->isInvariant(), ABIAlignment);
8193
8194 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8195 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8196
8197 if (BaseLoad.getValueType() != MVT::v4i32)
8198 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8199
8200 if (ExtraLoad.getValueType() != MVT::v4i32)
8201 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8202
Bill Schmidt6b5a7df2014-06-09 22:00:52 +00008203 // Because vperm has a big-endian bias, we must reverse the order
8204 // of the input vectors and complement the permute control vector
8205 // when generating little endian code. We have already handled the
8206 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8207 // and ExtraLoad here.
8208 SDValue Perm;
8209 if (isLittleEndian)
8210 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8211 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8212 else
8213 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8214 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
Hal Finkelcf2e9082013-05-24 23:00:14 +00008215
8216 if (VT != MVT::v4i32)
8217 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8218
8219 // Now we need to be really careful about how we update the users of the
8220 // original load. We cannot just call DCI.CombineTo (or
8221 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8222 // uses created here (the permutation for example) that need to stay.
8223 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8224 while (UI != UE) {
8225 SDUse &Use = UI.getUse();
8226 SDNode *User = *UI;
8227 // Note: BaseLoad is checked here because it might not be N, but a
8228 // bitcast of N.
8229 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8230 User == TF.getNode() || Use.getResNo() > 1) {
8231 ++UI;
8232 continue;
8233 }
8234
8235 SDValue To = Use.getResNo() ? TF : Perm;
8236 ++UI;
8237
8238 SmallVector<SDValue, 8> Ops;
Craig Topper66e588b2014-06-29 00:40:57 +00008239 for (const SDUse &O : User->ops()) {
8240 if (O == Use)
Hal Finkelcf2e9082013-05-24 23:00:14 +00008241 Ops.push_back(To);
8242 else
Craig Topper66e588b2014-06-29 00:40:57 +00008243 Ops.push_back(O);
Hal Finkelcf2e9082013-05-24 23:00:14 +00008244 }
8245
Craig Topper8c0b4d02014-04-28 05:57:50 +00008246 DAG.UpdateNodeOperands(User, Ops);
Hal Finkelcf2e9082013-05-24 23:00:14 +00008247 }
8248
8249 return SDValue(N, 0);
8250 }
8251 }
8252 break;
Bill Schmidt6b5a7df2014-06-09 22:00:52 +00008253 case ISD::INTRINSIC_WO_CHAIN: {
Eric Christopherb1aaebe2014-06-12 22:38:18 +00008254 bool isLittleEndian = Subtarget.isLittleEndian();
Bill Schmidt6b5a7df2014-06-09 22:00:52 +00008255 Intrinsic::ID Intr = (isLittleEndian ?
8256 Intrinsic::ppc_altivec_lvsr :
8257 Intrinsic::ppc_altivec_lvsl);
8258 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
Hal Finkelbc2ee4c2013-05-25 04:05:05 +00008259 N->getOperand(1)->getOpcode() == ISD::ADD) {
8260 SDValue Add = N->getOperand(1);
8261
8262 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8263 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8264 Add.getValueType().getScalarType().getSizeInBits()))) {
8265 SDNode *BasePtr = Add->getOperand(0).getNode();
8266 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8267 UE = BasePtr->use_end(); UI != UE; ++UI) {
8268 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8269 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
Bill Schmidt6b5a7df2014-06-09 22:00:52 +00008270 Intr) {
8271 // We've found another LVSL/LVSR, and this address is an aligned
Hal Finkelbc2ee4c2013-05-25 04:05:05 +00008272 // multiple of that one. The results will be the same, so use the
8273 // one we've just found instead.
8274
8275 return SDValue(*UI, 0);
8276 }
8277 }
8278 }
8279 }
Bill Schmidt6b5a7df2014-06-09 22:00:52 +00008280 }
Hal Finkelc3cfbf82013-09-13 20:09:02 +00008281
8282 break;
Chris Lattnera7976d32006-07-10 20:56:58 +00008283 case ISD::BSWAP:
8284 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
Gabor Greiff304a7a2008-08-28 21:40:38 +00008285 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
Chris Lattnera7976d32006-07-10 20:56:58 +00008286 N->getOperand(0).hasOneUse() &&
Hal Finkel31d29562013-03-28 19:25:55 +00008287 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8288 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
Hal Finkel22e41c42013-03-28 20:23:46 +00008289 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
Hal Finkel31d29562013-03-28 19:25:55 +00008290 N->getValueType(0) == MVT::i64))) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008291 SDValue Load = N->getOperand(0);
Evan Chenge71fe34d2006-10-09 20:57:25 +00008292 LoadSDNode *LD = cast<LoadSDNode>(Load);
Chris Lattnera7976d32006-07-10 20:56:58 +00008293 // Create the byte-swapping load.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008294 SDValue Ops[] = {
Evan Chenge71fe34d2006-10-09 20:57:25 +00008295 LD->getChain(), // Chain
8296 LD->getBasePtr(), // Ptr
Chris Lattnerd66f14e2006-08-11 17:18:05 +00008297 DAG.getValueType(N->getValueType(0)) // VT
8298 };
Dan Gohman48b185d2009-09-25 20:36:54 +00008299 SDValue BSLoad =
8300 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
Hal Finkel31d29562013-03-28 19:25:55 +00008301 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8302 MVT::i64 : MVT::i32, MVT::Other),
Craig Topper206fcd42014-04-26 19:29:41 +00008303 Ops, LD->getMemoryVT(), LD->getMemOperand());
Chris Lattnera7976d32006-07-10 20:56:58 +00008304
Scott Michelcf0da6c2009-02-17 22:15:04 +00008305 // If this is an i16 load, insert the truncate.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008306 SDValue ResVal = BSLoad;
Owen Anderson9f944592009-08-11 20:47:22 +00008307 if (N->getValueType(0) == MVT::i16)
8308 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
Scott Michelcf0da6c2009-02-17 22:15:04 +00008309
Chris Lattnera7976d32006-07-10 20:56:58 +00008310 // First, combine the bswap away. This makes the value produced by the
8311 // load dead.
8312 DCI.CombineTo(N, ResVal);
8313
8314 // Next, combine the load away, we give it a bogus result value but a real
8315 // chain result. The result value is dead because the bswap is dead.
Gabor Greiff304a7a2008-08-28 21:40:38 +00008316 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
Scott Michelcf0da6c2009-02-17 22:15:04 +00008317
Chris Lattnera7976d32006-07-10 20:56:58 +00008318 // Return N so it doesn't get rechecked!
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008319 return SDValue(N, 0);
Chris Lattnera7976d32006-07-10 20:56:58 +00008320 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008321
Chris Lattner27f53452006-03-01 05:50:56 +00008322 break;
Chris Lattnerd4058a52006-03-31 06:02:07 +00008323 case PPCISD::VCMP: {
8324 // If a VCMPo node already exists with exactly the same operands as this
8325 // node, use its result instead of this node (VCMPo computes both a CR6 and
8326 // a normal output).
8327 //
8328 if (!N->getOperand(0).hasOneUse() &&
8329 !N->getOperand(1).hasOneUse() &&
8330 !N->getOperand(2).hasOneUse()) {
Scott Michelcf0da6c2009-02-17 22:15:04 +00008331
Chris Lattnerd4058a52006-03-31 06:02:07 +00008332 // Scan all of the users of the LHS, looking for VCMPo's that match.
Craig Topper062a2ba2014-04-25 05:30:21 +00008333 SDNode *VCMPoNode = nullptr;
Scott Michelcf0da6c2009-02-17 22:15:04 +00008334
Gabor Greiff304a7a2008-08-28 21:40:38 +00008335 SDNode *LHSN = N->getOperand(0).getNode();
Chris Lattnerd4058a52006-03-31 06:02:07 +00008336 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8337 UI != E; ++UI)
Dan Gohman91e5dcb2008-07-27 20:43:25 +00008338 if (UI->getOpcode() == PPCISD::VCMPo &&
8339 UI->getOperand(1) == N->getOperand(1) &&
8340 UI->getOperand(2) == N->getOperand(2) &&
8341 UI->getOperand(0) == N->getOperand(0)) {
8342 VCMPoNode = *UI;
Chris Lattnerd4058a52006-03-31 06:02:07 +00008343 break;
8344 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008345
Chris Lattner518834c2006-04-18 18:28:22 +00008346 // If there is no VCMPo node, or if the flag value has a single use, don't
8347 // transform this.
8348 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8349 break;
Scott Michelcf0da6c2009-02-17 22:15:04 +00008350
8351 // Look at the (necessarily single) use of the flag value. If it has a
Chris Lattner518834c2006-04-18 18:28:22 +00008352 // chain, this transformation is more complex. Note that multiple things
8353 // could use the value result, which we should ignore.
Craig Topper062a2ba2014-04-25 05:30:21 +00008354 SDNode *FlagUser = nullptr;
Scott Michelcf0da6c2009-02-17 22:15:04 +00008355 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
Craig Topper062a2ba2014-04-25 05:30:21 +00008356 FlagUser == nullptr; ++UI) {
Chris Lattner518834c2006-04-18 18:28:22 +00008357 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
Dan Gohman91e5dcb2008-07-27 20:43:25 +00008358 SDNode *User = *UI;
Chris Lattner518834c2006-04-18 18:28:22 +00008359 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008360 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
Chris Lattner518834c2006-04-18 18:28:22 +00008361 FlagUser = User;
8362 break;
8363 }
8364 }
8365 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008366
Ulrich Weigandd5ebc622013-07-03 17:05:42 +00008367 // If the user is a MFOCRF instruction, we know this is safe.
8368 // Otherwise we give up for right now.
8369 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008370 return SDValue(VCMPoNode, 0);
Chris Lattnerd4058a52006-03-31 06:02:07 +00008371 }
8372 break;
8373 }
Hal Finkel940ab932014-02-28 00:27:01 +00008374 case ISD::BRCOND: {
8375 SDValue Cond = N->getOperand(1);
8376 SDValue Target = N->getOperand(2);
8377
8378 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8379 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8380 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8381
8382 // We now need to make the intrinsic dead (it cannot be instruction
8383 // selected).
8384 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8385 assert(Cond.getNode()->hasOneUse() &&
8386 "Counter decrement has more than one use");
8387
8388 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8389 N->getOperand(0), Target);
8390 }
8391 }
8392 break;
Chris Lattner9754d142006-04-18 17:59:36 +00008393 case ISD::BR_CC: {
8394 // If this is a branch on an altivec predicate comparison, lower this so
Ulrich Weigandd5ebc622013-07-03 17:05:42 +00008395 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
Chris Lattner9754d142006-04-18 17:59:36 +00008396 // lowering is done pre-legalize, because the legalizer lowers the predicate
8397 // compare down to code that is difficult to reassemble.
8398 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008399 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
Hal Finkel25c19922013-05-15 21:37:41 +00008400
8401 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8402 // value. If so, pass-through the AND to get to the intrinsic.
8403 if (LHS.getOpcode() == ISD::AND &&
8404 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8405 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8406 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8407 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8408 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8409 isZero())
8410 LHS = LHS.getOperand(0);
8411
8412 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8413 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8414 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8415 isa<ConstantSDNode>(RHS)) {
8416 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8417 "Counter decrement comparison is not EQ or NE");
8418
8419 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8420 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8421 (CC == ISD::SETNE && !Val);
8422
8423 // We now need to make the intrinsic dead (it cannot be instruction
8424 // selected).
8425 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8426 assert(LHS.getNode()->hasOneUse() &&
8427 "Counter decrement has more than one use");
8428
8429 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8430 N->getOperand(0), N->getOperand(4));
8431 }
8432
Chris Lattner9754d142006-04-18 17:59:36 +00008433 int CompareOpc;
8434 bool isDot;
Scott Michelcf0da6c2009-02-17 22:15:04 +00008435
Chris Lattner9754d142006-04-18 17:59:36 +00008436 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8437 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8438 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8439 assert(isDot && "Can't compare against a vector result!");
Scott Michelcf0da6c2009-02-17 22:15:04 +00008440
Chris Lattner9754d142006-04-18 17:59:36 +00008441 // If this is a comparison against something other than 0/1, then we know
8442 // that the condition is never/always true.
Dan Gohmaneffb8942008-09-12 16:56:44 +00008443 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
Chris Lattner9754d142006-04-18 17:59:36 +00008444 if (Val != 0 && Val != 1) {
8445 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8446 return N->getOperand(0);
8447 // Always !=, turn it into an unconditional branch.
Owen Anderson9f944592009-08-11 20:47:22 +00008448 return DAG.getNode(ISD::BR, dl, MVT::Other,
Chris Lattner9754d142006-04-18 17:59:36 +00008449 N->getOperand(0), N->getOperand(4));
8450 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008451
Chris Lattner9754d142006-04-18 17:59:36 +00008452 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
Scott Michelcf0da6c2009-02-17 22:15:04 +00008453
Chris Lattner9754d142006-04-18 17:59:36 +00008454 // Create the PPCISD altivec 'dot' comparison node.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008455 SDValue Ops[] = {
Chris Lattnerd66f14e2006-08-11 17:18:05 +00008456 LHS.getOperand(2), // LHS of compare
8457 LHS.getOperand(3), // RHS of compare
Owen Anderson9f944592009-08-11 20:47:22 +00008458 DAG.getConstant(CompareOpc, MVT::i32)
Chris Lattnerd66f14e2006-08-11 17:18:05 +00008459 };
Benjamin Kramerfdf362b2013-03-07 20:33:29 +00008460 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
Craig Topper48d114b2014-04-26 18:35:24 +00008461 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
Scott Michelcf0da6c2009-02-17 22:15:04 +00008462
Chris Lattner9754d142006-04-18 17:59:36 +00008463 // Unpack the result based on how the target uses it.
Chris Lattner8c6a41e2006-11-17 22:10:59 +00008464 PPC::Predicate CompOpc;
Dan Gohmaneffb8942008-09-12 16:56:44 +00008465 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
Chris Lattner9754d142006-04-18 17:59:36 +00008466 default: // Can't happen, don't crash on invalid number though.
8467 case 0: // Branch on the value of the EQ bit of CR6.
Chris Lattner8c6a41e2006-11-17 22:10:59 +00008468 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
Chris Lattner9754d142006-04-18 17:59:36 +00008469 break;
8470 case 1: // Branch on the inverted value of the EQ bit of CR6.
Chris Lattner8c6a41e2006-11-17 22:10:59 +00008471 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
Chris Lattner9754d142006-04-18 17:59:36 +00008472 break;
8473 case 2: // Branch on the value of the LT bit of CR6.
Chris Lattner8c6a41e2006-11-17 22:10:59 +00008474 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
Chris Lattner9754d142006-04-18 17:59:36 +00008475 break;
8476 case 3: // Branch on the inverted value of the LT bit of CR6.
Chris Lattner8c6a41e2006-11-17 22:10:59 +00008477 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
Chris Lattner9754d142006-04-18 17:59:36 +00008478 break;
8479 }
8480
Owen Anderson9f944592009-08-11 20:47:22 +00008481 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8482 DAG.getConstant(CompOpc, MVT::i32),
8483 DAG.getRegister(PPC::CR6, MVT::i32),
Chris Lattner9754d142006-04-18 17:59:36 +00008484 N->getOperand(4), CompNode.getValue(1));
8485 }
8486 break;
8487 }
Chris Lattnerf4184352006-03-01 04:57:39 +00008488 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008489
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008490 return SDValue();
Chris Lattnerf4184352006-03-01 04:57:39 +00008491}
8492
Chris Lattner4211ca92006-04-14 06:01:58 +00008493//===----------------------------------------------------------------------===//
8494// Inline Assembly Support
8495//===----------------------------------------------------------------------===//
8496
Jay Foada0653a32014-05-14 21:14:37 +00008497void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8498 APInt &KnownZero,
8499 APInt &KnownOne,
8500 const SelectionDAG &DAG,
8501 unsigned Depth) const {
Rafael Espindolaba0a6ca2012-04-04 12:51:34 +00008502 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
Chris Lattnerc5287c02006-04-02 06:26:07 +00008503 switch (Op.getOpcode()) {
8504 default: break;
Chris Lattnera7976d32006-07-10 20:56:58 +00008505 case PPCISD::LBRX: {
8506 // lhbrx is known to have the top bits cleared out.
Dan Gohmana5fc0352009-09-27 23:17:47 +00008507 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
Chris Lattnera7976d32006-07-10 20:56:58 +00008508 KnownZero = 0xFFFF0000;
8509 break;
8510 }
Chris Lattnerc5287c02006-04-02 06:26:07 +00008511 case ISD::INTRINSIC_WO_CHAIN: {
Dan Gohmaneffb8942008-09-12 16:56:44 +00008512 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
Chris Lattnerc5287c02006-04-02 06:26:07 +00008513 default: break;
8514 case Intrinsic::ppc_altivec_vcmpbfp_p:
8515 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8516 case Intrinsic::ppc_altivec_vcmpequb_p:
8517 case Intrinsic::ppc_altivec_vcmpequh_p:
8518 case Intrinsic::ppc_altivec_vcmpequw_p:
8519 case Intrinsic::ppc_altivec_vcmpgefp_p:
8520 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8521 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8522 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8523 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8524 case Intrinsic::ppc_altivec_vcmpgtub_p:
8525 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8526 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8527 KnownZero = ~1U; // All bits but the low one are known to be zero.
8528 break;
Scott Michelcf0da6c2009-02-17 22:15:04 +00008529 }
Chris Lattnerc5287c02006-04-02 06:26:07 +00008530 }
8531 }
8532}
8533
8534
Chris Lattnerd6855142007-03-25 02:14:49 +00008535/// getConstraintType - Given a constraint, return the type of
Chris Lattner203b2f12006-02-07 20:16:30 +00008536/// constraint it is for this target.
Scott Michelcf0da6c2009-02-17 22:15:04 +00008537PPCTargetLowering::ConstraintType
Chris Lattnerd6855142007-03-25 02:14:49 +00008538PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8539 if (Constraint.size() == 1) {
8540 switch (Constraint[0]) {
8541 default: break;
8542 case 'b':
8543 case 'r':
8544 case 'f':
8545 case 'v':
8546 case 'y':
8547 return C_RegisterClass;
Hal Finkel4f24c622012-11-05 18:18:42 +00008548 case 'Z':
8549 // FIXME: While Z does indicate a memory constraint, it specifically
8550 // indicates an r+r address (used in conjunction with the 'y' modifier
8551 // in the replacement string). Currently, we're forcing the base
8552 // register to be r0 in the asm printer (which is interpreted as zero)
8553 // and forming the complete address in the second register. This is
8554 // suboptimal.
8555 return C_Memory;
Chris Lattnerd6855142007-03-25 02:14:49 +00008556 }
Hal Finkel6aca2372014-03-02 18:23:39 +00008557 } else if (Constraint == "wc") { // individual CR bits.
8558 return C_RegisterClass;
Hal Finkel27774d92014-03-13 07:58:58 +00008559 } else if (Constraint == "wa" || Constraint == "wd" ||
8560 Constraint == "wf" || Constraint == "ws") {
8561 return C_RegisterClass; // VSX registers.
Chris Lattnerd6855142007-03-25 02:14:49 +00008562 }
8563 return TargetLowering::getConstraintType(Constraint);
Chris Lattner203b2f12006-02-07 20:16:30 +00008564}
8565
John Thompsone8360b72010-10-29 17:29:13 +00008566/// Examine constraint type and operand type and determine a weight value.
8567/// This object must already have been set up with the operand type
8568/// and the current alternative constraint selected.
8569TargetLowering::ConstraintWeight
8570PPCTargetLowering::getSingleConstraintMatchWeight(
8571 AsmOperandInfo &info, const char *constraint) const {
8572 ConstraintWeight weight = CW_Invalid;
8573 Value *CallOperandVal = info.CallOperandVal;
8574 // If we don't have a value, we can't do a match,
8575 // but allow it at the lowest weight.
Craig Topper062a2ba2014-04-25 05:30:21 +00008576 if (!CallOperandVal)
John Thompsone8360b72010-10-29 17:29:13 +00008577 return CW_Default;
Chris Lattner229907c2011-07-18 04:54:35 +00008578 Type *type = CallOperandVal->getType();
Hal Finkel6aca2372014-03-02 18:23:39 +00008579
John Thompsone8360b72010-10-29 17:29:13 +00008580 // Look at the constraint type.
Hal Finkel6aca2372014-03-02 18:23:39 +00008581 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8582 return CW_Register; // an individual CR bit.
Hal Finkel27774d92014-03-13 07:58:58 +00008583 else if ((StringRef(constraint) == "wa" ||
8584 StringRef(constraint) == "wd" ||
8585 StringRef(constraint) == "wf") &&
8586 type->isVectorTy())
8587 return CW_Register;
8588 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8589 return CW_Register;
Hal Finkel6aca2372014-03-02 18:23:39 +00008590
John Thompsone8360b72010-10-29 17:29:13 +00008591 switch (*constraint) {
8592 default:
8593 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8594 break;
8595 case 'b':
8596 if (type->isIntegerTy())
8597 weight = CW_Register;
8598 break;
8599 case 'f':
8600 if (type->isFloatTy())
8601 weight = CW_Register;
8602 break;
8603 case 'd':
8604 if (type->isDoubleTy())
8605 weight = CW_Register;
8606 break;
8607 case 'v':
8608 if (type->isVectorTy())
8609 weight = CW_Register;
8610 break;
8611 case 'y':
8612 weight = CW_Register;
8613 break;
Hal Finkel4f24c622012-11-05 18:18:42 +00008614 case 'Z':
8615 weight = CW_Memory;
8616 break;
John Thompsone8360b72010-10-29 17:29:13 +00008617 }
8618 return weight;
8619}
8620
Scott Michelcf0da6c2009-02-17 22:15:04 +00008621std::pair<unsigned, const TargetRegisterClass*>
Chris Lattner584a11a2006-11-02 01:44:04 +00008622PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Chad Rosier295bd432013-06-22 18:37:38 +00008623 MVT VT) const {
Chris Lattner01513612006-01-31 19:20:21 +00008624 if (Constraint.size() == 1) {
Chris Lattner584a11a2006-11-02 01:44:04 +00008625 // GCC RS6000 Constraint Letters
8626 switch (Constraint[0]) {
8627 case 'b': // R1-R31
Eric Christopherb1aaebe2014-06-12 22:38:18 +00008628 if (VT == MVT::i64 && Subtarget.isPPC64())
Hal Finkel638a9fa2013-03-19 18:51:05 +00008629 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8630 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
Chris Lattner584a11a2006-11-02 01:44:04 +00008631 case 'r': // R0-R31
Eric Christopherb1aaebe2014-06-12 22:38:18 +00008632 if (VT == MVT::i64 && Subtarget.isPPC64())
Craig Topperabadc662012-04-20 06:31:50 +00008633 return std::make_pair(0U, &PPC::G8RCRegClass);
8634 return std::make_pair(0U, &PPC::GPRCRegClass);
Chris Lattner584a11a2006-11-02 01:44:04 +00008635 case 'f':
Ulrich Weigand0de4a1e2012-10-29 17:49:34 +00008636 if (VT == MVT::f32 || VT == MVT::i32)
Craig Topperabadc662012-04-20 06:31:50 +00008637 return std::make_pair(0U, &PPC::F4RCRegClass);
Ulrich Weigand0de4a1e2012-10-29 17:49:34 +00008638 if (VT == MVT::f64 || VT == MVT::i64)
Craig Topperabadc662012-04-20 06:31:50 +00008639 return std::make_pair(0U, &PPC::F8RCRegClass);
Chris Lattner584a11a2006-11-02 01:44:04 +00008640 break;
Scott Michelcf0da6c2009-02-17 22:15:04 +00008641 case 'v':
Craig Topperabadc662012-04-20 06:31:50 +00008642 return std::make_pair(0U, &PPC::VRRCRegClass);
Chris Lattner584a11a2006-11-02 01:44:04 +00008643 case 'y': // crrc
Craig Topperabadc662012-04-20 06:31:50 +00008644 return std::make_pair(0U, &PPC::CRRCRegClass);
Chris Lattner01513612006-01-31 19:20:21 +00008645 }
Hal Finkel6aca2372014-03-02 18:23:39 +00008646 } else if (Constraint == "wc") { // an individual CR bit.
8647 return std::make_pair(0U, &PPC::CRBITRCRegClass);
Hal Finkel27774d92014-03-13 07:58:58 +00008648 } else if (Constraint == "wa" || Constraint == "wd" ||
Hal Finkel19be5062014-03-29 05:29:01 +00008649 Constraint == "wf") {
Hal Finkel27774d92014-03-13 07:58:58 +00008650 return std::make_pair(0U, &PPC::VSRCRegClass);
Hal Finkel19be5062014-03-29 05:29:01 +00008651 } else if (Constraint == "ws") {
8652 return std::make_pair(0U, &PPC::VSFRCRegClass);
Chris Lattner01513612006-01-31 19:20:21 +00008653 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008654
Hal Finkelb176acb2013-08-03 12:25:10 +00008655 std::pair<unsigned, const TargetRegisterClass*> R =
8656 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8657
8658 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8659 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8660 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8661 // register.
8662 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8663 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
Eric Christopherb1aaebe2014-06-12 22:38:18 +00008664 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
Hal Finkelb176acb2013-08-03 12:25:10 +00008665 PPC::GPRCRegClass.contains(R.first)) {
8666 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8667 return std::make_pair(TRI->getMatchingSuperReg(R.first,
Hal Finkelb3ca00d2013-08-14 20:05:04 +00008668 PPC::sub_32, &PPC::G8RCRegClass),
Hal Finkelb176acb2013-08-03 12:25:10 +00008669 &PPC::G8RCRegClass);
8670 }
8671
8672 return R;
Chris Lattner01513612006-01-31 19:20:21 +00008673}
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008674
Chris Lattner584a11a2006-11-02 01:44:04 +00008675
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00008676/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
Dale Johannesence97d552010-06-25 21:55:36 +00008677/// vector. If it is invalid, don't add anything to Ops.
Eric Christopher0713a9d2011-06-08 23:55:35 +00008678void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Eric Christopherde9399b2011-06-02 23:16:42 +00008679 std::string &Constraint,
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008680 std::vector<SDValue>&Ops,
Chris Lattner724539c2008-04-26 23:02:14 +00008681 SelectionDAG &DAG) const {
Craig Topper062a2ba2014-04-25 05:30:21 +00008682 SDValue Result;
Eric Christopher0713a9d2011-06-08 23:55:35 +00008683
Eric Christopherde9399b2011-06-02 23:16:42 +00008684 // Only support length 1 constraints.
8685 if (Constraint.length() > 1) return;
Eric Christopher0713a9d2011-06-08 23:55:35 +00008686
Eric Christopherde9399b2011-06-02 23:16:42 +00008687 char Letter = Constraint[0];
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008688 switch (Letter) {
8689 default: break;
8690 case 'I':
8691 case 'J':
8692 case 'K':
8693 case 'L':
8694 case 'M':
8695 case 'N':
8696 case 'O':
8697 case 'P': {
Chris Lattner0b7472d2007-05-15 01:31:05 +00008698 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00008699 if (!CST) return; // Must be an immediate to match.
Dan Gohmaneffb8942008-09-12 16:56:44 +00008700 unsigned Value = CST->getZExtValue();
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008701 switch (Letter) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00008702 default: llvm_unreachable("Unknown constraint letter!");
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008703 case 'I': // "I" is a signed 16-bit constant.
Chris Lattner0b7472d2007-05-15 01:31:05 +00008704 if ((short)Value == (int)Value)
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00008705 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattner8c6949e2006-10-31 19:40:43 +00008706 break;
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008707 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8708 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
Chris Lattner0b7472d2007-05-15 01:31:05 +00008709 if ((short)Value == 0)
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00008710 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattner8c6949e2006-10-31 19:40:43 +00008711 break;
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008712 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
Chris Lattner0b7472d2007-05-15 01:31:05 +00008713 if ((Value >> 16) == 0)
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00008714 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattner8c6949e2006-10-31 19:40:43 +00008715 break;
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008716 case 'M': // "M" is a constant that is greater than 31.
Chris Lattner0b7472d2007-05-15 01:31:05 +00008717 if (Value > 31)
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00008718 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattner8c6949e2006-10-31 19:40:43 +00008719 break;
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008720 case 'N': // "N" is a positive constant that is an exact power of two.
Chris Lattner0b7472d2007-05-15 01:31:05 +00008721 if ((int)Value > 0 && isPowerOf2_32(Value))
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00008722 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattner8c6949e2006-10-31 19:40:43 +00008723 break;
Scott Michelcf0da6c2009-02-17 22:15:04 +00008724 case 'O': // "O" is the constant zero.
Chris Lattner0b7472d2007-05-15 01:31:05 +00008725 if (Value == 0)
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00008726 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattner8c6949e2006-10-31 19:40:43 +00008727 break;
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008728 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
Chris Lattner0b7472d2007-05-15 01:31:05 +00008729 if ((short)-Value == (int)-Value)
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00008730 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattner8c6949e2006-10-31 19:40:43 +00008731 break;
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008732 }
8733 break;
8734 }
8735 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008736
Gabor Greiff304a7a2008-08-28 21:40:38 +00008737 if (Result.getNode()) {
Chris Lattnerd8c9cb92007-08-25 00:47:38 +00008738 Ops.push_back(Result);
8739 return;
8740 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008741
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008742 // Handle standard constraint letters.
Eric Christopherde9399b2011-06-02 23:16:42 +00008743 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
Chris Lattner15a6c4c2006-02-07 00:47:13 +00008744}
Evan Cheng2dd2c652006-03-13 23:20:37 +00008745
Chris Lattner1eb94d92007-03-30 23:15:24 +00008746// isLegalAddressingMode - Return true if the addressing mode represented
8747// by AM is legal for this target, for a load/store of the specified type.
Scott Michelcf0da6c2009-02-17 22:15:04 +00008748bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattner229907c2011-07-18 04:54:35 +00008749 Type *Ty) const {
Chris Lattner1eb94d92007-03-30 23:15:24 +00008750 // FIXME: PPC does not allow r+i addressing modes for vectors!
Scott Michelcf0da6c2009-02-17 22:15:04 +00008751
Chris Lattner1eb94d92007-03-30 23:15:24 +00008752 // PPC allows a sign-extended 16-bit immediate field.
8753 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8754 return false;
Scott Michelcf0da6c2009-02-17 22:15:04 +00008755
Chris Lattner1eb94d92007-03-30 23:15:24 +00008756 // No global is ever allowed as a base.
8757 if (AM.BaseGV)
8758 return false;
Scott Michelcf0da6c2009-02-17 22:15:04 +00008759
8760 // PPC only support r+r,
Chris Lattner1eb94d92007-03-30 23:15:24 +00008761 switch (AM.Scale) {
8762 case 0: // "r+i" or just "i", depending on HasBaseReg.
8763 break;
8764 case 1:
8765 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8766 return false;
8767 // Otherwise we have r+r or r+i.
8768 break;
8769 case 2:
8770 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8771 return false;
8772 // Allow 2*r as r+r.
8773 break;
Chris Lattner19ccd622007-04-09 22:10:05 +00008774 default:
8775 // No other scales are supported.
8776 return false;
Chris Lattner1eb94d92007-03-30 23:15:24 +00008777 }
Scott Michelcf0da6c2009-02-17 22:15:04 +00008778
Chris Lattner1eb94d92007-03-30 23:15:24 +00008779 return true;
8780}
8781
Dan Gohman21cea8a2010-04-17 15:26:15 +00008782SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8783 SelectionDAG &DAG) const {
Evan Cheng168ced92010-05-22 01:47:14 +00008784 MachineFunction &MF = DAG.getMachineFunction();
8785 MachineFrameInfo *MFI = MF.getFrameInfo();
8786 MFI->setReturnAddressIsTaken(true);
8787
Bill Wendling908bf812014-01-06 00:43:20 +00008788 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
Bill Wendlingdf7dd282014-01-05 01:47:20 +00008789 return SDValue();
Bill Wendlingdf7dd282014-01-05 01:47:20 +00008790
Andrew Trickef9de2a2013-05-25 02:42:55 +00008791 SDLoc dl(Op);
Dale Johannesen81bfca72010-05-03 22:59:34 +00008792 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
Chris Lattnerf6a81562007-12-08 06:59:59 +00008793
Dale Johannesen81bfca72010-05-03 22:59:34 +00008794 // Make sure the function does not optimize away the store of the RA to
8795 // the stack.
Chris Lattnerf6a81562007-12-08 06:59:59 +00008796 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
Dale Johannesen81bfca72010-05-03 22:59:34 +00008797 FuncInfo->setLRStoreRequired();
Eric Christopherb1aaebe2014-06-12 22:38:18 +00008798 bool isPPC64 = Subtarget.isPPC64();
8799 bool isDarwinABI = Subtarget.isDarwinABI();
Dale Johannesen81bfca72010-05-03 22:59:34 +00008800
8801 if (Depth > 0) {
8802 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8803 SDValue Offset =
Wesley Peck527da1b2010-11-23 03:31:01 +00008804
Anton Korobeynikov2f931282011-01-10 12:39:04 +00008805 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
Dale Johannesen81bfca72010-05-03 22:59:34 +00008806 isPPC64? MVT::i64 : MVT::i32);
8807 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8808 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8809 FrameAddr, Offset),
Pete Cooper82cd9e82011-11-08 18:42:53 +00008810 MachinePointerInfo(), false, false, false, 0);
Dale Johannesen81bfca72010-05-03 22:59:34 +00008811 }
Chris Lattnerf6a81562007-12-08 06:59:59 +00008812
Chris Lattnerf6a81562007-12-08 06:59:59 +00008813 // Just load the return address off the stack.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +00008814 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
Dale Johannesen81bfca72010-05-03 22:59:34 +00008815 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00008816 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
Chris Lattnerf6a81562007-12-08 06:59:59 +00008817}
8818
Dan Gohman21cea8a2010-04-17 15:26:15 +00008819SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8820 SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +00008821 SDLoc dl(Op);
Dale Johannesen81bfca72010-05-03 22:59:34 +00008822 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
Scott Michelcf0da6c2009-02-17 22:15:04 +00008823
Owen Anderson53aa7a92009-08-10 22:56:29 +00008824 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Owen Anderson9f944592009-08-11 20:47:22 +00008825 bool isPPC64 = PtrVT == MVT::i64;
Scott Michelcf0da6c2009-02-17 22:15:04 +00008826
Nicolas Geoffray75ab9792007-03-01 13:11:38 +00008827 MachineFunction &MF = DAG.getMachineFunction();
8828 MachineFrameInfo *MFI = MF.getFrameInfo();
Dale Johannesen81bfca72010-05-03 22:59:34 +00008829 MFI->setFrameAddressIsTaken(true);
Hal Finkelaa03c032013-03-21 19:03:19 +00008830
8831 // Naked functions never have a frame pointer, and so we use r1. For all
8832 // other functions, this decision must be delayed until during PEI.
8833 unsigned FrameReg;
8834 if (MF.getFunction()->getAttributes().hasAttribute(
8835 AttributeSet::FunctionIndex, Attribute::Naked))
8836 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8837 else
8838 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8839
Dale Johannesen81bfca72010-05-03 22:59:34 +00008840 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8841 PtrVT);
8842 while (Depth--)
8843 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
Pete Cooper82cd9e82011-11-08 18:42:53 +00008844 FrameAddr, MachinePointerInfo(), false, false,
8845 false, 0);
Dale Johannesen81bfca72010-05-03 22:59:34 +00008846 return FrameAddr;
Nicolas Geoffray75ab9792007-03-01 13:11:38 +00008847}
Dan Gohmanc14e5222008-10-21 03:41:46 +00008848
Hal Finkel0d8db462014-05-11 19:29:11 +00008849// FIXME? Maybe this could be a TableGen attribute on some registers and
8850// this table could be generated automatically from RegInfo.
8851unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
8852 EVT VT) const {
Eric Christopherb1aaebe2014-06-12 22:38:18 +00008853 bool isPPC64 = Subtarget.isPPC64();
8854 bool isDarwinABI = Subtarget.isDarwinABI();
Hal Finkel0d8db462014-05-11 19:29:11 +00008855
8856 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
8857 (!isPPC64 && VT != MVT::i32))
8858 report_fatal_error("Invalid register global variable type");
8859
8860 bool is64Bit = isPPC64 && VT == MVT::i64;
8861 unsigned Reg = StringSwitch<unsigned>(RegName)
8862 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
8863 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
8864 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
8865 (is64Bit ? PPC::X13 : PPC::R13))
8866 .Default(0);
8867
8868 if (Reg)
8869 return Reg;
8870 report_fatal_error("Invalid register name global variable");
8871}
8872
Dan Gohmanc14e5222008-10-21 03:41:46 +00008873bool
8874PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8875 // The PowerPC target isn't yet aware of offsets.
8876 return false;
8877}
Tilmann Schellerb93960d2009-07-03 06:45:56 +00008878
Evan Chengd9929f02010-04-01 20:10:42 +00008879/// getOptimalMemOpType - Returns the target specific optimal type for load
Evan Cheng61399372010-04-02 19:36:14 +00008880/// and store operations as a result of memset, memcpy, and memmove
8881/// lowering. If DstAlign is zero that means it's safe to destination
8882/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8883/// means there isn't a need to check it against alignment requirement,
Evan Cheng962711e2012-12-12 02:34:41 +00008884/// probably because the source does not need to be loaded. If 'IsMemset' is
8885/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8886/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8887/// source is constant so it does not need to be loaded.
Dan Gohman148c69a2010-04-16 20:11:05 +00008888/// It returns EVT::Other if the type should be determined using generic
8889/// target-independent logic.
Evan Cheng43cd9e32010-04-01 06:04:33 +00008890EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8891 unsigned DstAlign, unsigned SrcAlign,
Evan Cheng962711e2012-12-12 02:34:41 +00008892 bool IsMemset, bool ZeroMemset,
Evan Chengebe47c82010-04-08 07:37:57 +00008893 bool MemcpyStrSrc,
Dan Gohman148c69a2010-04-16 20:11:05 +00008894 MachineFunction &MF) const {
Eric Christopherd90a8742014-06-12 22:38:20 +00008895 if (Subtarget.isPPC64()) {
Owen Anderson9f944592009-08-11 20:47:22 +00008896 return MVT::i64;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00008897 } else {
Owen Anderson9f944592009-08-11 20:47:22 +00008898 return MVT::i32;
Tilmann Schellerb93960d2009-07-03 06:45:56 +00008899 }
8900}
Hal Finkel88ed4e32012-04-01 19:23:08 +00008901
Hal Finkel34974ed2014-04-12 21:52:38 +00008902/// \brief Returns true if it is beneficial to convert a load of a constant
8903/// to just the constant itself.
8904bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
8905 Type *Ty) const {
8906 assert(Ty->isIntegerTy());
8907
8908 unsigned BitSize = Ty->getPrimitiveSizeInBits();
8909 if (BitSize == 0 || BitSize > 64)
8910 return false;
8911 return true;
8912}
8913
8914bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
8915 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8916 return false;
8917 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8918 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8919 return NumBits1 == 64 && NumBits2 == 32;
8920}
8921
8922bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8923 if (!VT1.isInteger() || !VT2.isInteger())
8924 return false;
8925 unsigned NumBits1 = VT1.getSizeInBits();
8926 unsigned NumBits2 = VT2.getSizeInBits();
8927 return NumBits1 == 64 && NumBits2 == 32;
8928}
8929
8930bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8931 return isInt<16>(Imm) || isUInt<16>(Imm);
8932}
8933
8934bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8935 return isInt<16>(Imm) || isUInt<16>(Imm);
8936}
8937
Hal Finkel8d7fbc92013-03-15 15:27:13 +00008938bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
Matt Arsenault25793a32014-02-05 23:15:53 +00008939 unsigned,
Hal Finkel8d7fbc92013-03-15 15:27:13 +00008940 bool *Fast) const {
8941 if (DisablePPCUnaligned)
8942 return false;
8943
8944 // PowerPC supports unaligned memory access for simple non-vector types.
8945 // Although accessing unaligned addresses is not as efficient as accessing
8946 // aligned addresses, it is generally more efficient than manual expansion,
8947 // and generally only traps for software emulation when crossing page
8948 // boundaries.
8949
8950 if (!VT.isSimple())
8951 return false;
8952
Hal Finkel6e28e6a2014-03-26 19:39:09 +00008953 if (VT.getSimpleVT().isVector()) {
Eric Christopherb1aaebe2014-06-12 22:38:18 +00008954 if (Subtarget.hasVSX()) {
Hal Finkel6e28e6a2014-03-26 19:39:09 +00008955 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8956 return false;
8957 } else {
8958 return false;
8959 }
8960 }
Hal Finkel8d7fbc92013-03-15 15:27:13 +00008961
8962 if (VT == MVT::ppcf128)
8963 return false;
8964
8965 if (Fast)
8966 *Fast = true;
8967
8968 return true;
8969}
8970
Stephen Lin73de7bf2013-07-09 18:16:56 +00008971bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8972 VT = VT.getScalarType();
8973
Hal Finkel0a479ae2012-06-22 00:49:52 +00008974 if (!VT.isSimple())
8975 return false;
8976
8977 switch (VT.getSimpleVT().SimpleTy) {
8978 case MVT::f32:
8979 case MVT::f64:
Hal Finkel0a479ae2012-06-22 00:49:52 +00008980 return true;
8981 default:
8982 break;
8983 }
8984
8985 return false;
8986}
8987
Hal Finkelb4240ca2014-03-31 17:48:16 +00008988bool
8989PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
8990 EVT VT , unsigned DefinedValues) const {
8991 if (VT == MVT::v2i64)
8992 return false;
8993
8994 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
8995}
8996
Hal Finkel88ed4e32012-04-01 19:23:08 +00008997Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
Eric Christopherb1aaebe2014-06-12 22:38:18 +00008998 if (DisableILPPref || Subtarget.enableMachineScheduler())
Hal Finkel4e9f1a82012-06-10 19:32:29 +00008999 return TargetLowering::getSchedulingPreference(N);
Hal Finkel88ed4e32012-04-01 19:23:08 +00009000
Hal Finkel4e9f1a82012-06-10 19:32:29 +00009001 return Sched::ILP;
Hal Finkel88ed4e32012-04-01 19:23:08 +00009002}
9003
Bill Schmidt0cf702f2013-07-30 00:50:39 +00009004// Create a fast isel object.
9005FastISel *
9006PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9007 const TargetLibraryInfo *LibInfo) const {
9008 return PPC::createFastISel(FuncInfo, LibInfo);
9009}