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Quentin Colombet2ad1f852016-02-11 17:44:59 +00001//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the MachineIRBuidler class.
11//===----------------------------------------------------------------------===//
12#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
13
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover0f140c72016-09-09 11:46:34 +000017#include "llvm/CodeGen/MachineRegisterInfo.h"
Tim Northover09aac4a2017-01-26 23:39:14 +000018#include "llvm/IR/DebugInfo.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000019#include "llvm/Target/TargetInstrInfo.h"
Quentin Colombet8fd67182016-02-11 21:16:56 +000020#include "llvm/Target/TargetOpcodes.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000021#include "llvm/Target/TargetSubtargetInfo.h"
22
23using namespace llvm;
24
Quentin Colombet000b5802016-03-11 17:27:51 +000025void MachineIRBuilder::setMF(MachineFunction &MF) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000026 this->MF = &MF;
27 this->MBB = nullptr;
Tim Northover0f140c72016-09-09 11:46:34 +000028 this->MRI = &MF.getRegInfo();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000029 this->TII = MF.getSubtarget().getInstrInfo();
30 this->DL = DebugLoc();
Tim Northover05cc4852016-12-07 21:05:38 +000031 this->II = MachineBasicBlock::iterator();
Tim Northover438c77c2016-08-25 17:37:32 +000032 this->InsertedInstr = nullptr;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000033}
34
Tim Northover05cc4852016-12-07 21:05:38 +000035void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000036 this->MBB = &MBB;
Tim Northover05cc4852016-12-07 21:05:38 +000037 this->II = MBB.end();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000038 assert(&getMF() == MBB.getParent() &&
39 "Basic block is in a different function");
40}
41
Tim Northover05cc4852016-12-07 21:05:38 +000042void MachineIRBuilder::setInstr(MachineInstr &MI) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000043 assert(MI.getParent() && "Instruction is not part of a basic block");
Quentin Colombet91ebd712016-03-11 17:27:47 +000044 setMBB(*MI.getParent());
Tim Northover05cc4852016-12-07 21:05:38 +000045 this->II = MI.getIterator();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000046}
47
Tim Northover05cc4852016-12-07 21:05:38 +000048void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator II) {
50 assert(MBB.getParent() == &getMF() &&
51 "Basic block is in a different function");
52 this->MBB = &MBB;
53 this->II = II;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000054}
55
Tim Northover438c77c2016-08-25 17:37:32 +000056void MachineIRBuilder::recordInsertions(
57 std::function<void(MachineInstr *)> Inserted) {
Benjamin Kramer061f4a52017-01-13 14:39:03 +000058 InsertedInstr = std::move(Inserted);
Tim Northover438c77c2016-08-25 17:37:32 +000059}
60
61void MachineIRBuilder::stopRecordingInsertions() {
62 InsertedInstr = nullptr;
63}
64
Quentin Colombetf9b49342016-03-11 17:27:58 +000065//------------------------------------------------------------------------------
66// Build instruction variants.
67//------------------------------------------------------------------------------
Tim Northovercc5f7622016-07-26 16:45:26 +000068
Tim Northover0f140c72016-09-09 11:46:34 +000069MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
Tim Northovera5e38fa2016-09-22 13:49:25 +000070 return insertInstr(buildInstrNoInsert(Opcode));
71}
72
73MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
Tim Northovera51575f2016-07-29 17:43:52 +000074 MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode));
Tim Northovera5e38fa2016-09-22 13:49:25 +000075 return MIB;
76}
77
78
79MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
Tim Northovera51575f2016-07-29 17:43:52 +000080 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +000081 if (InsertedInstr)
82 InsertedInstr(MIB);
Tim Northovera51575f2016-07-29 17:43:52 +000083 return MIB;
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000084}
85
Tim Northover09aac4a2017-01-26 23:39:14 +000086MachineInstrBuilder MachineIRBuilder::buildDirectDbgValue(
87 unsigned Reg, const MDNode *Variable, const MDNode *Expr) {
88 assert(isa<DILocalVariable>(Variable) && "not a variable");
89 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
90 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
91 "Expected inlined-at fields to agree");
92 return buildInstr(TargetOpcode::DBG_VALUE)
93 .addReg(Reg, RegState::Debug)
94 .addReg(0, RegState::Debug)
95 .addMetadata(Variable)
96 .addMetadata(Expr);
97}
98
99MachineInstrBuilder MachineIRBuilder::buildIndirectDbgValue(
100 unsigned Reg, unsigned Offset, const MDNode *Variable, const MDNode *Expr) {
101 assert(isa<DILocalVariable>(Variable) && "not a variable");
102 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
103 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
104 "Expected inlined-at fields to agree");
105 return buildInstr(TargetOpcode::DBG_VALUE)
106 .addReg(Reg, RegState::Debug)
107 .addImm(Offset)
108 .addMetadata(Variable)
109 .addMetadata(Expr);
110}
111
112MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
113 const MDNode *Variable,
114 const MDNode *Expr) {
115 assert(isa<DILocalVariable>(Variable) && "not a variable");
116 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
117 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
118 "Expected inlined-at fields to agree");
119 return buildInstr(TargetOpcode::DBG_VALUE)
120 .addFrameIndex(FI)
121 .addImm(0)
122 .addMetadata(Variable)
123 .addMetadata(Expr);
124}
125
126MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
127 unsigned Offset,
128 const MDNode *Variable,
129 const MDNode *Expr) {
130 assert(isa<DILocalVariable>(Variable) && "not a variable");
131 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
132 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
133 "Expected inlined-at fields to agree");
134 auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
135 if (auto *CI = dyn_cast<ConstantInt>(&C)) {
136 if (CI->getBitWidth() > 64)
137 MIB.addCImm(CI);
138 else
139 MIB.addImm(CI->getZExtValue());
140 } else
141 MIB.addFPImm(&cast<ConstantFP>(C));
142
143 return MIB.addImm(Offset).addMetadata(Variable).addMetadata(Expr);
144}
145
Tim Northover0f140c72016-09-09 11:46:34 +0000146MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000147 assert(MRI->getType(Res).isPointer() && "invalid operand type");
Tim Northover0f140c72016-09-09 11:46:34 +0000148 return buildInstr(TargetOpcode::G_FRAME_INDEX)
Tim Northovera51575f2016-07-29 17:43:52 +0000149 .addDef(Res)
150 .addFrameIndex(Idx);
Tim Northoverbd505462016-07-22 16:59:52 +0000151}
Tim Northover33b07d62016-07-22 20:03:43 +0000152
Tim Northover032548f2016-09-12 12:10:41 +0000153MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
154 const GlobalValue *GV) {
155 assert(MRI->getType(Res).isPointer() && "invalid operand type");
156 assert(MRI->getType(Res).getAddressSpace() ==
157 GV->getType()->getAddressSpace() &&
158 "address space mismatch");
159
160 return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
161 .addDef(Res)
162 .addGlobalAddress(GV);
163}
164
Tim Northover0f140c72016-09-09 11:46:34 +0000165MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0,
166 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000167 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
168 "invalid operand type");
169 assert(MRI->getType(Res) == MRI->getType(Op0) &&
170 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
171
Tim Northover0f140c72016-09-09 11:46:34 +0000172 return buildInstr(TargetOpcode::G_ADD)
Tim Northovera51575f2016-07-29 17:43:52 +0000173 .addDef(Res)
174 .addUse(Op0)
175 .addUse(Op1);
Tim Northover33b07d62016-07-22 20:03:43 +0000176}
177
Tim Northovera7653b32016-09-12 11:20:22 +0000178MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
179 unsigned Op1) {
180 assert(MRI->getType(Res).isPointer() &&
181 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
182 assert(MRI->getType(Op1).isScalar() && "invalid offset type");
183
184 return buildInstr(TargetOpcode::G_GEP)
185 .addDef(Res)
186 .addUse(Op0)
187 .addUse(Op1);
188}
189
Tim Northoverc2f89562017-02-14 20:56:18 +0000190MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
191 uint32_t NumBits) {
192 assert(MRI->getType(Res).isPointer() &&
193 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
194
195 return buildInstr(TargetOpcode::G_PTR_MASK)
196 .addDef(Res)
197 .addUse(Op0)
198 .addImm(NumBits);
199}
200
Tim Northover0f140c72016-09-09 11:46:34 +0000201MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0,
202 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000203 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
204 "invalid operand type");
205 assert(MRI->getType(Res) == MRI->getType(Op0) &&
206 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
207
Tim Northover0f140c72016-09-09 11:46:34 +0000208 return buildInstr(TargetOpcode::G_SUB)
Tim Northovercecee562016-08-26 17:46:13 +0000209 .addDef(Res)
210 .addUse(Op0)
211 .addUse(Op1);
212}
213
Tim Northover0f140c72016-09-09 11:46:34 +0000214MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0,
215 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000216 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
217 "invalid operand type");
218 assert(MRI->getType(Res) == MRI->getType(Op0) &&
219 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
220
Tim Northover0f140c72016-09-09 11:46:34 +0000221 return buildInstr(TargetOpcode::G_MUL)
Tim Northovercecee562016-08-26 17:46:13 +0000222 .addDef(Res)
223 .addUse(Op0)
224 .addUse(Op1);
225}
226
Tim Northoverc3e3f592017-02-03 18:22:45 +0000227MachineInstrBuilder MachineIRBuilder::buildAnd(unsigned Res, unsigned Op0,
228 unsigned Op1) {
229 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
230 "invalid operand type");
231 assert(MRI->getType(Res) == MRI->getType(Op0) &&
232 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
233
234 return buildInstr(TargetOpcode::G_AND)
235 .addDef(Res)
236 .addUse(Op0)
237 .addUse(Op1);
238}
239
Tim Northovera51575f2016-07-29 17:43:52 +0000240MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
Tim Northover0f140c72016-09-09 11:46:34 +0000241 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
Tim Northovercc5f7622016-07-26 16:45:26 +0000242}
243
Kristof Beyls65a12c02017-01-30 09:13:18 +0000244MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
245 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
246}
247
Tim Northovera51575f2016-07-29 17:43:52 +0000248MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) {
249 return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
Tim Northover756eca32016-07-26 16:45:30 +0000250}
251
Tim Northover9267ac52016-12-05 21:47:07 +0000252MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
253 const ConstantInt &Val) {
254 LLT Ty = MRI->getType(Res);
Tim Northover1f8b1db2016-09-09 11:46:58 +0000255
Sam McCall03435f52016-12-06 10:14:36 +0000256 assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
Tim Northover9267ac52016-12-05 21:47:07 +0000257
258 const ConstantInt *NewVal = &Val;
259 if (Ty.getSizeInBits() != Val.getBitWidth())
260 NewVal = ConstantInt::get(MF->getFunction()->getContext(),
261 Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
262
263 return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal);
264}
265
266MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
267 int64_t Val) {
268 auto IntN = IntegerType::get(MF->getFunction()->getContext(),
269 MRI->getType(Res).getSizeInBits());
270 ConstantInt *CI = ConstantInt::get(IntN, Val, true);
271 return buildConstant(Res, *CI);
Tim Northover9656f142016-08-04 20:54:13 +0000272}
273
Tim Northover0f140c72016-09-09 11:46:34 +0000274MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res,
275 const ConstantFP &Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000276 assert(MRI->getType(Res).isScalar() && "invalid operand type");
277
Tim Northover0f140c72016-09-09 11:46:34 +0000278 return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val);
Tim Northoverb16734f2016-08-19 20:09:15 +0000279}
280
Tim Northover0f140c72016-09-09 11:46:34 +0000281MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
Tim Northover69c2ba52016-07-29 17:58:00 +0000282 MachineBasicBlock &Dest) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000283 assert(MRI->getType(Tst).isScalar() && "invalid operand type");
284
Tim Northover0f140c72016-09-09 11:46:34 +0000285 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
Tim Northover69c2ba52016-07-29 17:58:00 +0000286}
287
Tim Northover0f140c72016-09-09 11:46:34 +0000288MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
289 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000290 assert(MRI->getType(Res).isValid() && "invalid operand type");
291 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
292
Tim Northover0f140c72016-09-09 11:46:34 +0000293 return buildInstr(TargetOpcode::G_LOAD)
Tim Northovera51575f2016-07-29 17:43:52 +0000294 .addDef(Res)
295 .addUse(Addr)
296 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000297}
298
Tim Northover0f140c72016-09-09 11:46:34 +0000299MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
300 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000301 assert(MRI->getType(Val).isValid() && "invalid operand type");
302 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
303
Tim Northover0f140c72016-09-09 11:46:34 +0000304 return buildInstr(TargetOpcode::G_STORE)
Tim Northovera51575f2016-07-29 17:43:52 +0000305 .addUse(Val)
306 .addUse(Addr)
307 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000308}
309
Tim Northover0f140c72016-09-09 11:46:34 +0000310MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res,
311 unsigned CarryOut,
312 unsigned Op0, unsigned Op1,
313 unsigned CarryIn) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000314 assert(MRI->getType(Res).isScalar() && "invalid operand type");
315 assert(MRI->getType(Res) == MRI->getType(Op0) &&
316 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
317 assert(MRI->getType(CarryOut).isScalar() && "invalid operand type");
318 assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch");
319
Tim Northover0f140c72016-09-09 11:46:34 +0000320 return buildInstr(TargetOpcode::G_UADDE)
Tim Northover9656f142016-08-04 20:54:13 +0000321 .addDef(Res)
322 .addDef(CarryOut)
323 .addUse(Op0)
324 .addUse(Op1)
325 .addUse(CarryIn);
326}
327
Tim Northover0f140c72016-09-09 11:46:34 +0000328MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) {
329 validateTruncExt(Res, Op, true);
330 return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000331}
332
Tim Northover0f140c72016-09-09 11:46:34 +0000333MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) {
334 validateTruncExt(Res, Op, true);
335 return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000336}
337
Tim Northover0f140c72016-09-09 11:46:34 +0000338MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) {
339 validateTruncExt(Res, Op, true);
340 return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000341}
342
Tim Northovera7653b32016-09-12 11:20:22 +0000343MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
344 unsigned Op) {
345 unsigned Opcode = TargetOpcode::COPY;
346 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
347 Opcode = TargetOpcode::G_SEXT;
348 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
349 Opcode = TargetOpcode::G_TRUNC;
350
351 return buildInstr(Opcode).addDef(Res).addUse(Op);
352}
353
Tim Northoverc3e3f592017-02-03 18:22:45 +0000354MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(unsigned Res,
355 unsigned Op) {
356 unsigned Opcode = TargetOpcode::COPY;
357 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
358 Opcode = TargetOpcode::G_ZEXT;
359 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
360 Opcode = TargetOpcode::G_TRUNC;
361
362 return buildInstr(Opcode).addDef(Res).addUse(Op);
363}
364
Tim Northover0f140c72016-09-09 11:46:34 +0000365MachineInstrBuilder MachineIRBuilder::buildExtract(ArrayRef<unsigned> Results,
Tim Northover26b76f22016-08-19 18:32:14 +0000366 ArrayRef<uint64_t> Indices,
Tim Northover0f140c72016-09-09 11:46:34 +0000367 unsigned Src) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000368#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000369 assert(Results.size() == Indices.size() && "inconsistent number of regs");
Tim Northover26b76f22016-08-19 18:32:14 +0000370 assert(!Results.empty() && "invalid trivial extract");
Tim Northover991b12b2016-08-30 20:51:25 +0000371 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
372 "extract offsets must be in ascending order");
Tim Northover33b07d62016-07-22 20:03:43 +0000373
Tim Northover1f8b1db2016-09-09 11:46:58 +0000374 assert(MRI->getType(Src).isValid() && "invalid operand type");
375 for (auto Res : Results)
376 assert(MRI->getType(Res).isValid() && "invalid operand type");
377#endif
378
Tim Northover26b76f22016-08-19 18:32:14 +0000379 auto MIB = BuildMI(getMF(), DL, getTII().get(TargetOpcode::G_EXTRACT));
Tim Northover33b07d62016-07-22 20:03:43 +0000380 for (auto Res : Results)
Tim Northovera51575f2016-07-29 17:43:52 +0000381 MIB.addDef(Res);
Tim Northover33b07d62016-07-22 20:03:43 +0000382
Tim Northovera51575f2016-07-29 17:43:52 +0000383 MIB.addUse(Src);
Tim Northover33b07d62016-07-22 20:03:43 +0000384
Tim Northover26b76f22016-08-19 18:32:14 +0000385 for (auto Idx : Indices)
Tim Northover33b07d62016-07-22 20:03:43 +0000386 MIB.addImm(Idx);
Tim Northover26b76f22016-08-19 18:32:14 +0000387
388 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +0000389 if (InsertedInstr)
390 InsertedInstr(MIB);
Tim Northover26b76f22016-08-19 18:32:14 +0000391
Tim Northovera51575f2016-07-29 17:43:52 +0000392 return MIB;
Tim Northover33b07d62016-07-22 20:03:43 +0000393}
394
Tim Northover91c81732016-08-19 17:17:06 +0000395MachineInstrBuilder
Tim Northover0f140c72016-09-09 11:46:34 +0000396MachineIRBuilder::buildSequence(unsigned Res,
Tim Northover91c81732016-08-19 17:17:06 +0000397 ArrayRef<unsigned> Ops,
Tim Northoverb18ea162016-09-20 15:20:36 +0000398 ArrayRef<uint64_t> Indices) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000399#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000400 assert(Ops.size() == Indices.size() && "incompatible args");
Tim Northover26b76f22016-08-19 18:32:14 +0000401 assert(!Ops.empty() && "invalid trivial sequence");
Tim Northover991b12b2016-08-30 20:51:25 +0000402 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
403 "sequence offsets must be in ascending order");
Tim Northover91c81732016-08-19 17:17:06 +0000404
Tim Northover1f8b1db2016-09-09 11:46:58 +0000405 assert(MRI->getType(Res).isValid() && "invalid operand type");
406 for (auto Op : Ops)
407 assert(MRI->getType(Op).isValid() && "invalid operand type");
408#endif
409
Tim Northover0f140c72016-09-09 11:46:34 +0000410 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE);
Tim Northovera51575f2016-07-29 17:43:52 +0000411 MIB.addDef(Res);
Tim Northover91c81732016-08-19 17:17:06 +0000412 for (unsigned i = 0; i < Ops.size(); ++i) {
413 MIB.addUse(Ops[i]);
Tim Northover26b76f22016-08-19 18:32:14 +0000414 MIB.addImm(Indices[i]);
Tim Northover91c81732016-08-19 17:17:06 +0000415 }
Tim Northovera51575f2016-07-29 17:43:52 +0000416 return MIB;
Tim Northover33b07d62016-07-22 20:03:43 +0000417}
Tim Northover5fb414d2016-07-29 22:32:36 +0000418
Tim Northoverbf017292017-03-03 22:46:09 +0000419MachineInstrBuilder MachineIRBuilder::buildMerge(unsigned Res,
420 ArrayRef<unsigned> Ops) {
421
422#ifndef NDEBUG
423 assert(!Ops.empty() && "invalid trivial sequence");
424 LLT Ty = MRI->getType(Ops[0]);
425 for (auto Reg : Ops)
426 assert(MRI->getType(Reg) == Ty && "type mismatch in input list");
427 assert(Ops.size() * MRI->getType(Ops[0]).getSizeInBits() ==
428 MRI->getType(Res).getSizeInBits() &&
429 "input operands do not cover output register");
430#endif
431
432 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_MERGE_VALUES);
433 MIB.addDef(Res);
434 for (unsigned i = 0; i < Ops.size(); ++i)
435 MIB.addUse(Ops[i]);
436 return MIB;
437}
438
439MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
440 unsigned Op) {
441
442#ifndef NDEBUG
443 assert(!Res.empty() && "invalid trivial sequence");
444 LLT Ty = MRI->getType(Res[0]);
445 for (auto Reg : Res)
446 assert(MRI->getType(Reg) == Ty && "type mismatch in input list");
447 assert(Res.size() * MRI->getType(Res[0]).getSizeInBits() ==
448 MRI->getType(Op).getSizeInBits() &&
449 "input operands do not cover output register");
450#endif
451
452 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_UNMERGE_VALUES);
453 for (unsigned i = 0; i < Res.size(); ++i)
454 MIB.addDef(Res[i]);
455 MIB.addUse(Op);
456 return MIB;
457}
458
Tim Northover0f140c72016-09-09 11:46:34 +0000459MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
Tim Northover5fb414d2016-07-29 22:32:36 +0000460 unsigned Res,
461 bool HasSideEffects) {
462 auto MIB =
463 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
Tim Northover0f140c72016-09-09 11:46:34 +0000464 : TargetOpcode::G_INTRINSIC);
Tim Northover5fb414d2016-07-29 22:32:36 +0000465 if (Res)
466 MIB.addDef(Res);
467 MIB.addIntrinsicID(ID);
468 return MIB;
469}
Tim Northover32335812016-08-04 18:35:11 +0000470
Tim Northover0f140c72016-09-09 11:46:34 +0000471MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) {
472 validateTruncExt(Res, Op, false);
473 return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000474}
Tim Northoverde3aea0412016-08-17 20:25:25 +0000475
Tim Northover0f140c72016-09-09 11:46:34 +0000476MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) {
477 validateTruncExt(Res, Op, false);
478 return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op);
Tim Northovera11be042016-08-19 22:40:08 +0000479}
480
Tim Northover0f140c72016-09-09 11:46:34 +0000481MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
Tim Northoverde3aea0412016-08-17 20:25:25 +0000482 unsigned Res, unsigned Op0,
483 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000484#ifndef NDEBUG
Tim Northover1f8b1db2016-09-09 11:46:58 +0000485 assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch");
486 assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
Tim Northover4cf0a482016-09-15 10:40:38 +0000487 if (MRI->getType(Op0).isScalar() || MRI->getType(Op0).isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000488 assert(MRI->getType(Res).isScalar() && "type mismatch");
489 else
490 assert(MRI->getType(Res).isVector() &&
491 MRI->getType(Res).getNumElements() ==
492 MRI->getType(Op0).getNumElements() &&
493 "type mismatch");
494#endif
495
Tim Northover0f140c72016-09-09 11:46:34 +0000496 return buildInstr(TargetOpcode::G_ICMP)
Tim Northoverde3aea0412016-08-17 20:25:25 +0000497 .addDef(Res)
498 .addPredicate(Pred)
499 .addUse(Op0)
500 .addUse(Op1);
501}
Tim Northover5a28c362016-08-19 20:09:07 +0000502
Tim Northover0f140c72016-09-09 11:46:34 +0000503MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000504 unsigned Res, unsigned Op0,
505 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000506#ifndef NDEBUG
507 assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
508 "invalid operand type");
509 assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch");
510 assert(CmpInst::isFPPredicate(Pred) && "invalid predicate");
511 if (MRI->getType(Op0).isScalar())
512 assert(MRI->getType(Res).isScalar() && "type mismatch");
513 else
514 assert(MRI->getType(Res).isVector() &&
515 MRI->getType(Res).getNumElements() ==
516 MRI->getType(Op0).getNumElements() &&
517 "type mismatch");
518#endif
519
Tim Northover0f140c72016-09-09 11:46:34 +0000520 return buildInstr(TargetOpcode::G_FCMP)
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000521 .addDef(Res)
522 .addPredicate(Pred)
523 .addUse(Op0)
524 .addUse(Op1);
525}
526
Tim Northover0f140c72016-09-09 11:46:34 +0000527MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst,
Tim Northover5a28c362016-08-19 20:09:07 +0000528 unsigned Op0, unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000529#ifndef NDEBUG
Tim Northoverf50f2f32016-12-06 18:38:34 +0000530 LLT ResTy = MRI->getType(Res);
531 assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
Tim Northover1f8b1db2016-09-09 11:46:58 +0000532 "invalid operand type");
Tim Northoverf50f2f32016-12-06 18:38:34 +0000533 assert(ResTy == MRI->getType(Op0) && ResTy == MRI->getType(Op1) &&
534 "type mismatch");
535 if (ResTy.isScalar() || ResTy.isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000536 assert(MRI->getType(Tst).isScalar() && "type mismatch");
537 else
538 assert(MRI->getType(Tst).isVector() &&
539 MRI->getType(Tst).getNumElements() ==
540 MRI->getType(Op0).getNumElements() &&
541 "type mismatch");
542#endif
543
Tim Northover0f140c72016-09-09 11:46:34 +0000544 return buildInstr(TargetOpcode::G_SELECT)
Tim Northover5a28c362016-08-19 20:09:07 +0000545 .addDef(Res)
546 .addUse(Tst)
547 .addUse(Op0)
548 .addUse(Op1);
549}
Tim Northoverbdf67c92016-08-23 21:01:33 +0000550
Tim Northover0f140c72016-09-09 11:46:34 +0000551void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src,
552 bool IsExtend) {
Richard Smith418237b2016-08-23 22:14:15 +0000553#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000554 LLT SrcTy = MRI->getType(Src);
555 LLT DstTy = MRI->getType(Dst);
Tim Northoverbdf67c92016-08-23 21:01:33 +0000556
557 if (DstTy.isVector()) {
558 assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector");
559 assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
560 "different number of elements in a trunc/ext");
561 } else
562 assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
563
564 if (IsExtend)
565 assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
566 "invalid narrowing extend");
567 else
568 assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
569 "invalid widening trunc");
Richard Smith418237b2016-08-23 22:14:15 +0000570#endif
Tim Northoverbdf67c92016-08-23 21:01:33 +0000571}