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gerrit-public.fairphone.software / toolchain / llvm-project / c0eb9963180ef33debbd4f0a0e752eb8187a80c5 / . / llvm / test / CodeGen / PowerPC / float-to-int.ll
blob: 80e6b75ced3d1198eee9adee3ca79ae44c341d1d [file] [log] [blame]
Nemanja Ivanovic6354d232016-10-04 11:25:52 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
2; RUN: -mcpu=a2 | FileCheck %s
3; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
4; RUN: -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
5; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
6; RUN: -mcpu=g5
7; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
8; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck -check-prefix=CHECK-P9 %s
Hal Finkelf6d45f22013-04-01 17:52:07 +0000[diff] [blame]9target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
10target triple = "powerpc64-unknown-linux-gnu"
11
12define i64 @foo(float %a) nounwind {
13 %x = fptosi float %a to i64
14 ret i64 %x
15
16; CHECK: @foo
17; CHECK: fctidz [[REG:[0-9]+]], 1
18; CHECK: stfd [[REG]],
19; CHECK: ld 3,
20; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]21
22; CHECK-VSX: @foo
23; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
24; CHECK-VSX: stxsdx [[REG]],
25; CHECK-VSX: ld 3,
26; CHECK-VSX: blr
Nemanja Ivanovic6354d232016-10-04 11:25:52 +0000[diff] [blame]27
28; CHECK-LABEL-P9: @foo
29; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
30; CHECK-P9: stfd [[REG]],
31; CHECK-P9: ld 3,
32; CHECK-P9: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +0000[diff] [blame]33}
34
35define i64 @foo2(double %a) nounwind {
36 %x = fptosi double %a to i64
37 ret i64 %x
38
39; CHECK: @foo2
40; CHECK: fctidz [[REG:[0-9]+]], 1
41; CHECK: stfd [[REG]],
42; CHECK: ld 3,
43; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]44
45; CHECK-VSX: @foo2
46; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
47; CHECK-VSX: stxsdx [[REG]],
48; CHECK-VSX: ld 3,
49; CHECK-VSX: blr
Nemanja Ivanovic6354d232016-10-04 11:25:52 +0000[diff] [blame]50
51; CHECK-LABEL-P9: @foo2
52; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
53; CHECK-P9: stfd [[REG]],
54; CHECK-P9: ld 3,
55; CHECK-P9: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +0000[diff] [blame]56}
57
58define i64 @foo3(float %a) nounwind {
59 %x = fptoui float %a to i64
60 ret i64 %x
61
62; CHECK: @foo3
63; CHECK: fctiduz [[REG:[0-9]+]], 1
64; CHECK: stfd [[REG]],
65; CHECK: ld 3,
66; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]67
68; CHECK-VSX: @foo3
69; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1
70; CHECK-VSX: stxsdx [[REG]],
71; CHECK-VSX: ld 3,
72; CHECK-VSX: blr
Nemanja Ivanovic6354d232016-10-04 11:25:52 +0000[diff] [blame]73
74; CHECK-LABEL-P9: @foo3
75; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1
76; CHECK-P9: stfd [[REG]],
77; CHECK-P9: ld 3,
78; CHECK-P9: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +0000[diff] [blame]79}
80
81define i64 @foo4(double %a) nounwind {
82 %x = fptoui double %a to i64
83 ret i64 %x
84
85; CHECK: @foo4
86; CHECK: fctiduz [[REG:[0-9]+]], 1
87; CHECK: stfd [[REG]],
88; CHECK: ld 3,
89; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]90
91; CHECK-VSX: @foo4
92; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1
93; CHECK-VSX: stxsdx [[REG]],
94; CHECK-VSX: ld 3,
95; CHECK-VSX: blr
Nemanja Ivanovic6354d232016-10-04 11:25:52 +0000[diff] [blame]96
97; CHECK-LABEL-P9: @foo4
98; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1
99; CHECK-P9: stfd [[REG]],
100; CHECK-P9: ld 3,
101; CHECK-P9: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +0000[diff] [blame]102}
103
104define i32 @goo(float %a) nounwind {
105 %x = fptosi float %a to i32
106 ret i32 %x
107
108; CHECK: @goo
109; CHECK: fctiwz [[REG:[0-9]+]], 1
110; CHECK: stfiwx [[REG]],
111; CHECK: lwz 3,
112; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]113
114; CHECK-VSX: @goo
115; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1
116; CHECK-VSX: stfiwx [[REG]],
117; CHECK-VSX: lwz 3,
118; CHECK-VSX: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +0000[diff] [blame]119}
120
121define i32 @goo2(double %a) nounwind {
122 %x = fptosi double %a to i32
123 ret i32 %x
124
125; CHECK: @goo2
126; CHECK: fctiwz [[REG:[0-9]+]], 1
127; CHECK: stfiwx [[REG]],
128; CHECK: lwz 3,
129; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]130
131; CHECK-VSX: @goo2
132; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1
133; CHECK-VSX: stfiwx [[REG]],
134; CHECK-VSX: lwz 3,
135; CHECK-VSX: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +0000[diff] [blame]136}
137
138define i32 @goo3(float %a) nounwind {
139 %x = fptoui float %a to i32
140 ret i32 %x
141
142; CHECK: @goo3
143; CHECK: fctiwuz [[REG:[0-9]+]], 1
144; CHECK: stfiwx [[REG]],
145; CHECK: lwz 3,
146; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]147
148; CHECK-VSX: @goo3
149; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1
150; CHECK-VSX: stfiwx [[REG]],
151; CHECK-VSX: lwz 3,
152; CHECK-VSX: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +0000[diff] [blame]153}
154
155define i32 @goo4(double %a) nounwind {
156 %x = fptoui double %a to i32
157 ret i32 %x
158
159; CHECK: @goo4
160; CHECK: fctiwuz [[REG:[0-9]+]], 1
161; CHECK: stfiwx [[REG]],
162; CHECK: lwz 3,
163; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]164
165; CHECK-VSX: @goo4
166; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1
167; CHECK-VSX: stfiwx [[REG]],
168; CHECK-VSX: lwz 3,
169; CHECK-VSX: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +0000[diff] [blame]170}
171