blob: 706e89051a3da038ca1782ea4676fceb064cf908 [file] [log] [blame]
Simon Pilgrim476560a2016-10-18 19:28:12 +00001; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
4
5; fold (srl 0, x) -> 0
6define <4 x i32> @combine_vec_lshr_zero(<4 x i32> %x) {
7; SSE-LABEL: combine_vec_lshr_zero:
8; SSE: # BB#0:
9; SSE-NEXT: movdqa %xmm0, %xmm2
10; SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
11; SSE-NEXT: pxor %xmm1, %xmm1
12; SSE-NEXT: pxor %xmm3, %xmm3
13; SSE-NEXT: psrld %xmm2, %xmm3
14; SSE-NEXT: movdqa %xmm0, %xmm2
15; SSE-NEXT: psrlq $32, %xmm2
16; SSE-NEXT: pxor %xmm4, %xmm4
17; SSE-NEXT: psrld %xmm2, %xmm4
18; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm3[4,5,6,7]
19; SSE-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
20; SSE-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
21; SSE-NEXT: pxor %xmm3, %xmm3
22; SSE-NEXT: psrld %xmm0, %xmm3
23; SSE-NEXT: psrld %xmm2, %xmm1
24; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm3[4,5,6,7]
25; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm4[2,3],xmm1[4,5],xmm4[6,7]
26; SSE-NEXT: movdqa %xmm1, %xmm0
27; SSE-NEXT: retq
28;
29; AVX-LABEL: combine_vec_lshr_zero:
30; AVX: # BB#0:
31; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
32; AVX-NEXT: vpsrlvd %xmm0, %xmm1, %xmm0
33; AVX-NEXT: retq
34 %1 = lshr <4 x i32> zeroinitializer, %x
35 ret <4 x i32> %1
36}
37
38; fold (srl x, c >= size(x)) -> undef
39define <4 x i32> @combine_vec_lshr_outofrange0(<4 x i32> %x) {
40; SSE-LABEL: combine_vec_lshr_outofrange0:
41; SSE: # BB#0:
42; SSE-NEXT: retq
43;
44; AVX-LABEL: combine_vec_lshr_outofrange0:
45; AVX: # BB#0:
46; AVX-NEXT: retq
47 %1 = lshr <4 x i32> %x, <i32 33, i32 33, i32 33, i32 33>
48 ret <4 x i32> %1
49}
50
51define <4 x i32> @combine_vec_lshr_outofrange1(<4 x i32> %x) {
52; SSE-LABEL: combine_vec_lshr_outofrange1:
53; SSE: # BB#0:
54; SSE-NEXT: xorps %xmm0, %xmm0
55; SSE-NEXT: retq
56;
57; AVX-LABEL: combine_vec_lshr_outofrange1:
58; AVX: # BB#0:
59; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
60; AVX-NEXT: retq
61 %1 = lshr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 36>
62 ret <4 x i32> %1
63}
64
65; fold (srl x, 0) -> x
66define <4 x i32> @combine_vec_lshr_by_zero(<4 x i32> %x) {
67; SSE-LABEL: combine_vec_lshr_by_zero:
68; SSE: # BB#0:
69; SSE-NEXT: retq
70;
71; AVX-LABEL: combine_vec_lshr_by_zero:
72; AVX: # BB#0:
73; AVX-NEXT: retq
74 %1 = lshr <4 x i32> %x, zeroinitializer
75 ret <4 x i32> %1
76}
77
78; if (srl x, c) is known to be zero, return 0
79define <4 x i32> @combine_vec_lshr_known_zero0(<4 x i32> %x) {
80; SSE-LABEL: combine_vec_lshr_known_zero0:
81; SSE: # BB#0:
Sanjay Patel9ca028c2016-10-23 23:13:31 +000082; SSE-NEXT: xorps %xmm0, %xmm0
Simon Pilgrim476560a2016-10-18 19:28:12 +000083; SSE-NEXT: retq
84;
85; AVX-LABEL: combine_vec_lshr_known_zero0:
86; AVX: # BB#0:
Sanjay Patel9ca028c2016-10-23 23:13:31 +000087; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
Simon Pilgrim476560a2016-10-18 19:28:12 +000088; AVX-NEXT: retq
89 %1 = and <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
90 %2 = lshr <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>
91 ret <4 x i32> %2
92}
93
94define <4 x i32> @combine_vec_lshr_known_zero1(<4 x i32> %x) {
95; SSE-LABEL: combine_vec_lshr_known_zero1:
96; SSE: # BB#0:
97; SSE-NEXT: pand {{.*}}(%rip), %xmm0
98; SSE-NEXT: movdqa %xmm0, %xmm1
99; SSE-NEXT: psrld $11, %xmm1
100; SSE-NEXT: movdqa %xmm0, %xmm2
101; SSE-NEXT: psrld $9, %xmm2
102; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
103; SSE-NEXT: movdqa %xmm0, %xmm1
104; SSE-NEXT: psrld $10, %xmm1
105; SSE-NEXT: psrld $8, %xmm0
106; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
107; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
108; SSE-NEXT: retq
109;
110; AVX-LABEL: combine_vec_lshr_known_zero1:
111; AVX: # BB#0:
112; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
113; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
114; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
115; AVX-NEXT: retq
116 %1 = and <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
117 %2 = lshr <4 x i32> %1, <i32 8, i32 9, i32 10, i32 11>
118 ret <4 x i32> %2
119}
120
121; fold (srl (srl x, c1), c2) -> (srl x, (add c1, c2))
122define <4 x i32> @combine_vec_lshr_lshr0(<4 x i32> %x) {
123; SSE-LABEL: combine_vec_lshr_lshr0:
124; SSE: # BB#0:
125; SSE-NEXT: psrld $6, %xmm0
126; SSE-NEXT: retq
127;
128; AVX-LABEL: combine_vec_lshr_lshr0:
129; AVX: # BB#0:
130; AVX-NEXT: vpsrld $6, %xmm0, %xmm0
131; AVX-NEXT: retq
132 %1 = lshr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
133 %2 = lshr <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>
134 ret <4 x i32> %2
135}
136
137define <4 x i32> @combine_vec_lshr_lshr1(<4 x i32> %x) {
138; SSE-LABEL: combine_vec_lshr_lshr1:
139; SSE: # BB#0:
140; SSE-NEXT: movdqa %xmm0, %xmm2
141; SSE-NEXT: movdqa %xmm0, %xmm1
142; SSE-NEXT: psrld $2, %xmm1
143; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7]
144; SSE-NEXT: psrld $3, %xmm0
145; SSE-NEXT: psrld $1, %xmm2
146; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm0[4,5,6,7]
147; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
148; SSE-NEXT: movdqa %xmm1, %xmm0
149; SSE-NEXT: psrld $7, %xmm0
150; SSE-NEXT: movdqa %xmm1, %xmm2
151; SSE-NEXT: psrld $5, %xmm2
152; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm0[4,5,6,7]
153; SSE-NEXT: movdqa %xmm1, %xmm0
154; SSE-NEXT: psrld $6, %xmm0
155; SSE-NEXT: psrld $4, %xmm1
156; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]
157; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
158; SSE-NEXT: movdqa %xmm1, %xmm0
159; SSE-NEXT: retq
160;
161; AVX-LABEL: combine_vec_lshr_lshr1:
162; AVX: # BB#0:
163; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
164; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
165; AVX-NEXT: retq
166 %1 = lshr <4 x i32> %x, <i32 0, i32 1, i32 2, i32 3>
167 %2 = lshr <4 x i32> %1, <i32 4, i32 5, i32 6, i32 7>
168 ret <4 x i32> %2
169}
170
171; fold (srl (srl x, c1), c2) -> 0
172define <4 x i32> @combine_vec_lshr_lshr_zero0(<4 x i32> %x) {
173; SSE-LABEL: combine_vec_lshr_lshr_zero0:
174; SSE: # BB#0:
175; SSE-NEXT: xorps %xmm0, %xmm0
176; SSE-NEXT: retq
177;
178; AVX-LABEL: combine_vec_lshr_lshr_zero0:
179; AVX: # BB#0:
180; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
181; AVX-NEXT: retq
182 %1 = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
183 %2 = lshr <4 x i32> %1, <i32 20, i32 20, i32 20, i32 20>
184 ret <4 x i32> %2
185}
186
187define <4 x i32> @combine_vec_lshr_lshr_zero1(<4 x i32> %x) {
188; SSE-LABEL: combine_vec_lshr_lshr_zero1:
189; SSE: # BB#0:
190; SSE-NEXT: movdqa %xmm0, %xmm1
191; SSE-NEXT: psrld $20, %xmm1
192; SSE-NEXT: movdqa %xmm0, %xmm2
193; SSE-NEXT: psrld $18, %xmm2
194; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
195; SSE-NEXT: movdqa %xmm0, %xmm1
196; SSE-NEXT: psrld $19, %xmm1
197; SSE-NEXT: psrld $17, %xmm0
198; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
199; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
200; SSE-NEXT: movdqa %xmm0, %xmm1
201; SSE-NEXT: psrld $28, %xmm1
202; SSE-NEXT: movdqa %xmm0, %xmm2
203; SSE-NEXT: psrld $26, %xmm2
204; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
205; SSE-NEXT: movdqa %xmm0, %xmm1
206; SSE-NEXT: psrld $27, %xmm1
207; SSE-NEXT: psrld $25, %xmm0
208; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
209; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
210; SSE-NEXT: retq
211;
212; AVX-LABEL: combine_vec_lshr_lshr_zero1:
213; AVX: # BB#0:
214; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
215; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
216; AVX-NEXT: retq
217 %1 = lshr <4 x i32> %x, <i32 17, i32 18, i32 19, i32 20>
218 %2 = lshr <4 x i32> %1, <i32 25, i32 26, i32 27, i32 28>
219 ret <4 x i32> %2
220}
221
222; fold (srl (trunc (srl x, c1)), c2) -> (trunc (srl x, (add c1, c2)))
223define <4 x i32> @combine_vec_lshr_trunc_lshr0(<4 x i64> %x) {
224; SSE-LABEL: combine_vec_lshr_trunc_lshr0:
225; SSE: # BB#0:
Simon Pilgrim7d65b662017-04-25 12:40:45 +0000226; SSE-NEXT: psrlq $48, %xmm1
227; SSE-NEXT: psrlq $48, %xmm0
Sanjay Patela0d8a272016-12-15 18:03:38 +0000228; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
Simon Pilgrim476560a2016-10-18 19:28:12 +0000229; SSE-NEXT: retq
230;
231; AVX-LABEL: combine_vec_lshr_trunc_lshr0:
232; AVX: # BB#0:
Simon Pilgrim7d65b662017-04-25 12:40:45 +0000233; AVX-NEXT: vpsrlq $48, %ymm0, %ymm0
Simon Pilgrim476560a2016-10-18 19:28:12 +0000234; AVX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
235; AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
Simon Pilgrim7d65b662017-04-25 12:40:45 +0000236; AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
Simon Pilgrim476560a2016-10-18 19:28:12 +0000237; AVX-NEXT: vzeroupper
238; AVX-NEXT: retq
239 %1 = lshr <4 x i64> %x, <i64 32, i64 32, i64 32, i64 32>
240 %2 = trunc <4 x i64> %1 to <4 x i32>
241 %3 = lshr <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
242 ret <4 x i32> %3
243}
244
245define <4 x i32> @combine_vec_lshr_trunc_lshr1(<4 x i64> %x) {
246; SSE-LABEL: combine_vec_lshr_trunc_lshr1:
247; SSE: # BB#0:
Simon Pilgrim476560a2016-10-18 19:28:12 +0000248; SSE-NEXT: movdqa %xmm1, %xmm2
249; SSE-NEXT: psrlq $35, %xmm2
250; SSE-NEXT: psrlq $34, %xmm1
251; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
Simon Pilgrim476560a2016-10-18 19:28:12 +0000252; SSE-NEXT: movdqa %xmm0, %xmm2
Sanjay Patela0d8a272016-12-15 18:03:38 +0000253; SSE-NEXT: psrlq $33, %xmm2
254; SSE-NEXT: psrlq $32, %xmm0
255; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
256; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
257; SSE-NEXT: movaps %xmm0, %xmm1
258; SSE-NEXT: psrld $19, %xmm1
259; SSE-NEXT: movaps %xmm0, %xmm2
Simon Pilgrim476560a2016-10-18 19:28:12 +0000260; SSE-NEXT: psrld $17, %xmm2
261; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
Sanjay Patela0d8a272016-12-15 18:03:38 +0000262; SSE-NEXT: movaps %xmm0, %xmm1
Simon Pilgrim476560a2016-10-18 19:28:12 +0000263; SSE-NEXT: psrld $18, %xmm1
264; SSE-NEXT: psrld $16, %xmm0
265; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
266; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
267; SSE-NEXT: retq
268;
269; AVX-LABEL: combine_vec_lshr_trunc_lshr1:
270; AVX: # BB#0:
271; AVX-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0
272; AVX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
273; AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
274; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
275; AVX-NEXT: vzeroupper
276; AVX-NEXT: retq
277 %1 = lshr <4 x i64> %x, <i64 32, i64 33, i64 34, i64 35>
278 %2 = trunc <4 x i64> %1 to <4 x i32>
279 %3 = lshr <4 x i32> %2, <i32 16, i32 17, i32 18, i32 19>
280 ret <4 x i32> %3
281}
282
283; fold (srl (trunc (srl x, c1)), c2) -> 0
284define <4 x i32> @combine_vec_lshr_trunc_lshr_zero0(<4 x i64> %x) {
285; SSE-LABEL: combine_vec_lshr_trunc_lshr_zero0:
286; SSE: # BB#0:
Sanjay Patel9ca028c2016-10-23 23:13:31 +0000287; SSE-NEXT: xorps %xmm0, %xmm0
Simon Pilgrim476560a2016-10-18 19:28:12 +0000288; SSE-NEXT: retq
289;
290; AVX-LABEL: combine_vec_lshr_trunc_lshr_zero0:
291; AVX: # BB#0:
Sanjay Patel9ca028c2016-10-23 23:13:31 +0000292; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
Simon Pilgrim476560a2016-10-18 19:28:12 +0000293; AVX-NEXT: retq
294 %1 = lshr <4 x i64> %x, <i64 48, i64 48, i64 48, i64 48>
295 %2 = trunc <4 x i64> %1 to <4 x i32>
296 %3 = lshr <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24>
297 ret <4 x i32> %3
298}
299
300define <4 x i32> @combine_vec_lshr_trunc_lshr_zero1(<4 x i64> %x) {
301; SSE-LABEL: combine_vec_lshr_trunc_lshr_zero1:
302; SSE: # BB#0:
Simon Pilgrim476560a2016-10-18 19:28:12 +0000303; SSE-NEXT: movdqa %xmm1, %xmm2
304; SSE-NEXT: psrlq $51, %xmm2
305; SSE-NEXT: psrlq $50, %xmm1
306; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
Simon Pilgrim476560a2016-10-18 19:28:12 +0000307; SSE-NEXT: movdqa %xmm0, %xmm2
Sanjay Patela0d8a272016-12-15 18:03:38 +0000308; SSE-NEXT: psrlq $49, %xmm2
309; SSE-NEXT: psrlq $48, %xmm0
310; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
311; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
312; SSE-NEXT: movaps %xmm0, %xmm1
313; SSE-NEXT: psrld $27, %xmm1
314; SSE-NEXT: movaps %xmm0, %xmm2
Simon Pilgrim476560a2016-10-18 19:28:12 +0000315; SSE-NEXT: psrld $25, %xmm2
316; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
Sanjay Patela0d8a272016-12-15 18:03:38 +0000317; SSE-NEXT: movaps %xmm0, %xmm1
Simon Pilgrim476560a2016-10-18 19:28:12 +0000318; SSE-NEXT: psrld $26, %xmm1
319; SSE-NEXT: psrld $24, %xmm0
320; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
321; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
322; SSE-NEXT: retq
323;
324; AVX-LABEL: combine_vec_lshr_trunc_lshr_zero1:
325; AVX: # BB#0:
326; AVX-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0
327; AVX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
328; AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
329; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
330; AVX-NEXT: vzeroupper
331; AVX-NEXT: retq
332 %1 = lshr <4 x i64> %x, <i64 48, i64 49, i64 50, i64 51>
333 %2 = trunc <4 x i64> %1 to <4 x i32>
334 %3 = lshr <4 x i32> %2, <i32 24, i32 25, i32 26, i32 27>
335 ret <4 x i32> %3
336}
337
338; fold (srl (shl x, c), c) -> (and x, cst2)
339define <4 x i32> @combine_vec_lshr_shl_mask0(<4 x i32> %x) {
340; SSE-LABEL: combine_vec_lshr_shl_mask0:
341; SSE: # BB#0:
342; SSE-NEXT: andps {{.*}}(%rip), %xmm0
343; SSE-NEXT: retq
344;
345; AVX-LABEL: combine_vec_lshr_shl_mask0:
346; AVX: # BB#0:
347; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
348; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
349; AVX-NEXT: retq
350 %1 = shl <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
351 %2 = lshr <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>
352 ret <4 x i32> %2
353}
354
355define <4 x i32> @combine_vec_lshr_shl_mask1(<4 x i32> %x) {
356; SSE-LABEL: combine_vec_lshr_shl_mask1:
357; SSE: # BB#0:
Simon Pilgrim618d3ae2016-10-20 11:10:21 +0000358; SSE-NEXT: andps {{.*}}(%rip), %xmm0
Simon Pilgrim476560a2016-10-18 19:28:12 +0000359; SSE-NEXT: retq
360;
361; AVX-LABEL: combine_vec_lshr_shl_mask1:
362; AVX: # BB#0:
Simon Pilgrim618d3ae2016-10-20 11:10:21 +0000363; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
Simon Pilgrim476560a2016-10-18 19:28:12 +0000364; AVX-NEXT: retq
365 %1 = shl <4 x i32> %x, <i32 2, i32 3, i32 4, i32 5>
366 %2 = lshr <4 x i32> %1, <i32 2, i32 3, i32 4, i32 5>
367 ret <4 x i32> %2
368}
369
370; fold (srl (sra X, Y), 31) -> (srl X, 31)
371define <4 x i32> @combine_vec_lshr_ashr_sign(<4 x i32> %x, <4 x i32> %y) {
372; SSE-LABEL: combine_vec_lshr_ashr_sign:
373; SSE: # BB#0:
374; SSE-NEXT: psrld $31, %xmm0
375; SSE-NEXT: retq
376;
377; AVX-LABEL: combine_vec_lshr_ashr_sign:
378; AVX: # BB#0:
379; AVX-NEXT: vpsrld $31, %xmm0, %xmm0
380; AVX-NEXT: retq
381 %1 = ashr <4 x i32> %x, %y
382 %2 = lshr <4 x i32> %1, <i32 31, i32 31, i32 31, i32 31>
383 ret <4 x i32> %2
384}
385
386; fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
387define <4 x i32> @combine_vec_lshr_lzcnt_bit0(<4 x i32> %x) {
388; SSE-LABEL: combine_vec_lshr_lzcnt_bit0:
389; SSE: # BB#0:
390; SSE-NEXT: pand {{.*}}(%rip), %xmm0
391; SSE-NEXT: psrld $4, %xmm0
392; SSE-NEXT: pxor {{.*}}(%rip), %xmm0
393; SSE-NEXT: retq
394;
395; AVX-LABEL: combine_vec_lshr_lzcnt_bit0:
396; AVX: # BB#0:
397; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
398; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
399; AVX-NEXT: vpsrld $4, %xmm0, %xmm0
400; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
401; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
402; AVX-NEXT: retq
403 %1 = and <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
404 %2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %1, i1 0)
405 %3 = lshr <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5>
406 ret <4 x i32> %3
407}
408
409define <4 x i32> @combine_vec_lshr_lzcnt_bit1(<4 x i32> %x) {
410; SSE-LABEL: combine_vec_lshr_lzcnt_bit1:
411; SSE: # BB#0:
412; SSE-NEXT: pand {{.*}}(%rip), %xmm0
413; SSE-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
414; SSE-NEXT: movdqa %xmm0, %xmm1
415; SSE-NEXT: pand %xmm2, %xmm1
416; SSE-NEXT: movdqa {{.*#+}} xmm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
417; SSE-NEXT: movdqa %xmm3, %xmm4
418; SSE-NEXT: pshufb %xmm1, %xmm4
419; SSE-NEXT: movdqa %xmm0, %xmm1
420; SSE-NEXT: psrlw $4, %xmm1
421; SSE-NEXT: pand %xmm2, %xmm1
422; SSE-NEXT: pxor %xmm2, %xmm2
423; SSE-NEXT: pshufb %xmm1, %xmm3
424; SSE-NEXT: pcmpeqb %xmm2, %xmm1
425; SSE-NEXT: pand %xmm4, %xmm1
426; SSE-NEXT: paddb %xmm3, %xmm1
427; SSE-NEXT: movdqa %xmm0, %xmm3
428; SSE-NEXT: pcmpeqb %xmm2, %xmm3
429; SSE-NEXT: psrlw $8, %xmm3
430; SSE-NEXT: pand %xmm1, %xmm3
431; SSE-NEXT: psrlw $8, %xmm1
432; SSE-NEXT: paddw %xmm3, %xmm1
433; SSE-NEXT: pcmpeqw %xmm2, %xmm0
434; SSE-NEXT: psrld $16, %xmm0
435; SSE-NEXT: pand %xmm1, %xmm0
436; SSE-NEXT: psrld $16, %xmm1
437; SSE-NEXT: paddd %xmm0, %xmm1
438; SSE-NEXT: psrld $5, %xmm1
439; SSE-NEXT: movdqa %xmm1, %xmm0
440; SSE-NEXT: retq
441;
442; AVX-LABEL: combine_vec_lshr_lzcnt_bit1:
443; AVX: # BB#0:
444; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
445; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
446; AVX-NEXT: vpand %xmm1, %xmm0, %xmm2
447; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
448; AVX-NEXT: vpshufb %xmm2, %xmm3, %xmm2
449; AVX-NEXT: vpsrlw $4, %xmm0, %xmm4
450; AVX-NEXT: vpand %xmm1, %xmm4, %xmm1
451; AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
452; AVX-NEXT: vpcmpeqb %xmm4, %xmm1, %xmm5
453; AVX-NEXT: vpand %xmm5, %xmm2, %xmm2
454; AVX-NEXT: vpshufb %xmm1, %xmm3, %xmm1
455; AVX-NEXT: vpaddb %xmm1, %xmm2, %xmm1
456; AVX-NEXT: vpcmpeqb %xmm4, %xmm0, %xmm2
457; AVX-NEXT: vpsrlw $8, %xmm2, %xmm2
458; AVX-NEXT: vpand %xmm2, %xmm1, %xmm2
459; AVX-NEXT: vpsrlw $8, %xmm1, %xmm1
460; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
461; AVX-NEXT: vpcmpeqw %xmm4, %xmm0, %xmm0
462; AVX-NEXT: vpsrld $16, %xmm0, %xmm0
463; AVX-NEXT: vpand %xmm0, %xmm1, %xmm0
464; AVX-NEXT: vpsrld $16, %xmm1, %xmm1
465; AVX-NEXT: vpaddd %xmm0, %xmm1, %xmm0
466; AVX-NEXT: vpsrld $5, %xmm0, %xmm0
467; AVX-NEXT: retq
468 %1 = and <4 x i32> %x, <i32 4, i32 32, i32 64, i32 128>
469 %2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %1, i1 0)
470 %3 = lshr <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5>
471 ret <4 x i32> %3
472}
473declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1)
474
475; fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
476define <4 x i32> @combine_vec_lshr_trunc_and(<4 x i32> %x, <4 x i64> %y) {
477; SSE-LABEL: combine_vec_lshr_trunc_and:
478; SSE: # BB#0:
Sanjay Patela0d8a272016-12-15 18:03:38 +0000479; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
480; SSE-NEXT: andps {{.*}}(%rip), %xmm1
481; SSE-NEXT: movaps %xmm1, %xmm2
Simon Pilgrim476560a2016-10-18 19:28:12 +0000482; SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
483; SSE-NEXT: movdqa %xmm0, %xmm3
484; SSE-NEXT: psrld %xmm2, %xmm3
Sanjay Patela0d8a272016-12-15 18:03:38 +0000485; SSE-NEXT: movaps %xmm1, %xmm2
Simon Pilgrim476560a2016-10-18 19:28:12 +0000486; SSE-NEXT: psrlq $32, %xmm2
487; SSE-NEXT: movdqa %xmm0, %xmm4
488; SSE-NEXT: psrld %xmm2, %xmm4
489; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm3[4,5,6,7]
490; SSE-NEXT: pxor %xmm2, %xmm2
491; SSE-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
492; SSE-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
493; SSE-NEXT: movdqa %xmm0, %xmm2
494; SSE-NEXT: psrld %xmm1, %xmm2
495; SSE-NEXT: psrld %xmm3, %xmm0
496; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
497; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3],xmm0[4,5],xmm4[6,7]
498; SSE-NEXT: retq
499;
500; AVX-LABEL: combine_vec_lshr_trunc_and:
501; AVX: # BB#0:
Simon Pilgrim476560a2016-10-18 19:28:12 +0000502; AVX-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
503; AVX-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
Simon Pilgrimb2ca2502016-10-19 08:57:37 +0000504; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
Simon Pilgrim476560a2016-10-18 19:28:12 +0000505; AVX-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
506; AVX-NEXT: vzeroupper
507; AVX-NEXT: retq
508 %1 = and <4 x i64> %y, <i64 15, i64 255, i64 4095, i64 65535>
509 %2 = trunc <4 x i64> %1 to <4 x i32>
510 %3 = lshr <4 x i32> %x, %2
511 ret <4 x i32> %3
512}