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Matt Arsenault0c90e952015-11-06 18:17:45 +00001//=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
Tom Stellard75aadc22012-12-11 21:25:42 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief AMDGPU specific subclass of TargetSubtarget.
12//
13//===----------------------------------------------------------------------===//
14
Matt Arsenault0c90e952015-11-06 18:17:45 +000015#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
Matt Arsenaultf59e5382015-11-06 18:23:00 +000017
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000018#include "AMDGPU.h"
Quentin Colombet61d71a12017-08-15 22:31:51 +000019#include "AMDGPUCallLowering.h"
Matt Arsenault43e92fe2016-06-24 06:30:11 +000020#include "R600FrameLowering.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000021#include "R600ISelLowering.h"
22#include "R600InstrInfo.h"
Matt Arsenault43e92fe2016-06-24 06:30:11 +000023#include "SIFrameLowering.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000024#include "SIISelLowering.h"
25#include "SIInstrInfo.h"
Valery Pykhtinfd4c4102017-03-21 13:15:46 +000026#include "SIMachineFunctionInfo.h"
Tom Stellard347ac792015-06-26 21:15:07 +000027#include "Utils/AMDGPUBaseInfo.h"
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000028#include "llvm/ADT/Triple.h"
Quentin Colombet61d71a12017-08-15 22:31:51 +000029#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
31#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000032#include "llvm/CodeGen/MachineFunction.h"
Matt Arsenault56684d42016-08-11 17:31:42 +000033#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000034#include "llvm/MC/MCInstrItineraries.h"
35#include "llvm/Support/MathExtras.h"
36#include <cassert>
37#include <cstdint>
38#include <memory>
39#include <utility>
Tom Stellard75aadc22012-12-11 21:25:42 +000040
41#define GET_SUBTARGETINFO_HEADER
42#include "AMDGPUGenSubtargetInfo.inc"
43
Tom Stellard75aadc22012-12-11 21:25:42 +000044namespace llvm {
45
Matt Arsenault43e92fe2016-06-24 06:30:11 +000046class StringRef;
Tom Stellarde99fb652015-01-20 19:33:04 +000047
Tom Stellard75aadc22012-12-11 21:25:42 +000048class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000049public:
50 enum Generation {
51 R600 = 0,
52 R700,
53 EVERGREEN,
54 NORTHERN_ISLANDS,
Tom Stellard6e1ee472013-10-29 16:37:28 +000055 SOUTHERN_ISLANDS,
Marek Olsak5df00d62014-12-07 12:18:57 +000056 SEA_ISLANDS,
57 VOLCANIC_ISLANDS,
Matt Arsenaulte823d922017-02-18 18:29:53 +000058 GFX9,
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000059 };
60
Marek Olsak4d00dd22015-03-09 15:48:09 +000061 enum {
Tom Stellard347ac792015-06-26 21:15:07 +000062 ISAVersion0_0_0,
Wei Ding7c3e5112017-06-10 03:53:19 +000063 ISAVersion6_0_0,
64 ISAVersion6_0_1,
Tom Stellard347ac792015-06-26 21:15:07 +000065 ISAVersion7_0_0,
66 ISAVersion7_0_1,
Yaxun Liu94add852016-10-26 16:37:56 +000067 ISAVersion7_0_2,
Wei Ding7c3e5112017-06-10 03:53:19 +000068 ISAVersion7_0_3,
Konstantin Zhuravlyovc40d9f22017-12-08 20:52:28 +000069 ISAVersion7_0_4,
Changpeng Fangc16be002016-01-13 20:39:25 +000070 ISAVersion8_0_1,
Changpeng Fang98317d22016-10-11 16:00:47 +000071 ISAVersion8_0_2,
Yaxun Liu94add852016-10-26 16:37:56 +000072 ISAVersion8_0_3,
Yaxun Liu94add852016-10-26 16:37:56 +000073 ISAVersion8_1_0,
Matt Arsenaulte823d922017-02-18 18:29:53 +000074 ISAVersion9_0_0,
Konstantin Zhuravlyovc40d9f22017-12-08 20:52:28 +000075 ISAVersion9_0_2
Tom Stellard347ac792015-06-26 21:15:07 +000076 };
77
Wei Ding205bfdb2017-02-10 02:15:29 +000078 enum TrapHandlerAbi {
79 TrapHandlerAbiNone = 0,
80 TrapHandlerAbiHsa = 1
81 };
82
Wei Dingf2cce022017-02-22 23:22:19 +000083 enum TrapID {
84 TrapIDHardwareReserved = 0,
85 TrapIDHSADebugTrap = 1,
86 TrapIDLLVMTrap = 2,
87 TrapIDLLVMDebugTrap = 3,
88 TrapIDDebugBreakpoint = 7,
89 TrapIDDebugReserved8 = 8,
90 TrapIDDebugReservedFE = 0xfe,
91 TrapIDDebugReservedFF = 0xff
Wei Ding205bfdb2017-02-10 02:15:29 +000092 };
93
94 enum TrapRegValues {
Wei Dingf2cce022017-02-22 23:22:19 +000095 LLVMTrapHandlerRegValue = 1
Wei Ding205bfdb2017-02-10 02:15:29 +000096 };
97
Matt Arsenault43e92fe2016-06-24 06:30:11 +000098protected:
99 // Basic subtarget description.
100 Triple TargetTriple;
Matt Arsenaultd782d052014-06-27 17:57:00 +0000101 Generation Gen;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000102 unsigned IsaVersion;
103 unsigned WavefrontSize;
104 int LocalMemorySize;
105 int LDSBankCount;
106 unsigned MaxPrivateElementSize;
107
108 // Possibly statically set by tablegen, but may want to be overridden.
Matt Arsenaultb035a572015-01-29 19:34:25 +0000109 bool FastFMAF32;
Matt Arsenaulte83690c2016-01-18 21:13:50 +0000110 bool HalfRate64Ops;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000111
112 // Dynamially set bits that enable features.
113 bool FP32Denormals;
Matt Arsenaulta6867fd2017-01-23 22:31:03 +0000114 bool FP64FP16Denormals;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000115 bool FPExceptions;
Matt Arsenault2fdf2a12017-02-21 23:35:48 +0000116 bool DX10Clamp;
Changpeng Fangb41574a2015-12-22 20:55:23 +0000117 bool FlatForGlobal;
Konstantin Zhuravlyovbe6c0ca2017-06-02 17:40:26 +0000118 bool AutoWaitcntBeforeBarrier;
Konstantin Zhuravlyoveda425e2017-10-14 15:59:07 +0000119 bool CodeObjectV3;
Tom Stellard64a9d082016-10-14 18:10:39 +0000120 bool UnalignedScratchAccess;
Matt Arsenault7f681ac2016-07-01 23:03:44 +0000121 bool UnalignedBufferAccess;
Matt Arsenaulte823d922017-02-18 18:29:53 +0000122 bool HasApertureRegs;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000123 bool EnableXNACK;
Wei Ding205bfdb2017-02-10 02:15:29 +0000124 bool TrapHandler;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000125 bool DebuggerInsertNops;
126 bool DebuggerReserveRegs;
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000127 bool DebuggerEmitPrologue;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000128
129 // Used as options.
Matt Arsenault45b98182017-11-15 00:45:43 +0000130 bool EnableHugePrivateBuffer;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000131 bool EnableVGPRSpilling;
Matt Arsenaultd9a23ab2014-07-13 02:08:26 +0000132 bool EnablePromoteAlloca;
Matt Arsenault41033282014-10-10 22:01:59 +0000133 bool EnableLoadStoreOpt;
Matt Arsenault706f9302015-07-06 16:01:58 +0000134 bool EnableUnsafeDSOffsetFolding;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000135 bool EnableSIScheduler;
136 bool DumpCode;
137
138 // Subtarget statically properties set by tablegen
139 bool FP64;
Jan Vesely39aeab42017-12-04 23:07:28 +0000140 bool FMA;
Dmitry Preobrazhenskye3271ae2018-02-05 12:45:43 +0000141 bool MIMG_R128;
Tom Stellardd7e6f132015-04-08 01:09:26 +0000142 bool IsGCN;
Tom Stellardd7e6f132015-04-08 01:09:26 +0000143 bool GCN3Encoding;
Tom Stellardd1f0f022015-04-23 19:33:54 +0000144 bool CIInsts;
Matt Arsenault2021f082017-02-18 19:12:26 +0000145 bool GFX9Insts;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000146 bool SGPRInitBug;
Matt Arsenault9d82ee72016-02-27 08:53:55 +0000147 bool HasSMemRealTime;
148 bool Has16BitInsts;
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000149 bool HasIntClamp;
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000150 bool HasVOP3PInsts;
Matt Arsenault28f52e52017-10-25 07:00:51 +0000151 bool HasMadMixInsts;
Matt Arsenaultcc88ce32016-10-12 18:00:51 +0000152 bool HasMovrel;
153 bool HasVGPRIndexMode;
Matt Arsenault7b647552016-10-28 21:55:15 +0000154 bool HasScalarStores;
Matt Arsenaultc88ba362016-10-29 04:05:06 +0000155 bool HasInv2PiInlineImm;
Sam Kolton07dbde22017-01-20 10:01:25 +0000156 bool HasSDWA;
Sam Kolton3c4933f2017-06-22 06:26:41 +0000157 bool HasSDWAOmod;
158 bool HasSDWAScalar;
159 bool HasSDWASdst;
160 bool HasSDWAMac;
Sam Koltona179d252017-06-27 15:02:23 +0000161 bool HasSDWAOutModsVOPC;
Sam Kolton07dbde22017-01-20 10:01:25 +0000162 bool HasDPP;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000163 bool FlatAddressSpace;
Matt Arsenaultacdc7652017-05-10 21:19:05 +0000164 bool FlatInstOffsets;
165 bool FlatGlobalInsts;
166 bool FlatScratchInsts;
Matt Arsenaultc37fe662017-07-20 17:42:47 +0000167 bool AddNoCarryInsts;
Changpeng Fang44dfa1d2018-01-12 21:12:19 +0000168 bool HasUnpackedD16VMem;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000169 bool R600ALUInst;
170 bool CaymanISA;
171 bool CFALUBug;
172 bool HasVertexCache;
173 short TexVTXClauseSize;
Alexander Timofeev18009562016-12-08 17:28:47 +0000174 bool ScalarizeGlobal;
Tom Stellard75aadc22012-12-11 21:25:42 +0000175
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000176 // Dummy feature to use for assembler in tablegen.
177 bool FeatureDisable;
178
Tom Stellard75aadc22012-12-11 21:25:42 +0000179 InstrItineraryData InstrItins;
Matt Arsenault56684d42016-08-11 17:31:42 +0000180 SelectionDAGTargetInfo TSInfo;
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000181 AMDGPUAS AS;
Tom Stellard75aadc22012-12-11 21:25:42 +0000182
183public:
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000184 AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
185 const TargetMachine &TM);
Eugene Zelenko2bc2f332016-12-09 22:06:55 +0000186 ~AMDGPUSubtarget() override;
187
Daniel Sandersa73f1fd2015-06-10 12:11:26 +0000188 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
189 StringRef GPU, StringRef FS);
Tom Stellard75aadc22012-12-11 21:25:42 +0000190
Matt Arsenaultf9245b72016-07-22 17:01:25 +0000191 const AMDGPUInstrInfo *getInstrInfo() const override = 0;
192 const AMDGPUFrameLowering *getFrameLowering() const override = 0;
193 const AMDGPUTargetLowering *getTargetLowering() const override = 0;
194 const AMDGPURegisterInfo *getRegisterInfo() const override = 0;
Tom Stellard000c5af2016-04-14 19:09:28 +0000195
Eric Christopherd9134482014-08-04 21:25:23 +0000196 const InstrItineraryData *getInstrItineraryData() const override {
197 return &InstrItins;
198 }
Matt Arsenaultd782d052014-06-27 17:57:00 +0000199
Matt Arsenault56684d42016-08-11 17:31:42 +0000200 // Nothing implemented, just prevent crashes on use.
201 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
202 return &TSInfo;
203 }
204
Craig Topperee7b0f32014-04-30 05:53:27 +0000205 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
Tom Stellard75aadc22012-12-11 21:25:42 +0000206
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000207 bool isAmdHsaOS() const {
208 return TargetTriple.getOS() == Triple::AMDHSA;
Matt Arsenaultd782d052014-06-27 17:57:00 +0000209 }
210
Tom Stellard0b76fc4c2016-09-16 21:34:26 +0000211 bool isMesa3DOS() const {
212 return TargetTriple.getOS() == Triple::Mesa3D;
213 }
214
Tom Stellarde88bbc32016-09-23 01:33:26 +0000215 bool isOpenCLEnv() const {
Yaxun Liua618acf2017-06-01 21:31:53 +0000216 return TargetTriple.getEnvironment() == Triple::OpenCL ||
217 TargetTriple.getEnvironmentName() == "amdgizcl";
Tom Stellarde88bbc32016-09-23 01:33:26 +0000218 }
219
Tim Renouf9f7ead32017-09-29 09:48:12 +0000220 bool isAmdPalOS() const {
221 return TargetTriple.getOS() == Triple::AMDPAL;
222 }
223
Matt Arsenaultd782d052014-06-27 17:57:00 +0000224 Generation getGeneration() const {
225 return Gen;
226 }
227
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000228 unsigned getWavefrontSize() const {
229 return WavefrontSize;
230 }
231
Matt Arsenault4eea3f32017-11-13 22:55:05 +0000232 unsigned getWavefrontSizeLog2() const {
233 return Log2_32(WavefrontSize);
234 }
235
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000236 int getLocalMemorySize() const {
237 return LocalMemorySize;
238 }
239
240 int getLDSBankCount() const {
241 return LDSBankCount;
242 }
243
244 unsigned getMaxPrivateElementSize() const {
245 return MaxPrivateElementSize;
246 }
247
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000248 AMDGPUAS getAMDGPUAS() const {
249 return AS;
250 }
251
Konstantin Zhuravlyovd971a112016-11-01 17:49:33 +0000252 bool has16BitInsts() const {
253 return Has16BitInsts;
254 }
255
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000256 bool hasIntClamp() const {
257 return HasIntClamp;
258 }
259
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000260 bool hasVOP3PInsts() const {
261 return HasVOP3PInsts;
262 }
263
Jan Veselyd1c9b612017-12-04 22:57:29 +0000264 bool hasFP64() const {
Matt Arsenaultd782d052014-06-27 17:57:00 +0000265 return FP64;
266 }
267
Dmitry Preobrazhenskye3271ae2018-02-05 12:45:43 +0000268 bool hasMIMG_R128() const {
269 return MIMG_R128;
270 }
271
Matt Arsenaultb035a572015-01-29 19:34:25 +0000272 bool hasFastFMAF32() const {
273 return FastFMAF32;
274 }
275
Matt Arsenaulte83690c2016-01-18 21:13:50 +0000276 bool hasHalfRate64Ops() const {
277 return HalfRate64Ops;
278 }
279
Matt Arsenault88701812016-06-09 23:42:48 +0000280 bool hasAddr64() const {
281 return (getGeneration() < VOLCANIC_ISLANDS);
282 }
283
Matt Arsenaultfae02982014-03-17 18:58:11 +0000284 bool hasBFE() const {
285 return (getGeneration() >= EVERGREEN);
286 }
287
Matt Arsenault6e439652014-06-10 19:00:20 +0000288 bool hasBFI() const {
289 return (getGeneration() >= EVERGREEN);
290 }
291
Matt Arsenaultfae02982014-03-17 18:58:11 +0000292 bool hasBFM() const {
293 return hasBFE();
294 }
295
Matt Arsenault60425062014-06-10 19:18:28 +0000296 bool hasBCNT(unsigned Size) const {
297 if (Size == 32)
298 return (getGeneration() >= EVERGREEN);
299
Matt Arsenault3dd43fc2014-07-18 06:07:13 +0000300 if (Size == 64)
301 return (getGeneration() >= SOUTHERN_ISLANDS);
302
303 return false;
Matt Arsenault60425062014-06-10 19:18:28 +0000304 }
305
Tom Stellard50122a52014-04-07 19:45:41 +0000306 bool hasMulU24() const {
307 return (getGeneration() >= EVERGREEN);
308 }
309
310 bool hasMulI24() const {
311 return (getGeneration() >= SOUTHERN_ISLANDS ||
312 hasCaymanISA());
313 }
314
Jan Vesely6ddb8dd2014-07-15 15:51:09 +0000315 bool hasFFBL() const {
316 return (getGeneration() >= EVERGREEN);
317 }
318
319 bool hasFFBH() const {
320 return (getGeneration() >= EVERGREEN);
321 }
322
Matt Arsenault10268f92017-02-27 22:40:39 +0000323 bool hasMed3_16() const {
324 return getGeneration() >= GFX9;
325 }
326
Matt Arsenaultee324ff2017-05-17 19:25:06 +0000327 bool hasMin3Max3_16() const {
328 return getGeneration() >= GFX9;
329 }
330
Matt Arsenaultd7e23032017-09-07 18:05:07 +0000331 bool hasMadMixInsts() const {
Matt Arsenault28f52e52017-10-25 07:00:51 +0000332 return HasMadMixInsts;
Matt Arsenaultd7e23032017-09-07 18:05:07 +0000333 }
334
Jan Vesely808fff52015-04-30 17:15:56 +0000335 bool hasCARRY() const {
336 return (getGeneration() >= EVERGREEN);
337 }
338
339 bool hasBORROW() const {
340 return (getGeneration() >= EVERGREEN);
341 }
342
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000343 bool hasCaymanISA() const {
344 return CaymanISA;
345 }
346
Jan Vesely39aeab42017-12-04 23:07:28 +0000347 bool hasFMA() const {
348 return FMA;
349 }
350
Wei Ding205bfdb2017-02-10 02:15:29 +0000351 TrapHandlerAbi getTrapHandlerAbi() const {
352 return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
353 }
354
Matt Arsenault45b98182017-11-15 00:45:43 +0000355 bool enableHugePrivateBuffer() const {
356 return EnableHugePrivateBuffer;
357 }
358
Matt Arsenaultd9a23ab2014-07-13 02:08:26 +0000359 bool isPromoteAllocaEnabled() const {
360 return EnablePromoteAlloca;
361 }
362
Matt Arsenault706f9302015-07-06 16:01:58 +0000363 bool unsafeDSOffsetFoldingEnabled() const {
364 return EnableUnsafeDSOffsetFolding;
365 }
366
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000367 bool dumpCode() const {
368 return DumpCode;
Matt Arsenaultd782d052014-06-27 17:57:00 +0000369 }
370
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000371 /// Return the amount of LDS that can be used that will not restrict the
372 /// occupancy lower than WaveCount.
Stanislav Mekhanoshin2b913b12017-02-01 22:59:50 +0000373 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
374 const Function &) const;
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000375
376 /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
377 /// the given LDS memory size is the only constraint.
Stanislav Mekhanoshin2b913b12017-02-01 22:59:50 +0000378 unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const;
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000379
Valery Pykhtinfd4c4102017-03-21 13:15:46 +0000380 unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const {
381 const auto *MFI = MF.getInfo<SIMachineFunctionInfo>();
Matthias Braunf1caa282017-12-15 22:22:58 +0000382 return getOccupancyWithLocalMemSize(MFI->getLDSSize(), MF.getFunction());
Valery Pykhtinfd4c4102017-03-21 13:15:46 +0000383 }
384
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000385 bool hasFP16Denormals() const {
Matt Arsenaulta6867fd2017-01-23 22:31:03 +0000386 return FP64FP16Denormals;
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000387 }
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000388
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000389 bool hasFP32Denormals() const {
390 return FP32Denormals;
Matt Arsenaultd782d052014-06-27 17:57:00 +0000391 }
Tom Stellard75aadc22012-12-11 21:25:42 +0000392
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000393 bool hasFP64Denormals() const {
Matt Arsenaulta6867fd2017-01-23 22:31:03 +0000394 return FP64FP16Denormals;
Matt Arsenault24ee0782016-02-12 02:40:47 +0000395 }
396
Stanislav Mekhanoshindc2890a2017-07-13 23:59:15 +0000397 bool supportsMinMaxDenormModes() const {
398 return getGeneration() >= AMDGPUSubtarget::GFX9;
399 }
400
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000401 bool hasFPExceptions() const {
402 return FPExceptions;
Marek Olsak4d00dd22015-03-09 15:48:09 +0000403 }
404
Matt Arsenault2fdf2a12017-02-21 23:35:48 +0000405 bool enableDX10Clamp() const {
406 return DX10Clamp;
407 }
408
409 bool enableIEEEBit(const MachineFunction &MF) const {
Matthias Braunf1caa282017-12-15 22:22:58 +0000410 return AMDGPU::isCompute(MF.getFunction().getCallingConv());
Matt Arsenault2fdf2a12017-02-21 23:35:48 +0000411 }
412
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000413 bool useFlatForGlobal() const {
414 return FlatForGlobal;
Tom Stellardec87f842015-05-25 16:15:54 +0000415 }
416
Matt Arsenaultcaf0ed42017-11-30 00:52:40 +0000417 /// \returns If MUBUF instructions always perform range checking, even for
418 /// buffer resources used for private memory access.
419 bool privateMemoryResourceIsRangeChecked() const {
420 return getGeneration() < AMDGPUSubtarget::GFX9;
421 }
422
Konstantin Zhuravlyovbe6c0ca2017-06-02 17:40:26 +0000423 bool hasAutoWaitcntBeforeBarrier() const {
424 return AutoWaitcntBeforeBarrier;
425 }
426
Konstantin Zhuravlyoveda425e2017-10-14 15:59:07 +0000427 bool hasCodeObjectV3() const {
428 return CodeObjectV3;
429 }
430
Matt Arsenault7f681ac2016-07-01 23:03:44 +0000431 bool hasUnalignedBufferAccess() const {
432 return UnalignedBufferAccess;
433 }
434
Tom Stellard64a9d082016-10-14 18:10:39 +0000435 bool hasUnalignedScratchAccess() const {
436 return UnalignedScratchAccess;
437 }
438
Matt Arsenaulte823d922017-02-18 18:29:53 +0000439 bool hasApertureRegs() const {
440 return HasApertureRegs;
441 }
442
Wei Ding205bfdb2017-02-10 02:15:29 +0000443 bool isTrapHandlerEnabled() const {
444 return TrapHandler;
445 }
446
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000447 bool isXNACKEnabled() const {
448 return EnableXNACK;
449 }
Tom Stellardb8fd6ef2014-12-02 22:00:07 +0000450
Matt Arsenaultb6491cc2017-01-31 01:20:54 +0000451 bool hasFlatAddressSpace() const {
452 return FlatAddressSpace;
453 }
454
Matt Arsenaultacdc7652017-05-10 21:19:05 +0000455 bool hasFlatInstOffsets() const {
456 return FlatInstOffsets;
457 }
458
459 bool hasFlatGlobalInsts() const {
460 return FlatGlobalInsts;
461 }
462
463 bool hasFlatScratchInsts() const {
464 return FlatScratchInsts;
465 }
466
Matt Arsenaulted6e8f02017-09-01 18:36:06 +0000467 bool hasD16LoadStore() const {
468 return getGeneration() >= GFX9;
469 }
470
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000471 /// Return if most LDS instructions have an m0 use that require m0 to be
472 /// iniitalized.
473 bool ldsRequiresM0Init() const {
474 return getGeneration() < GFX9;
475 }
476
Matt Arsenaultc37fe662017-07-20 17:42:47 +0000477 bool hasAddNoCarry() const {
478 return AddNoCarryInsts;
479 }
480
Changpeng Fang44dfa1d2018-01-12 21:12:19 +0000481 bool hasUnpackedD16VMem() const {
482 return HasUnpackedD16VMem;
483 }
484
Tom Stellard2f3f9852017-01-25 01:25:13 +0000485 bool isMesaKernel(const MachineFunction &MF) const {
Matthias Braunf1caa282017-12-15 22:22:58 +0000486 return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction().getCallingConv());
Tom Stellard2f3f9852017-01-25 01:25:13 +0000487 }
488
489 // Covers VS/PS/CS graphics shaders
490 bool isMesaGfxShader(const MachineFunction &MF) const {
Matthias Braunf1caa282017-12-15 22:22:58 +0000491 return isMesa3DOS() && AMDGPU::isShader(MF.getFunction().getCallingConv());
Tom Stellard2f3f9852017-01-25 01:25:13 +0000492 }
493
494 bool isAmdCodeObjectV2(const MachineFunction &MF) const {
495 return isAmdHsaOS() || isMesaKernel(MF);
Tom Stellard0b76fc4c2016-09-16 21:34:26 +0000496 }
497
Matt Arsenault4f6318f2017-11-06 17:04:37 +0000498 bool hasMad64_32() const {
499 return getGeneration() >= SEA_ISLANDS;
500 }
501
Matt Arsenaultda7a6562017-02-01 00:42:40 +0000502 bool hasFminFmaxLegacy() const {
503 return getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;
504 }
505
Stanislav Mekhanoshin53a21292017-05-23 19:54:48 +0000506 bool hasSDWA() const {
507 return HasSDWA;
508 }
509
Sam Kolton3c4933f2017-06-22 06:26:41 +0000510 bool hasSDWAOmod() const {
511 return HasSDWAOmod;
512 }
513
514 bool hasSDWAScalar() const {
515 return HasSDWAScalar;
516 }
517
518 bool hasSDWASdst() const {
519 return HasSDWASdst;
520 }
521
522 bool hasSDWAMac() const {
523 return HasSDWAMac;
524 }
525
Sam Koltona179d252017-06-27 15:02:23 +0000526 bool hasSDWAOutModsVOPC() const {
527 return HasSDWAOutModsVOPC;
Sam Kolton3c4933f2017-06-22 06:26:41 +0000528 }
529
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000530 /// \brief Returns the offset in bytes from the start of the input buffer
531 /// of the first explicit kernel argument.
Tom Stellard2f3f9852017-01-25 01:25:13 +0000532 unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const {
533 return isAmdCodeObjectV2(MF) ? 0 : 36;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000534 }
535
Tom Stellardb2869eb2016-09-09 19:28:00 +0000536 unsigned getAlignmentForImplicitArgPtr() const {
537 return isAmdHsaOS() ? 8 : 4;
538 }
539
Tom Stellard2f3f9852017-01-25 01:25:13 +0000540 unsigned getImplicitArgNumBytes(const MachineFunction &MF) const {
541 if (isMesaKernel(MF))
Tom Stellarde88bbc32016-09-23 01:33:26 +0000542 return 16;
543 if (isAmdHsaOS() && isOpenCLEnv())
544 return 32;
545 return 0;
546 }
547
Matt Arsenault869fec22017-04-17 19:48:24 +0000548 // Scratch is allocated in 256 dword per wave blocks for the entire
549 // wavefront. When viewed from the perspecive of an arbitrary workitem, this
550 // is 4-byte aligned.
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000551 unsigned getStackAlignment() const {
Matt Arsenault869fec22017-04-17 19:48:24 +0000552 return 4;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000553 }
Tom Stellard347ac792015-06-26 21:15:07 +0000554
Craig Topper5656db42014-04-29 07:57:24 +0000555 bool enableMachineScheduler() const override {
Tom Stellard83f0bce2015-01-29 16:55:25 +0000556 return true;
Andrew Trick978674b2013-09-20 05:14:41 +0000557 }
558
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000559 bool enableSubRegLiveness() const override {
560 return true;
561 }
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000562
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000563 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b;}
564 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal;}
565
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000566 /// \returns Number of execution units per compute unit supported by the
567 /// subtarget.
568 unsigned getEUsPerCU() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000569 return AMDGPU::IsaInfo::getEUsPerCU(getFeatureBits());
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000570 }
571
572 /// \returns Maximum number of work groups per compute unit supported by the
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000573 /// subtarget and limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000574 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000575 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(getFeatureBits(),
576 FlatWorkGroupSize);
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000577 }
578
579 /// \returns Maximum number of waves per compute unit supported by the
580 /// subtarget without any kind of limitation.
581 unsigned getMaxWavesPerCU() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000582 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits());
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000583 }
584
585 /// \returns Maximum number of waves per compute unit supported by the
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000586 /// subtarget and limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000587 unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000588 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits(),
589 FlatWorkGroupSize);
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000590 }
591
592 /// \returns Minimum number of waves per execution unit supported by the
593 /// subtarget.
594 unsigned getMinWavesPerEU() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000595 return AMDGPU::IsaInfo::getMinWavesPerEU(getFeatureBits());
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000596 }
597
598 /// \returns Maximum number of waves per execution unit supported by the
599 /// subtarget without any kind of limitation.
600 unsigned getMaxWavesPerEU() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000601 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits());
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000602 }
603
604 /// \returns Maximum number of waves per execution unit supported by the
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000605 /// subtarget and limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000606 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000607 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits(),
608 FlatWorkGroupSize);
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000609 }
610
611 /// \returns Minimum flat work group size supported by the subtarget.
612 unsigned getMinFlatWorkGroupSize() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000613 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(getFeatureBits());
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000614 }
615
616 /// \returns Maximum flat work group size supported by the subtarget.
617 unsigned getMaxFlatWorkGroupSize() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000618 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(getFeatureBits());
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000619 }
620
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000621 /// \returns Number of waves per work group supported by the subtarget and
622 /// limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000623 unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000624 return AMDGPU::IsaInfo::getWavesPerWorkGroup(getFeatureBits(),
625 FlatWorkGroupSize);
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000626 }
627
Matt Arsenaultb7918022017-10-23 17:09:35 +0000628 /// \returns Default range flat work group size for a calling convention.
629 std::pair<unsigned, unsigned> getDefaultFlatWorkGroupSize(CallingConv::ID CC) const;
630
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000631 /// \returns Subtarget's default pair of minimum/maximum flat work group sizes
632 /// for function \p F, or minimum/maximum flat work group sizes explicitly
633 /// requested using "amdgpu-flat-work-group-size" attribute attached to
634 /// function \p F.
635 ///
636 /// \returns Subtarget's default values if explicitly requested values cannot
637 /// be converted to integer, or violate subtarget's specifications.
638 std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
639
640 /// \returns Subtarget's default pair of minimum/maximum number of waves per
641 /// execution unit for function \p F, or minimum/maximum number of waves per
642 /// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
643 /// attached to function \p F.
644 ///
645 /// \returns Subtarget's default values if explicitly requested values cannot
646 /// be converted to integer, violate subtarget's specifications, or are not
647 /// compatible with minimum/maximum number of waves limited by flat work group
648 /// size, register usage, and/or lds usage.
649 std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
Stanislav Mekhanoshinc90347d2017-04-12 20:48:56 +0000650
651 /// Creates value range metadata on an workitemid.* inrinsic call or load.
652 bool makeLIDRangeMetadata(Instruction *I) const;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000653};
654
655class R600Subtarget final : public AMDGPUSubtarget {
656private:
657 R600InstrInfo InstrInfo;
658 R600FrameLowering FrameLowering;
659 R600TargetLowering TLInfo;
660
661public:
662 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
663 const TargetMachine &TM);
664
665 const R600InstrInfo *getInstrInfo() const override {
666 return &InstrInfo;
667 }
668
669 const R600FrameLowering *getFrameLowering() const override {
670 return &FrameLowering;
671 }
672
673 const R600TargetLowering *getTargetLowering() const override {
674 return &TLInfo;
675 }
676
677 const R600RegisterInfo *getRegisterInfo() const override {
678 return &InstrInfo.getRegisterInfo();
679 }
680
681 bool hasCFAluBug() const {
682 return CFALUBug;
683 }
684
685 bool hasVertexCache() const {
686 return HasVertexCache;
687 }
688
689 short getTexVTXClauseSize() const {
690 return TexVTXClauseSize;
691 }
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000692};
693
694class SISubtarget final : public AMDGPUSubtarget {
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000695private:
696 SIInstrInfo InstrInfo;
697 SIFrameLowering FrameLowering;
698 SITargetLowering TLInfo;
Quentin Colombet61d71a12017-08-15 22:31:51 +0000699
700 /// GlobalISel related APIs.
701 std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
702 std::unique_ptr<InstructionSelector> InstSelector;
703 std::unique_ptr<LegalizerInfo> Legalizer;
704 std::unique_ptr<RegisterBankInfo> RegBankInfo;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000705
706public:
707 SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
Matt Arsenaultc3fe46b2018-03-08 16:24:16 +0000708 const GCNTargetMachine &TM);
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000709
710 const SIInstrInfo *getInstrInfo() const override {
711 return &InstrInfo;
712 }
713
714 const SIFrameLowering *getFrameLowering() const override {
715 return &FrameLowering;
716 }
717
718 const SITargetLowering *getTargetLowering() const override {
719 return &TLInfo;
720 }
721
722 const CallLowering *getCallLowering() const override {
Quentin Colombet61d71a12017-08-15 22:31:51 +0000723 return CallLoweringInfo.get();
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000724 }
725
Tom Stellardca166212017-01-30 21:56:46 +0000726 const InstructionSelector *getInstructionSelector() const override {
Quentin Colombet61d71a12017-08-15 22:31:51 +0000727 return InstSelector.get();
Tom Stellardca166212017-01-30 21:56:46 +0000728 }
729
730 const LegalizerInfo *getLegalizerInfo() const override {
Quentin Colombet61d71a12017-08-15 22:31:51 +0000731 return Legalizer.get();
Tom Stellardca166212017-01-30 21:56:46 +0000732 }
733
734 const RegisterBankInfo *getRegBankInfo() const override {
Quentin Colombet61d71a12017-08-15 22:31:51 +0000735 return RegBankInfo.get();
Tom Stellardca166212017-01-30 21:56:46 +0000736 }
737
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000738 const SIRegisterInfo *getRegisterInfo() const override {
739 return &InstrInfo.getRegisterInfo();
740 }
741
Matt Arsenault9f5e0ef2017-01-25 04:25:02 +0000742 // XXX - Why is this here if it isn't in the default pass set?
743 bool enableEarlyIfConversion() const override {
744 return true;
745 }
746
Tom Stellard83f0bce2015-01-29 16:55:25 +0000747 void overrideSchedPolicy(MachineSchedPolicy &Policy,
Tom Stellard83f0bce2015-01-29 16:55:25 +0000748 unsigned NumRegionInstrs) const override;
749
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000750 bool isVGPRSpillingEnabled(const Function& F) const;
751
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000752 unsigned getMaxNumUserSGPRs() const {
753 return 16;
754 }
755
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000756 bool hasSMemRealTime() const {
757 return HasSMemRealTime;
758 }
759
Matt Arsenaultcc88ce32016-10-12 18:00:51 +0000760 bool hasMovrel() const {
761 return HasMovrel;
762 }
763
764 bool hasVGPRIndexMode() const {
765 return HasVGPRIndexMode;
766 }
767
Marek Olsake22fdb92017-03-21 17:00:32 +0000768 bool useVGPRIndexMode(bool UserEnable) const {
769 return !hasMovrel() || (UserEnable && hasVGPRIndexMode());
770 }
771
Matt Arsenault7b1dc2c2016-09-17 02:02:19 +0000772 bool hasScalarCompareEq64() const {
773 return getGeneration() >= VOLCANIC_ISLANDS;
774 }
775
Matt Arsenault7b647552016-10-28 21:55:15 +0000776 bool hasScalarStores() const {
777 return HasScalarStores;
778 }
779
Matt Arsenaultc88ba362016-10-29 04:05:06 +0000780 bool hasInv2PiInlineImm() const {
781 return HasInv2PiInlineImm;
782 }
783
Sam Kolton07dbde22017-01-20 10:01:25 +0000784 bool hasDPP() const {
785 return HasDPP;
786 }
787
Tom Stellardde008d32016-01-21 04:28:34 +0000788 bool enableSIScheduler() const {
789 return EnableSIScheduler;
790 }
791
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000792 bool debuggerSupported() const {
793 return debuggerInsertNops() && debuggerReserveRegs() &&
794 debuggerEmitPrologue();
795 }
796
Konstantin Zhuravlyov8c273ad2016-04-18 16:28:23 +0000797 bool debuggerInsertNops() const {
798 return DebuggerInsertNops;
799 }
800
Konstantin Zhuravlyov29ddd2b2016-05-24 18:37:18 +0000801 bool debuggerReserveRegs() const {
802 return DebuggerReserveRegs;
Konstantin Zhuravlyov1d99c4d2016-04-26 15:43:14 +0000803 }
804
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000805 bool debuggerEmitPrologue() const {
806 return DebuggerEmitPrologue;
807 }
808
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000809 bool loadStoreOptEnabled() const {
810 return EnableLoadStoreOpt;
Nicolai Haehnle5b504972016-01-04 23:35:53 +0000811 }
812
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000813 bool hasSGPRInitBug() const {
814 return SGPRInitBug;
Matt Arsenault41003af2015-11-30 21:16:07 +0000815 }
Tom Stellard0d23ebe2016-08-29 19:42:52 +0000816
Tom Stellardb133fbb2016-10-27 23:05:31 +0000817 bool has12DWordStoreHazard() const {
818 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
819 }
820
Matt Arsenaulte823d922017-02-18 18:29:53 +0000821 bool hasSMovFedHazard() const {
822 return getGeneration() >= AMDGPUSubtarget::GFX9;
823 }
824
Matt Arsenaulta41351e2017-11-17 21:35:32 +0000825 bool hasReadM0MovRelInterpHazard() const {
Matt Arsenaulte823d922017-02-18 18:29:53 +0000826 return getGeneration() >= AMDGPUSubtarget::GFX9;
827 }
828
Matt Arsenaulta41351e2017-11-17 21:35:32 +0000829 bool hasReadM0SendMsgHazard() const {
830 return getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
831 }
832
Matt Arsenault9166ce82017-07-28 15:52:08 +0000833 unsigned getKernArgSegmentSize(const MachineFunction &MF,
834 unsigned ExplictArgBytes) const;
Tom Stellarde88bbc32016-09-23 01:33:26 +0000835
Tom Stellard0d23ebe2016-08-29 19:42:52 +0000836 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs SGPRs
837 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
838
839 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs VGPRs
840 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
Konstantin Zhuravlyovd7bdf242016-09-30 16:50:36 +0000841
Matt Arsenaulte823d922017-02-18 18:29:53 +0000842 /// \returns true if the flat_scratch register should be initialized with the
843 /// pointer to the wave's scratch memory rather than a size and offset.
844 bool flatScratchIsPointer() const {
845 return getGeneration() >= GFX9;
Konstantin Zhuravlyovd7bdf242016-09-30 16:50:36 +0000846 }
Matt Arsenault4eae3012016-10-28 20:31:47 +0000847
Tim Renouf832f90f2018-02-26 14:46:43 +0000848 /// \returns true if the machine has merged shaders in which s0-s7 are
849 /// reserved by the hardware and user SGPRs start at s8
850 bool hasMergedShaders() const {
851 return getGeneration() >= GFX9;
852 }
853
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000854 /// \returns SGPR allocation granularity supported by the subtarget.
855 unsigned getSGPRAllocGranule() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000856 return AMDGPU::IsaInfo::getSGPRAllocGranule(getFeatureBits());
Konstantin Zhuravlyove22fbcb2017-02-08 13:18:40 +0000857 }
858
859 /// \returns SGPR encoding granularity supported by the subtarget.
860 unsigned getSGPREncodingGranule() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000861 return AMDGPU::IsaInfo::getSGPREncodingGranule(getFeatureBits());
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000862 }
863
864 /// \returns Total number of SGPRs supported by the subtarget.
865 unsigned getTotalNumSGPRs() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000866 return AMDGPU::IsaInfo::getTotalNumSGPRs(getFeatureBits());
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000867 }
868
869 /// \returns Addressable number of SGPRs supported by the subtarget.
870 unsigned getAddressableNumSGPRs() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000871 return AMDGPU::IsaInfo::getAddressableNumSGPRs(getFeatureBits());
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000872 }
873
874 /// \returns Minimum number of SGPRs that meets the given number of waves per
875 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000876 unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
877 return AMDGPU::IsaInfo::getMinNumSGPRs(getFeatureBits(), WavesPerEU);
878 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000879
880 /// \returns Maximum number of SGPRs that meets the given number of waves per
881 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000882 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
883 return AMDGPU::IsaInfo::getMaxNumSGPRs(getFeatureBits(), WavesPerEU,
884 Addressable);
885 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000886
887 /// \returns Reserved number of SGPRs for given function \p MF.
888 unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
889
890 /// \returns Maximum number of SGPRs that meets number of waves per execution
891 /// unit requirement for function \p MF, or number of SGPRs explicitly
892 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
893 ///
894 /// \returns Value that meets number of waves per execution unit requirement
895 /// if explicitly requested value cannot be converted to integer, violates
896 /// subtarget's specifications, or does not meet number of waves per execution
897 /// unit requirement.
898 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
899
900 /// \returns VGPR allocation granularity supported by the subtarget.
901 unsigned getVGPRAllocGranule() const {
Mandeep Singh Grang5e1697e2017-06-06 05:08:36 +0000902 return AMDGPU::IsaInfo::getVGPRAllocGranule(getFeatureBits());
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000903 }
904
Konstantin Zhuravlyove22fbcb2017-02-08 13:18:40 +0000905 /// \returns VGPR encoding granularity supported by the subtarget.
906 unsigned getVGPREncodingGranule() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000907 return AMDGPU::IsaInfo::getVGPREncodingGranule(getFeatureBits());
Konstantin Zhuravlyove22fbcb2017-02-08 13:18:40 +0000908 }
909
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000910 /// \returns Total number of VGPRs supported by the subtarget.
911 unsigned getTotalNumVGPRs() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000912 return AMDGPU::IsaInfo::getTotalNumVGPRs(getFeatureBits());
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000913 }
914
915 /// \returns Addressable number of VGPRs supported by the subtarget.
916 unsigned getAddressableNumVGPRs() const {
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000917 return AMDGPU::IsaInfo::getAddressableNumVGPRs(getFeatureBits());
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000918 }
919
920 /// \returns Minimum number of VGPRs that meets given number of waves per
921 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000922 unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
923 return AMDGPU::IsaInfo::getMinNumVGPRs(getFeatureBits(), WavesPerEU);
924 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000925
926 /// \returns Maximum number of VGPRs that meets given number of waves per
927 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000928 unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
929 return AMDGPU::IsaInfo::getMaxNumVGPRs(getFeatureBits(), WavesPerEU);
930 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000931
932 /// \returns Reserved number of VGPRs for given function \p MF.
933 unsigned getReservedNumVGPRs(const MachineFunction &MF) const {
934 return debuggerReserveRegs() ? 4 : 0;
935 }
936
937 /// \returns Maximum number of VGPRs that meets number of waves per execution
938 /// unit requirement for function \p MF, or number of VGPRs explicitly
939 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
940 ///
941 /// \returns Value that meets number of waves per execution unit requirement
942 /// if explicitly requested value cannot be converted to integer, violates
943 /// subtarget's specifications, or does not meet number of waves per execution
944 /// unit requirement.
945 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
Stanislav Mekhanoshind4ae4702017-09-19 20:54:38 +0000946
947 void getPostRAMutations(
948 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
949 const override;
Tom Stellard75aadc22012-12-11 21:25:42 +0000950};
951
Eugene Zelenko2bc2f332016-12-09 22:06:55 +0000952} // end namespace llvm
Tom Stellard75aadc22012-12-11 21:25:42 +0000953
Eugene Zelenko2bc2f332016-12-09 22:06:55 +0000954#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H