blob: f68c909513153b0f8a82aee72e6c06be72c921b0 [file] [log] [blame]
Matt Arsenault9c47dd52016-02-11 06:02:01 +00001; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
2; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +00003
Matt Arsenault9c47dd52016-02-11 06:02:01 +00004declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
5declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
6declare void @llvm.amdgcn.s.barrier() #2
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +00007
8; The required pointer calculations for the alloca'd actually requires
9; an add and won't be folded into the addressing, which fails with a
10; 64-bit pointer add. This should work since private pointers should
11; be 32-bits.
12
Tom Stellard79243d92014-10-01 17:15:17 +000013; SI-LABEL: {{^}}test_private_array_ptr_calc:
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +000014
Tom Stellardb02094e2014-07-21 15:45:01 +000015; FIXME: We end up with zero argument for ADD, because
16; SIRegisterInfo::eliminateFrameIndex() blindly replaces the frame index
17; with the appropriate offset. We should fold this into the store.
Matt Arsenaultc10783c2016-04-16 02:13:37 +000018
Matt Arsenaulte4d0c142015-08-29 07:16:50 +000019; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 0, v{{[0-9]+}}
Matt Arsenaultc5fce692016-04-28 18:38:48 +000020; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64
Matt Arsenaultc10783c2016-04-16 02:13:37 +000021; SI-ALLOCA: s_barrier
Matt Arsenaultc5fce692016-04-28 18:38:48 +000022; SI-ALLOCA: buffer_load_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64
Tom Stellard880a80a2014-06-17 16:53:14 +000023;
24; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this
25; alloca to a vector. It currently fails because it does not know how
26; to interpret:
Matt Arsenaultc5fce692016-04-28 18:38:48 +000027; getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 1, i32 %b
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +000028
Matt Arsenaultc5fce692016-04-28 18:38:48 +000029; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 64
Tom Stellard326d6ec2014-11-05 14:50:53 +000030; SI-PROMOTE: ds_write_b32 [[PTRREG]]
Matt Arsenault9c47dd52016-02-11 06:02:01 +000031define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) #0 {
Matt Arsenaultc5fce692016-04-28 18:38:48 +000032 %alloca = alloca [16 x i32], align 16
Matt Arsenault9c47dd52016-02-11 06:02:01 +000033 %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0);
34 %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo)
Matt Arsenaultde420812016-02-02 21:16:12 +000035 %a_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inA, i32 %tid
36 %b_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inB, i32 %tid
David Blaikiea79ac142015-02-27 21:17:42 +000037 %a = load i32, i32 addrspace(1)* %a_ptr
38 %b = load i32, i32 addrspace(1)* %b_ptr
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +000039 %result = add i32 %a, %b
Matt Arsenaultc5fce692016-04-28 18:38:48 +000040 %alloca_ptr = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 1, i32 %b
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +000041 store i32 %result, i32* %alloca_ptr, align 4
42 ; Dummy call
Matt Arsenault9c47dd52016-02-11 06:02:01 +000043 call void @llvm.amdgcn.s.barrier()
David Blaikiea79ac142015-02-27 21:17:42 +000044 %reload = load i32, i32* %alloca_ptr, align 4
Matt Arsenaultde420812016-02-02 21:16:12 +000045 %out_ptr = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +000046 store i32 %reload, i32 addrspace(1)* %out_ptr, align 4
47 ret void
48}
49
Matt Arsenault9c47dd52016-02-11 06:02:01 +000050attributes #0 = { nounwind }
51attributes #1 = { nounwind readnone }
52attributes #2 = { nounwind convergent }