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Evan Cheng12a02222008-06-04 09:18:41 +00001//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the live stack slot analysis pass. It is analogous to
11// live interval analysis except it's analyzing liveness of stack slots rather
12// than registers.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "livestacks"
17#include "llvm/CodeGen/LiveStackAnalysis.h"
Lang Hamesfc968ef2009-06-02 16:53:25 +000018#include "llvm/CodeGen/LiveIntervalAnalysis.h"
Evan Cheng12a02222008-06-04 09:18:41 +000019#include "llvm/CodeGen/Passes.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/Support/Debug.h"
Chris Lattnerd99f1c62009-08-23 03:47:42 +000022#include "llvm/Support/raw_ostream.h"
Evan Cheng12a02222008-06-04 09:18:41 +000023#include "llvm/ADT/Statistic.h"
Lang Hamesfc968ef2009-06-02 16:53:25 +000024#include <limits>
Evan Cheng12a02222008-06-04 09:18:41 +000025using namespace llvm;
26
27char LiveStacks::ID = 0;
Evan Chengb53825b2012-09-21 20:04:28 +000028INITIALIZE_PASS_BEGIN(LiveStacks, "livestacks",
29 "Live Stack Slot Analysis", false, false)
30INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
31INITIALIZE_PASS_END(LiveStacks, "livestacks",
Owen Andersondf7a4f22010-10-07 22:25:06 +000032 "Live Stack Slot Analysis", false, false)
Evan Cheng12a02222008-06-04 09:18:41 +000033
Jakob Stoklund Olesen7cdc1e52010-10-26 00:11:33 +000034char &llvm::LiveStacksID = LiveStacks::ID;
35
Evan Cheng12a02222008-06-04 09:18:41 +000036void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
Evan Chengbab59882008-09-22 22:26:15 +000037 AU.setPreservesAll();
Lang Hames05fb9632009-11-03 23:52:08 +000038 AU.addPreserved<SlotIndexes>();
39 AU.addRequiredTransitive<SlotIndexes>();
Evan Cheng168f8f32008-09-22 20:58:04 +000040 MachineFunctionPass::getAnalysisUsage(AU);
Evan Cheng12a02222008-06-04 09:18:41 +000041}
42
43void LiveStacks::releaseMemory() {
Benjamin Kramera0000022010-06-26 11:30:59 +000044 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
45 VNInfoAllocator.Reset();
Evan Cheng210fc622009-05-03 18:32:42 +000046 S2IMap.clear();
47 S2RCMap.clear();
Evan Cheng12a02222008-06-04 09:18:41 +000048}
49
Jakob Stoklund Olesen1352be22011-09-30 22:18:51 +000050bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
51 TRI = MF.getTarget().getRegisterInfo();
Evan Cheng12a02222008-06-04 09:18:41 +000052 // FIXME: No analysis is being done right now. We are relying on the
53 // register allocators to provide the information.
54 return false;
55}
56
Jakob Stoklund Olesenb83a6b22011-01-09 21:17:37 +000057LiveInterval &
58LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
59 assert(Slot >= 0 && "Spill slot indice must be >= 0");
60 SS2IntervalMap::iterator I = S2IMap.find(Slot);
61 if (I == S2IMap.end()) {
62 I = S2IMap.insert(I, std::make_pair(Slot,
63 LiveInterval(TargetRegisterInfo::index2StackSlot(Slot), 0.0F)));
64 S2RCMap.insert(std::make_pair(Slot, RC));
65 } else {
66 // Use the largest common subclass register class.
67 const TargetRegisterClass *OldRC = S2RCMap[Slot];
Jakob Stoklund Olesen1352be22011-09-30 22:18:51 +000068 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
Jakob Stoklund Olesenb83a6b22011-01-09 21:17:37 +000069 }
70 return I->second;
71}
72
Evan Cheng12a02222008-06-04 09:18:41 +000073/// print - Implement the dump method.
Chris Lattner13626022009-08-23 06:03:38 +000074void LiveStacks::print(raw_ostream &OS, const Module*) const {
Chris Lattnerd99f1c62009-08-23 03:47:42 +000075
76 OS << "********** INTERVALS **********\n";
Evan Cheng12a02222008-06-04 09:18:41 +000077 for (const_iterator I = begin(), E = end(); I != E; ++I) {
Chris Lattnerd99f1c62009-08-23 03:47:42 +000078 I->second.print(OS);
Evan Cheng210fc622009-05-03 18:32:42 +000079 int Slot = I->first;
80 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
81 if (RC)
Chris Lattnerd99f1c62009-08-23 03:47:42 +000082 OS << " [" << RC->getName() << "]\n";
Evan Cheng210fc622009-05-03 18:32:42 +000083 else
Chris Lattnerd99f1c62009-08-23 03:47:42 +000084 OS << " [Unknown]\n";
Evan Cheng12a02222008-06-04 09:18:41 +000085 }
86}