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Dylan McKay6d8078f2016-05-06 10:12:31 +00001//===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the AVR implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_AVR_INSTR_INFO_H
15#define LLVM_AVR_INSTR_INFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18
19#include "AVRRegisterInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "AVRGenInstrInfo.inc"
23#undef GET_INSTRINFO_HEADER
24
25namespace llvm {
26
27namespace AVRCC {
28
29/// AVR specific condition codes.
30/// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
31/// They must be kept in synch.
32enum CondCodes {
33 COND_EQ, //!< Equal
34 COND_NE, //!< Not equal
35 COND_GE, //!< Greater than or equal
36 COND_LT, //!< Less than
37 COND_SH, //!< Unsigned same or higher
38 COND_LO, //!< Unsigned lower
39 COND_MI, //!< Minus
40 COND_PL, //!< Plus
41 COND_INVALID
42};
43
44} // end of namespace AVRCC
45
46namespace AVRII {
47
48/// Specifies a target operand flag.
49enum TOF {
50 MO_NO_FLAG,
51
52 /// On a symbol operand, this represents the lo part.
53 MO_LO = (1 << 1),
54
55 /// On a symbol operand, this represents the hi part.
56 MO_HI = (1 << 2),
57
58 /// On a symbol operand, this represents it has to be negated.
59 MO_NEG = (1 << 3)
60};
61
62} // end of namespace AVRII
63
Dylan McKayd56676e2016-05-18 09:43:01 +000064/// Utilities related to the AVR instruction set.
Dylan McKay6d8078f2016-05-06 10:12:31 +000065class AVRInstrInfo : public AVRGenInstrInfo {
66public:
67 explicit AVRInstrInfo();
68
69 const AVRRegisterInfo &getRegisterInfo() const { return RI; }
70 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
71 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
72 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
Job Noorman6cd8c9a2016-08-16 08:41:35 +000073 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
Dylan McKay6d8078f2016-05-06 10:12:31 +000074
75 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
Benjamin Kramerbdc49562016-06-12 15:39:02 +000076 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
Dylan McKay6d8078f2016-05-06 10:12:31 +000077 bool KillSrc) const override;
78 void storeRegToStackSlot(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI, unsigned SrcReg,
80 bool isKill, int FrameIndex,
81 const TargetRegisterClass *RC,
82 const TargetRegisterInfo *TRI) const override;
83 void loadRegFromStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI, unsigned DestReg,
85 int FrameIndex, const TargetRegisterClass *RC,
86 const TargetRegisterInfo *TRI) const override;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +000087 unsigned isLoadFromStackSlot(const MachineInstr &MI,
Dylan McKay6d8078f2016-05-06 10:12:31 +000088 int &FrameIndex) const override;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +000089 unsigned isStoreToStackSlot(const MachineInstr &MI,
Dylan McKay6d8078f2016-05-06 10:12:31 +000090 int &FrameIndex) const override;
91
92 // Branch analysis.
Jacques Pienaar71c30a12016-07-15 14:41:04 +000093 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
Dylan McKay6d8078f2016-05-06 10:12:31 +000094 MachineBasicBlock *&FBB,
95 SmallVectorImpl<MachineOperand> &Cond,
96 bool AllowModify = false) const override;
97 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
98 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
Benjamin Kramerbdc49562016-06-12 15:39:02 +000099 const DebugLoc &DL) const override;
Dylan McKay6d8078f2016-05-06 10:12:31 +0000100 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
101 bool
102 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
103
104private:
105 const AVRRegisterInfo RI;
106};
107
108} // end namespace llvm
109
110#endif // LLVM_AVR_INSTR_INFO_H