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gerrit-public.fairphone.software / toolchain / llvm-project / 21fb07b7157311fd2625805d83a3b23689e554fe / . / llvm / test / CodeGen / X86 / vector-shuffle-combining-sse4a.ll
blob: 1669317f4aa66777b23d754d5154c549f30b398a [file] [log] [blame]
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Simon Pilgrimb5c68a62017-07-03 15:55:54 +0000[diff] [blame]2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2,+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE42
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]4; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,+sse4a| FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2,+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
6;
Simon Pilgrimb5c68a62017-07-03 15:55:54 +0000[diff] [blame]7; Combine tests involving SSE4A target shuffles (EXTRQI,INSERTQI)
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]8
9declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
10
11define <16 x i8> @combine_extrqi_pshufb_16i8(<16 x i8> %a0) {
12; SSE-LABEL: combine_extrqi_pshufb_16i8:
13; SSE: # BB#0:
Simon Pilgrimfa6e6752017-07-03 20:58:16 +0000[diff] [blame]14; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[1,2],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]15; SSE-NEXT: retq
16;
17; AVX-LABEL: combine_extrqi_pshufb_16i8:
18; AVX: # BB#0:
Simon Pilgrimfa6e6752017-07-03 20:58:16 +0000[diff] [blame]19; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,2],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]20; AVX-NEXT: retq
21 %1 = shufflevector <16 x i8> %a0, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 2, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
22 %2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 255, i8 255, i8 255, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>)
23 ret <16 x i8> %2
24}
25
26define <8 x i16> @combine_extrqi_pshufb_8i16(<8 x i16> %a0) {
Simon Pilgrimac3e7f32017-07-04 18:11:02 +0000[diff] [blame]27; SSE-LABEL: combine_extrqi_pshufb_8i16:
28; SSE: # BB#0:
29; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[2,3],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
30; SSE-NEXT: retq
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]31;
32; AVX-LABEL: combine_extrqi_pshufb_8i16:
33; AVX: # BB#0:
Simon Pilgrimac3e7f32017-07-04 18:11:02 +0000[diff] [blame]34; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,3],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]35; AVX-NEXT: retq
36 %1 = shufflevector <8 x i16> %a0, <8 x i16> zeroinitializer, <8 x i32> <i32 1, i32 2, i32 8, i32 8, i32 undef, i32 undef, i32 undef, i32 undef>
37 %2 = bitcast <8 x i16> %1 to <16 x i8>
38 %3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 0, i8 1, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>)
39 %4 = bitcast <16 x i8> %3 to <8 x i16>
40 ret <8 x i16> %4
41}
42
43define <16 x i8> @combine_insertqi_pshufb_16i8(<16 x i8> %a0, <16 x i8> %a1) {
Simon Pilgrimb5c68a62017-07-03 15:55:54 +0000[diff] [blame]44; SSSE3-LABEL: combine_insertqi_pshufb_16i8:
45; SSSE3: # BB#0:
Simon Pilgrimfa6e6752017-07-03 20:58:16 +0000[diff] [blame]46; SSSE3-NEXT: movl $65535, %eax # imm = 0xFFFF
47; SSSE3-NEXT: movd %eax, %xmm0
48; SSSE3-NEXT: pand %xmm1, %xmm0
Simon Pilgrimb5c68a62017-07-03 15:55:54 +0000[diff] [blame]49; SSSE3-NEXT: retq
50;
51; SSE42-LABEL: combine_insertqi_pshufb_16i8:
52; SSE42: # BB#0:
Simon Pilgrimfa6e6752017-07-03 20:58:16 +0000[diff] [blame]53; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
Simon Pilgrimb5c68a62017-07-03 15:55:54 +0000[diff] [blame]54; SSE42-NEXT: retq
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]55;
56; AVX-LABEL: combine_insertqi_pshufb_16i8:
57; AVX: # BB#0:
Simon Pilgrimfa6e6752017-07-03 20:58:16 +0000[diff] [blame]58; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]59; AVX-NEXT: retq
60 %1 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
61 %2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>)
62 ret <16 x i8> %2
63}
64
65define <8 x i16> @combine_insertqi_pshufb_8i16(<8 x i16> %a0, <8 x i16> %a1) {
Simon Pilgrimb5c68a62017-07-03 15:55:54 +0000[diff] [blame]66; SSSE3-LABEL: combine_insertqi_pshufb_8i16:
67; SSSE3: # BB#0:
Simon Pilgrimac3e7f32017-07-04 18:11:02 +0000[diff] [blame]68; SSSE3-NEXT: movl $65535, %eax # imm = 0xFFFF
69; SSSE3-NEXT: movd %eax, %xmm0
70; SSSE3-NEXT: pand %xmm1, %xmm0
Simon Pilgrimb5c68a62017-07-03 15:55:54 +0000[diff] [blame]71; SSSE3-NEXT: retq
72;
73; SSE42-LABEL: combine_insertqi_pshufb_8i16:
74; SSE42: # BB#0:
Simon Pilgrimac3e7f32017-07-04 18:11:02 +0000[diff] [blame]75; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
Simon Pilgrimb5c68a62017-07-03 15:55:54 +0000[diff] [blame]76; SSE42-NEXT: retq
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]77;
78; AVX-LABEL: combine_insertqi_pshufb_8i16:
79; AVX: # BB#0:
Simon Pilgrimac3e7f32017-07-04 18:11:02 +0000[diff] [blame]80; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
Simon Pilgrimdecfaca2017-07-03 15:01:07 +0000[diff] [blame]81; AVX-NEXT: retq
82 %1 = shufflevector <8 x i16> %a0, <8 x i16> %a1, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
83 %2 = bitcast <8 x i16> %1 to <16 x i8>
84 %3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 0, i8 1, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>)
85 %4 = bitcast <16 x i8> %3 to <8 x i16>
86 ret <8 x i16> %4
87}