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gerrit-public.fairphone.software / toolchain / llvm-project / cd2a1b5341a3c42b1a56f8f301bd0de0343b5e8e / . / llvm / test / CodeGen / SystemZ / vec-args-04.ll
blob: 3a25404934e23518250b0293ae25098d5719fe9e [file] [log] [blame]
Ulrich Weigandcd2a1b52015-05-05 19:29:21 +0000[diff] [blame^]1; Test the handling of named short vector arguments.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK
5
6; This routine has 12 vector arguments, which fill up %v24-%v31
7; and the four single-wide stack slots starting at 160.
8declare void @bar(<1 x i8>, <2 x i8>, <4 x i8>, <8 x i8>,
9 <1 x i8>, <2 x i8>, <4 x i8>, <8 x i8>,
10 <1 x i8>, <2 x i8>, <4 x i8>, <8 x i8>)
11
12define void @foo() {
13; CHECK-VEC-LABEL: foo:
14; CHECK-VEC-DAG: vrepib %v24, 1
15; CHECK-VEC-DAG: vrepib %v26, 2
16; CHECK-VEC-DAG: vrepib %v28, 3
17; CHECK-VEC-DAG: vrepib %v30, 4
18; CHECK-VEC-DAG: vrepib %v25, 5
19; CHECK-VEC-DAG: vrepib %v27, 6
20; CHECK-VEC-DAG: vrepib %v29, 7
21; CHECK-VEC-DAG: vrepib %v31, 8
22; CHECK-VEC: brasl %r14, bar@PLT
23;
24; CHECK-STACK-LABEL: foo:
25; CHECK-STACK: aghi %r15, -192
26; CHECK-STACK-DAG: llihh [[REG1:%r[0-9]+]], 2304
27; CHECK-STACK-DAG: stg [[REG1]], 160(%r15)
28; CHECK-STACK-DAG: llihh [[REG2:%r[0-9]+]], 2570
29; CHECK-STACK-DAG: stg [[REG2]], 168(%r15)
30; CHECK-STACK-DAG: llihf [[REG3:%r[0-9]+]], 185273099
31; CHECK-STACK-DAG: stg [[REG3]], 176(%r15)
32; CHECK-STACK-DAG: llihf [[REG4:%r[0-9]+]], 202116108
33; CHECK-STACK-DAG: oilf [[REG4]], 202116108
34; CHECK-STACK-DAG: stg [[REG4]], 176(%r15)
35; CHECK-STACK: brasl %r14, bar@PLT
36
37 call void @bar (<1 x i8> <i8 1>,
38 <2 x i8> <i8 2, i8 2>,
39 <4 x i8> <i8 3, i8 3, i8 3, i8 3>,
40 <8 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>,
41 <1 x i8> <i8 5>,
42 <2 x i8> <i8 6, i8 6>,
43 <4 x i8> <i8 7, i8 7, i8 7, i8 7>,
44 <8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>,
45 <1 x i8> <i8 9>,
46 <2 x i8> <i8 10, i8 10>,
47 <4 x i8> <i8 11, i8 11, i8 11, i8 11>,
48 <8 x i8> <i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12>)
49 ret void
50}