Blame - clang/lib/Headers/avx512vlintrin.h - toolchain/llvm-project

blob: fd18e7177b778fd09675ec7aaa254c5f90639238 [file] [log] [blame]

Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	1	/*===---- avx512vlintrin.h - AVX512VL intrinsics ---------------------------===
				2	*
				3	* Permission is hereby granted, free of charge, to any person obtaining a copy
				4	* of this software and associated documentation files (the "Software"), to deal
				5	* in the Software without restriction, including without limitation the rights
				6	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
				7	* copies of the Software, and to permit persons to whom the Software is
				8	* furnished to do so, subject to the following conditions:
				9	*
				10	* The above copyright notice and this permission notice shall be included in
				11	* all copies or substantial portions of the Software.
				12	*
				13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
				14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
				15	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
				16	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
				17	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
				18	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
				19	* THE SOFTWARE.
				20	*
				21	*===-----------------------------------------------------------------------===
				22	*/
				23
				24	#ifndef __IMMINTRIN_H
				25	#error "Never use <avx512vlintrin.h> directly; include <immintrin.h> instead."
				26	#endif
				27
				28	#ifndef __AVX512VLINTRIN_H
				29	#define __AVX512VLINTRIN_H
				30
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	31	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vl")))
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	32	#define __DEFAULT_FN_ATTRS_BOTH __attribute__((__always_inline__, __nodebug__, __target__("avx512vl, avx512bw")))
Eric Christopher	4d185168	2015-06-17 07:09:20 +0000	[diff] [blame]	33
Michael Zuckerman	38a2727	2016-02-22 09:05:41 +0000	[diff] [blame]	34	static __inline __v2di __DEFAULT_FN_ATTRS
				35	_mm_setzero_di(void) {
				36	return (__v2di){ 0, 0};
				37	}
				38
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	39	/* Integer compare */
				40
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	41	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	42	_mm_cmpeq_epi32_mask(__m128i __a, __m128i __b) {
				43	return (__mmask8)__builtin_ia32_pcmpeqd128_mask((__v4si)__a, (__v4si)__b,
				44	(__mmask8)-1);
				45	}
				46
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	47	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	48	_mm_mask_cmpeq_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				49	return (__mmask8)__builtin_ia32_pcmpeqd128_mask((__v4si)__a, (__v4si)__b,
				50	__u);
				51	}
				52
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	53	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	54	_mm_cmpeq_epu32_mask(__m128i __a, __m128i __b) {
				55	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 0,
				56	(__mmask8)-1);
				57	}
				58
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	59	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	60	_mm_mask_cmpeq_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				61	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 0,
				62	__u);
				63	}
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	64
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	65	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	66	_mm256_cmpeq_epi32_mask(__m256i __a, __m256i __b) {
				67	return (__mmask8)__builtin_ia32_pcmpeqd256_mask((__v8si)__a, (__v8si)__b,
				68	(__mmask8)-1);
				69	}
				70
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	71	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	72	_mm256_mask_cmpeq_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				73	return (__mmask8)__builtin_ia32_pcmpeqd256_mask((__v8si)__a, (__v8si)__b,
				74	__u);
				75	}
				76
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	77	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	78	_mm256_cmpeq_epu32_mask(__m256i __a, __m256i __b) {
				79	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 0,
				80	(__mmask8)-1);
				81	}
				82
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	83	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	84	_mm256_mask_cmpeq_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				85	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 0,
				86	__u);
				87	}
				88
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	89	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	90	_mm_cmpeq_epi64_mask(__m128i __a, __m128i __b) {
				91	return (__mmask8)__builtin_ia32_pcmpeqq128_mask((__v2di)__a, (__v2di)__b,
				92	(__mmask8)-1);
				93	}
				94
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	95	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	96	_mm_mask_cmpeq_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				97	return (__mmask8)__builtin_ia32_pcmpeqq128_mask((__v2di)__a, (__v2di)__b,
				98	__u);
				99	}
				100
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	101	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	102	_mm_cmpeq_epu64_mask(__m128i __a, __m128i __b) {
				103	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 0,
				104	(__mmask8)-1);
				105	}
				106
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	107	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	108	_mm_mask_cmpeq_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				109	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 0,
				110	__u);
				111	}
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	112
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	113	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	114	_mm256_cmpeq_epi64_mask(__m256i __a, __m256i __b) {
				115	return (__mmask8)__builtin_ia32_pcmpeqq256_mask((__v4di)__a, (__v4di)__b,
				116	(__mmask8)-1);
				117	}
				118
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	119	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	120	_mm256_mask_cmpeq_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				121	return (__mmask8)__builtin_ia32_pcmpeqq256_mask((__v4di)__a, (__v4di)__b,
				122	__u);
				123	}
				124
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	125	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	126	_mm256_cmpeq_epu64_mask(__m256i __a, __m256i __b) {
				127	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 0,
				128	(__mmask8)-1);
				129	}
				130
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	131	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	132	_mm256_mask_cmpeq_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				133	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 0,
				134	__u);
				135	}
				136
				137
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	138	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	139	_mm_cmpge_epi32_mask(__m128i __a, __m128i __b) {
				140	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 5,
				141	(__mmask8)-1);
				142	}
				143
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	144	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	145	_mm_mask_cmpge_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				146	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 5,
				147	__u);
				148	}
				149
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	150	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	151	_mm_cmpge_epu32_mask(__m128i __a, __m128i __b) {
				152	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 5,
				153	(__mmask8)-1);
				154	}
				155
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	156	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	157	_mm_mask_cmpge_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				158	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 5,
				159	__u);
				160	}
				161
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	162	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	163	_mm256_cmpge_epi32_mask(__m256i __a, __m256i __b) {
				164	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 5,
				165	(__mmask8)-1);
				166	}
				167
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	168	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	169	_mm256_mask_cmpge_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				170	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 5,
				171	__u);
				172	}
				173
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	174	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	175	_mm256_cmpge_epu32_mask(__m256i __a, __m256i __b) {
				176	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 5,
				177	(__mmask8)-1);
				178	}
				179
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	180	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	181	_mm256_mask_cmpge_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				182	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 5,
				183	__u);
				184	}
				185
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	186	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	187	_mm_cmpge_epi64_mask(__m128i __a, __m128i __b) {
				188	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 5,
				189	(__mmask8)-1);
				190	}
				191
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	192	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	193	_mm_mask_cmpge_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				194	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 5,
				195	__u);
				196	}
				197
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	198	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	199	_mm_cmpge_epu64_mask(__m128i __a, __m128i __b) {
				200	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 5,
				201	(__mmask8)-1);
				202	}
				203
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	204	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	205	_mm_mask_cmpge_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				206	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 5,
				207	__u);
				208	}
				209
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	210	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	211	_mm256_cmpge_epi64_mask(__m256i __a, __m256i __b) {
				212	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 5,
				213	(__mmask8)-1);
				214	}
				215
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	216	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	217	_mm256_mask_cmpge_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				218	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 5,
				219	__u);
				220	}
				221
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	222	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	223	_mm256_cmpge_epu64_mask(__m256i __a, __m256i __b) {
				224	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 5,
				225	(__mmask8)-1);
				226	}
				227
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	228	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	229	_mm256_mask_cmpge_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				230	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 5,
				231	__u);
				232	}
				233
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	234	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	235	_mm_cmpgt_epi32_mask(__m128i __a, __m128i __b) {
				236	return (__mmask8)__builtin_ia32_pcmpgtd128_mask((__v4si)__a, (__v4si)__b,
				237	(__mmask8)-1);
				238	}
				239
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	240	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	241	_mm_mask_cmpgt_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				242	return (__mmask8)__builtin_ia32_pcmpgtd128_mask((__v4si)__a, (__v4si)__b,
				243	__u);
				244	}
				245
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	246	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	247	_mm_cmpgt_epu32_mask(__m128i __a, __m128i __b) {
				248	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 6,
				249	(__mmask8)-1);
				250	}
				251
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	252	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	253	_mm_mask_cmpgt_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				254	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 6,
				255	__u);
				256	}
				257
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	258	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	259	_mm256_cmpgt_epi32_mask(__m256i __a, __m256i __b) {
				260	return (__mmask8)__builtin_ia32_pcmpgtd256_mask((__v8si)__a, (__v8si)__b,
				261	(__mmask8)-1);
				262	}
				263
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	264	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	265	_mm256_mask_cmpgt_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				266	return (__mmask8)__builtin_ia32_pcmpgtd256_mask((__v8si)__a, (__v8si)__b,
				267	__u);
				268	}
				269
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	270	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	271	_mm256_cmpgt_epu32_mask(__m256i __a, __m256i __b) {
				272	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 6,
				273	(__mmask8)-1);
				274	}
				275
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	276	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	277	_mm256_mask_cmpgt_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				278	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 6,
				279	__u);
				280	}
				281
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	282	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	283	_mm_cmpgt_epi64_mask(__m128i __a, __m128i __b) {
				284	return (__mmask8)__builtin_ia32_pcmpgtq128_mask((__v2di)__a, (__v2di)__b,
				285	(__mmask8)-1);
				286	}
				287
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	288	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	289	_mm_mask_cmpgt_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				290	return (__mmask8)__builtin_ia32_pcmpgtq128_mask((__v2di)__a, (__v2di)__b,
				291	__u);
				292	}
				293
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	294	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	295	_mm_cmpgt_epu64_mask(__m128i __a, __m128i __b) {
				296	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 6,
				297	(__mmask8)-1);
				298	}
				299
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	300	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	301	_mm_mask_cmpgt_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				302	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 6,
				303	__u);
				304	}
				305
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	306	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	307	_mm256_cmpgt_epi64_mask(__m256i __a, __m256i __b) {
				308	return (__mmask8)__builtin_ia32_pcmpgtq256_mask((__v4di)__a, (__v4di)__b,
				309	(__mmask8)-1);
				310	}
				311
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	312	static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	313	_mm256_mask_cmpgt_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				314	return (__mmask8)__builtin_ia32_pcmpgtq256_mask((__v4di)__a, (__v4di)__b,
				315	__u);
				316	}
				317
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	318	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	319	_mm256_cmpgt_epu64_mask(__m256i __a, __m256i __b) {
				320	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 6,
				321	(__mmask8)-1);
				322	}
				323
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	324	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	325	_mm256_mask_cmpgt_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				326	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 6,
				327	__u);
				328	}
				329
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	330	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	331	_mm_cmple_epi32_mask(__m128i __a, __m128i __b) {
				332	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 2,
				333	(__mmask8)-1);
				334	}
				335
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	336	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	337	_mm_mask_cmple_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				338	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 2,
				339	__u);
				340	}
				341
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	342	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	343	_mm_cmple_epu32_mask(__m128i __a, __m128i __b) {
				344	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 2,
				345	(__mmask8)-1);
				346	}
				347
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	348	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	349	_mm_mask_cmple_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				350	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 2,
				351	__u);
				352	}
				353
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	354	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	355	_mm256_cmple_epi32_mask(__m256i __a, __m256i __b) {
				356	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 2,
				357	(__mmask8)-1);
				358	}
				359
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	360	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	361	_mm256_mask_cmple_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				362	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 2,
				363	__u);
				364	}
				365
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	366	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	367	_mm256_cmple_epu32_mask(__m256i __a, __m256i __b) {
				368	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 2,
				369	(__mmask8)-1);
				370	}
				371
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	372	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	373	_mm256_mask_cmple_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				374	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 2,
				375	__u);
				376	}
				377
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	378	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	379	_mm_cmple_epi64_mask(__m128i __a, __m128i __b) {
				380	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 2,
				381	(__mmask8)-1);
				382	}
				383
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	384	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	385	_mm_mask_cmple_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				386	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 2,
				387	__u);
				388	}
				389
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	390	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	391	_mm_cmple_epu64_mask(__m128i __a, __m128i __b) {
				392	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 2,
				393	(__mmask8)-1);
				394	}
				395
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	396	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	397	_mm_mask_cmple_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				398	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 2,
				399	__u);
				400	}
				401
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	402	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	403	_mm256_cmple_epi64_mask(__m256i __a, __m256i __b) {
				404	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 2,
				405	(__mmask8)-1);
				406	}
				407
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	408	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	409	_mm256_mask_cmple_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				410	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 2,
				411	__u);
				412	}
				413
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	414	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	415	_mm256_cmple_epu64_mask(__m256i __a, __m256i __b) {
				416	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 2,
				417	(__mmask8)-1);
				418	}
				419
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	420	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	421	_mm256_mask_cmple_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				422	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 2,
				423	__u);
				424	}
				425
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	426	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	427	_mm_cmplt_epi32_mask(__m128i __a, __m128i __b) {
				428	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 1,
				429	(__mmask8)-1);
				430	}
				431
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	432	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	433	_mm_mask_cmplt_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				434	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 1,
				435	__u);
				436	}
				437
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	438	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	439	_mm_cmplt_epu32_mask(__m128i __a, __m128i __b) {
				440	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 1,
				441	(__mmask8)-1);
				442	}
				443
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	444	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	445	_mm_mask_cmplt_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				446	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 1,
				447	__u);
				448	}
				449
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	450	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	451	_mm256_cmplt_epi32_mask(__m256i __a, __m256i __b) {
				452	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 1,
				453	(__mmask8)-1);
				454	}
				455
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	456	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	457	_mm256_mask_cmplt_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				458	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 1,
				459	__u);
				460	}
				461
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	462	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	463	_mm256_cmplt_epu32_mask(__m256i __a, __m256i __b) {
				464	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 1,
				465	(__mmask8)-1);
				466	}
				467
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	468	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	469	_mm256_mask_cmplt_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				470	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 1,
				471	__u);
				472	}
				473
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	474	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	475	_mm_cmplt_epi64_mask(__m128i __a, __m128i __b) {
				476	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 1,
				477	(__mmask8)-1);
				478	}
				479
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	480	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	481	_mm_mask_cmplt_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				482	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 1,
				483	__u);
				484	}
				485
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	486	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	487	_mm_cmplt_epu64_mask(__m128i __a, __m128i __b) {
				488	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 1,
				489	(__mmask8)-1);
				490	}
				491
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	492	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	493	_mm_mask_cmplt_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				494	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 1,
				495	__u);
				496	}
				497
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	498	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	499	_mm256_cmplt_epi64_mask(__m256i __a, __m256i __b) {
				500	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 1,
				501	(__mmask8)-1);
				502	}
				503
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	504	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	505	_mm256_mask_cmplt_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				506	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 1,
				507	__u);
				508	}
				509
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	510	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	511	_mm256_cmplt_epu64_mask(__m256i __a, __m256i __b) {
				512	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 1,
				513	(__mmask8)-1);
				514	}
				515
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	516	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	517	_mm256_mask_cmplt_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				518	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 1,
				519	__u);
				520	}
				521
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	522	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	523	_mm_cmpneq_epi32_mask(__m128i __a, __m128i __b) {
				524	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 4,
				525	(__mmask8)-1);
				526	}
				527
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	528	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	529	_mm_mask_cmpneq_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				530	return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 4,
				531	__u);
				532	}
				533
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	534	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	535	_mm_cmpneq_epu32_mask(__m128i __a, __m128i __b) {
				536	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 4,
				537	(__mmask8)-1);
				538	}
				539
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	540	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	541	_mm_mask_cmpneq_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				542	return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 4,
				543	__u);
				544	}
				545
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	546	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	547	_mm256_cmpneq_epi32_mask(__m256i __a, __m256i __b) {
				548	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 4,
				549	(__mmask8)-1);
				550	}
				551
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	552	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	553	_mm256_mask_cmpneq_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				554	return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 4,
				555	__u);
				556	}
				557
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	558	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	559	_mm256_cmpneq_epu32_mask(__m256i __a, __m256i __b) {
				560	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 4,
				561	(__mmask8)-1);
				562	}
				563
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	564	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	565	_mm256_mask_cmpneq_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				566	return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 4,
				567	__u);
				568	}
				569
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	570	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	571	_mm_cmpneq_epi64_mask(__m128i __a, __m128i __b) {
				572	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 4,
				573	(__mmask8)-1);
				574	}
				575
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	576	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	577	_mm_mask_cmpneq_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				578	return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 4,
				579	__u);
				580	}
				581
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	582	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	583	_mm_cmpneq_epu64_mask(__m128i __a, __m128i __b) {
				584	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 4,
				585	(__mmask8)-1);
				586	}
				587
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	588	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	589	_mm_mask_cmpneq_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
				590	return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 4,
				591	__u);
				592	}
				593
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	594	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	595	_mm256_cmpneq_epi64_mask(__m256i __a, __m256i __b) {
				596	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 4,
				597	(__mmask8)-1);
				598	}
				599
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	600	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	601	_mm256_mask_cmpneq_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				602	return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 4,
				603	__u);
				604	}
				605
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	606	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	607	_mm256_cmpneq_epu64_mask(__m256i __a, __m256i __b) {
				608	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 4,
				609	(__mmask8)-1);
				610	}
				611
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	612	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	613	_mm256_mask_cmpneq_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
				614	return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 4,
				615	__u);
				616	}
				617
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	618	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	619	_mm256_mask_add_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				620	__m256i __B)
				621	{
				622	return (__m256i) __builtin_ia32_paddd256_mask ((__v8si) __A,
				623	(__v8si) __B,
				624	(__v8si) __W,
				625	(__mmask8) __U);
				626	}
				627
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	628	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	629	_mm256_maskz_add_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				630	{
				631	return (__m256i) __builtin_ia32_paddd256_mask ((__v8si) __A,
				632	(__v8si) __B,
				633	(__v8si)
				634	_mm256_setzero_si256 (),
				635	(__mmask8) __U);
				636	}
				637
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	638	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	639	_mm256_mask_add_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				640	__m256i __B)
				641	{
				642	return (__m256i) __builtin_ia32_paddq256_mask ((__v4di) __A,
				643	(__v4di) __B,
				644	(__v4di) __W,
				645	(__mmask8) __U);
				646	}
				647
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	648	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	649	_mm256_maskz_add_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				650	{
				651	return (__m256i) __builtin_ia32_paddq256_mask ((__v4di) __A,
				652	(__v4di) __B,
				653	(__v4di)
				654	_mm256_setzero_si256 (),
				655	(__mmask8) __U);
				656	}
				657
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	658	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	659	_mm256_mask_sub_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				660	__m256i __B)
				661	{
				662	return (__m256i) __builtin_ia32_psubd256_mask ((__v8si) __A,
				663	(__v8si) __B,
				664	(__v8si) __W,
				665	(__mmask8) __U);
				666	}
				667
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	668	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	669	_mm256_maskz_sub_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				670	{
				671	return (__m256i) __builtin_ia32_psubd256_mask ((__v8si) __A,
				672	(__v8si) __B,
				673	(__v8si)
				674	_mm256_setzero_si256 (),
				675	(__mmask8) __U);
				676	}
				677
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	678	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	679	_mm256_mask_sub_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				680	__m256i __B)
				681	{
				682	return (__m256i) __builtin_ia32_psubq256_mask ((__v4di) __A,
				683	(__v4di) __B,
				684	(__v4di) __W,
				685	(__mmask8) __U);
				686	}
				687
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	688	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	689	_mm256_maskz_sub_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				690	{
				691	return (__m256i) __builtin_ia32_psubq256_mask ((__v4di) __A,
				692	(__v4di) __B,
				693	(__v4di)
				694	_mm256_setzero_si256 (),
				695	(__mmask8) __U);
				696	}
				697
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	698	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	699	_mm_mask_add_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				700	__m128i __B)
				701	{
				702	return (__m128i) __builtin_ia32_paddd128_mask ((__v4si) __A,
				703	(__v4si) __B,
				704	(__v4si) __W,
				705	(__mmask8) __U);
				706	}
				707
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	708	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	709	_mm_maskz_add_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				710	{
				711	return (__m128i) __builtin_ia32_paddd128_mask ((__v4si) __A,
				712	(__v4si) __B,
				713	(__v4si)
				714	_mm_setzero_si128 (),
				715	(__mmask8) __U);
				716	}
				717
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	718	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	719	_mm_mask_add_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				720	__m128i __B)
				721	{
				722	return (__m128i) __builtin_ia32_paddq128_mask ((__v2di) __A,
				723	(__v2di) __B,
				724	(__v2di) __W,
				725	(__mmask8) __U);
				726	}
				727
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	728	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	729	_mm_maskz_add_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				730	{
				731	return (__m128i) __builtin_ia32_paddq128_mask ((__v2di) __A,
				732	(__v2di) __B,
				733	(__v2di)
				734	_mm_setzero_si128 (),
				735	(__mmask8) __U);
				736	}
				737
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	738	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	739	_mm_mask_sub_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				740	__m128i __B)
				741	{
				742	return (__m128i) __builtin_ia32_psubd128_mask ((__v4si) __A,
				743	(__v4si) __B,
				744	(__v4si) __W,
				745	(__mmask8) __U);
				746	}
				747
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	748	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	749	_mm_maskz_sub_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				750	{
				751	return (__m128i) __builtin_ia32_psubd128_mask ((__v4si) __A,
				752	(__v4si) __B,
				753	(__v4si)
				754	_mm_setzero_si128 (),
				755	(__mmask8) __U);
				756	}
				757
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	758	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	759	_mm_mask_sub_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				760	__m128i __B)
				761	{
				762	return (__m128i) __builtin_ia32_psubq128_mask ((__v2di) __A,
				763	(__v2di) __B,
				764	(__v2di) __W,
				765	(__mmask8) __U);
				766	}
				767
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	768	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	769	_mm_maskz_sub_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				770	{
				771	return (__m128i) __builtin_ia32_psubq128_mask ((__v2di) __A,
				772	(__v2di) __B,
				773	(__v2di)
				774	_mm_setzero_si128 (),
				775	(__mmask8) __U);
				776	}
				777
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	778	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	779	_mm256_mask_mul_epi32 (__m256i __W, __mmask8 __M, __m256i __X,
				780	__m256i __Y)
				781	{
				782	return (__m256i) __builtin_ia32_pmuldq256_mask ((__v8si) __X,
				783	(__v8si) __Y,
				784	(__v4di) __W, __M);
				785	}
				786
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	787	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	788	_mm256_maskz_mul_epi32 (__mmask8 __M, __m256i __X, __m256i __Y)
				789	{
				790	return (__m256i) __builtin_ia32_pmuldq256_mask ((__v8si) __X,
				791	(__v8si) __Y,
				792	(__v4di)
				793	_mm256_setzero_si256 (),
				794	__M);
				795	}
				796
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	797	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	798	_mm_mask_mul_epi32 (__m128i __W, __mmask8 __M, __m128i __X,
				799	__m128i __Y)
				800	{
				801	return (__m128i) __builtin_ia32_pmuldq128_mask ((__v4si) __X,
				802	(__v4si) __Y,
				803	(__v2di) __W, __M);
				804	}
				805
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	806	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	807	_mm_maskz_mul_epi32 (__mmask8 __M, __m128i __X, __m128i __Y)
				808	{
				809	return (__m128i) __builtin_ia32_pmuldq128_mask ((__v4si) __X,
				810	(__v4si) __Y,
				811	(__v2di)
				812	_mm_setzero_si128 (),
				813	__M);
				814	}
				815
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	816	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	817	_mm256_mask_mul_epu32 (__m256i __W, __mmask8 __M, __m256i __X,
				818	__m256i __Y)
				819	{
				820	return (__m256i) __builtin_ia32_pmuludq256_mask ((__v8si) __X,
				821	(__v8si) __Y,
				822	(__v4di) __W, __M);
				823	}
				824
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	825	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	826	_mm256_maskz_mul_epu32 (__mmask8 __M, __m256i __X, __m256i __Y)
				827	{
				828	return (__m256i) __builtin_ia32_pmuludq256_mask ((__v8si) __X,
				829	(__v8si) __Y,
				830	(__v4di)
				831	_mm256_setzero_si256 (),
				832	__M);
				833	}
				834
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	835	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	836	_mm_mask_mul_epu32 (__m128i __W, __mmask8 __M, __m128i __X,
				837	__m128i __Y)
				838	{
				839	return (__m128i) __builtin_ia32_pmuludq128_mask ((__v4si) __X,
				840	(__v4si) __Y,
				841	(__v2di) __W, __M);
				842	}
				843
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	844	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	845	_mm_maskz_mul_epu32 (__mmask8 __M, __m128i __X, __m128i __Y)
				846	{
				847	return (__m128i) __builtin_ia32_pmuludq128_mask ((__v4si) __X,
				848	(__v4si) __Y,
				849	(__v2di)
				850	_mm_setzero_si128 (),
				851	__M);
				852	}
				853
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	854	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	855	_mm256_maskz_mullo_epi32 (__mmask8 __M, __m256i __A, __m256i __B)
				856	{
				857	return (__m256i) __builtin_ia32_pmulld256_mask ((__v8si) __A,
				858	(__v8si) __B,
				859	(__v8si)
				860	_mm256_setzero_si256 (),
				861	__M);
				862	}
				863
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	864	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	865	_mm256_mask_mullo_epi32 (__m256i __W, __mmask8 __M, __m256i __A,
				866	__m256i __B)
				867	{
				868	return (__m256i) __builtin_ia32_pmulld256_mask ((__v8si) __A,
				869	(__v8si) __B,
				870	(__v8si) __W, __M);
				871	}
				872
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	873	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	874	_mm_maskz_mullo_epi32 (__mmask8 __M, __m128i __A, __m128i __B)
				875	{
				876	return (__m128i) __builtin_ia32_pmulld128_mask ((__v4si) __A,
				877	(__v4si) __B,
				878	(__v4si)
				879	_mm_setzero_si128 (),
				880	__M);
				881	}
				882
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	883	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	884	_mm_mask_mullo_epi32 (__m128i __W, __mmask16 __M, __m128i __A,
				885	__m128i __B)
				886	{
				887	return (__m128i) __builtin_ia32_pmulld128_mask ((__v4si) __A,
				888	(__v4si) __B,
				889	(__v4si) __W, __M);
				890	}
				891
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	892	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	893	_mm256_mask_and_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				894	__m256i __B)
				895	{
				896	return (__m256i) __builtin_ia32_pandd256_mask ((__v8si) __A,
				897	(__v8si) __B,
				898	(__v8si) __W,
				899	(__mmask8) __U);
				900	}
				901
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	902	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	903	_mm256_maskz_and_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				904	{
				905	return (__m256i) __builtin_ia32_pandd256_mask ((__v8si) __A,
				906	(__v8si) __B,
				907	(__v8si)
				908	_mm256_setzero_si256 (),
				909	(__mmask8) __U);
				910	}
				911
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	912	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	913	_mm_mask_and_epi32 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)
				914	{
				915	return (__m128i) __builtin_ia32_pandd128_mask ((__v4si) __A,
				916	(__v4si) __B,
				917	(__v4si) __W,
				918	(__mmask8) __U);
				919	}
				920
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	921	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	922	_mm_maskz_and_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				923	{
				924	return (__m128i) __builtin_ia32_pandd128_mask ((__v4si) __A,
				925	(__v4si) __B,
				926	(__v4si)
				927	_mm_setzero_si128 (),
				928	(__mmask8) __U);
				929	}
				930
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	931	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	932	_mm256_mask_andnot_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				933	__m256i __B)
				934	{
				935	return (__m256i) __builtin_ia32_pandnd256_mask ((__v8si) __A,
				936	(__v8si) __B,
				937	(__v8si) __W,
				938	(__mmask8) __U);
				939	}
				940
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	941	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	942	_mm256_maskz_andnot_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				943	{
				944	return (__m256i) __builtin_ia32_pandnd256_mask ((__v8si) __A,
				945	(__v8si) __B,
				946	(__v8si)
				947	_mm256_setzero_si256 (),
				948	(__mmask8) __U);
				949	}
				950
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	951	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	952	_mm_mask_andnot_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				953	__m128i __B)
				954	{
				955	return (__m128i) __builtin_ia32_pandnd128_mask ((__v4si) __A,
				956	(__v4si) __B,
				957	(__v4si) __W,
				958	(__mmask8) __U);
				959	}
				960
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	961	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	962	_mm_maskz_andnot_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				963	{
				964	return (__m128i) __builtin_ia32_pandnd128_mask ((__v4si) __A,
				965	(__v4si) __B,
				966	(__v4si)
				967	_mm_setzero_si128 (),
				968	(__mmask8) __U);
				969	}
				970
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	971	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	972	_mm256_mask_or_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				973	__m256i __B)
				974	{
				975	return (__m256i) __builtin_ia32_pord256_mask ((__v8si) __A,
				976	(__v8si) __B,
				977	(__v8si) __W,
				978	(__mmask8) __U);
				979	}
				980
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	981	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	982	_mm256_maskz_or_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				983	{
				984	return (__m256i) __builtin_ia32_pord256_mask ((__v8si) __A,
				985	(__v8si) __B,
				986	(__v8si)
				987	_mm256_setzero_si256 (),
				988	(__mmask8) __U);
				989	}
				990
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	991	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	992	_mm_mask_or_epi32 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)
				993	{
				994	return (__m128i) __builtin_ia32_pord128_mask ((__v4si) __A,
				995	(__v4si) __B,
				996	(__v4si) __W,
				997	(__mmask8) __U);
				998	}
				999
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1000	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1001	_mm_maskz_or_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				1002	{
				1003	return (__m128i) __builtin_ia32_pord128_mask ((__v4si) __A,
				1004	(__v4si) __B,
				1005	(__v4si)
				1006	_mm_setzero_si128 (),
				1007	(__mmask8) __U);
				1008	}
				1009
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1010	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1011	_mm256_mask_xor_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				1012	__m256i __B)
				1013	{
				1014	return (__m256i) __builtin_ia32_pxord256_mask ((__v8si) __A,
				1015	(__v8si) __B,
				1016	(__v8si) __W,
				1017	(__mmask8) __U);
				1018	}
				1019
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1020	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1021	_mm256_maskz_xor_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				1022	{
				1023	return (__m256i) __builtin_ia32_pxord256_mask ((__v8si) __A,
				1024	(__v8si) __B,
				1025	(__v8si)
				1026	_mm256_setzero_si256 (),
				1027	(__mmask8) __U);
				1028	}
				1029
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1030	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1031	_mm_mask_xor_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				1032	__m128i __B)
				1033	{
				1034	return (__m128i) __builtin_ia32_pxord128_mask ((__v4si) __A,
				1035	(__v4si) __B,
				1036	(__v4si) __W,
				1037	(__mmask8) __U);
				1038	}
				1039
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1040	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1041	_mm_maskz_xor_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				1042	{
				1043	return (__m128i) __builtin_ia32_pxord128_mask ((__v4si) __A,
				1044	(__v4si) __B,
				1045	(__v4si)
				1046	_mm_setzero_si128 (),
				1047	(__mmask8) __U);
				1048	}
				1049
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1050	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1051	_mm256_mask_and_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				1052	__m256i __B)
				1053	{
				1054	return (__m256i) __builtin_ia32_pandq256_mask ((__v4di) __A,
				1055	(__v4di) __B,
				1056	(__v4di) __W, __U);
				1057	}
				1058
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1059	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1060	_mm256_maskz_and_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				1061	{
				1062	return (__m256i) __builtin_ia32_pandq256_mask ((__v4di) __A,
				1063	(__v4di) __B,
				1064	(__v4di)
				1065	_mm256_setzero_pd (),
				1066	__U);
				1067	}
				1068
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1069	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1070	_mm_mask_and_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				1071	__m128i __B)
				1072	{
				1073	return (__m128i) __builtin_ia32_pandq128_mask ((__v2di) __A,
				1074	(__v2di) __B,
				1075	(__v2di) __W, __U);
				1076	}
				1077
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1078	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1079	_mm_maskz_and_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				1080	{
				1081	return (__m128i) __builtin_ia32_pandq128_mask ((__v2di) __A,
				1082	(__v2di) __B,
				1083	(__v2di)
				1084	_mm_setzero_pd (),
				1085	__U);
				1086	}
				1087
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1088	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1089	_mm256_mask_andnot_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				1090	__m256i __B)
				1091	{
				1092	return (__m256i) __builtin_ia32_pandnq256_mask ((__v4di) __A,
				1093	(__v4di) __B,
				1094	(__v4di) __W, __U);
				1095	}
				1096
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1097	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1098	_mm256_maskz_andnot_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				1099	{
				1100	return (__m256i) __builtin_ia32_pandnq256_mask ((__v4di) __A,
				1101	(__v4di) __B,
				1102	(__v4di)
				1103	_mm256_setzero_pd (),
				1104	__U);
				1105	}
				1106
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1107	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1108	_mm_mask_andnot_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				1109	__m128i __B)
				1110	{
				1111	return (__m128i) __builtin_ia32_pandnq128_mask ((__v2di) __A,
				1112	(__v2di) __B,
				1113	(__v2di) __W, __U);
				1114	}
				1115
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1116	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1117	_mm_maskz_andnot_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				1118	{
				1119	return (__m128i) __builtin_ia32_pandnq128_mask ((__v2di) __A,
				1120	(__v2di) __B,
				1121	(__v2di)
				1122	_mm_setzero_pd (),
				1123	__U);
				1124	}
				1125
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1126	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1127	_mm256_mask_or_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				1128	__m256i __B)
				1129	{
				1130	return (__m256i) __builtin_ia32_porq256_mask ((__v4di) __A,
				1131	(__v4di) __B,
				1132	(__v4di) __W,
				1133	(__mmask8) __U);
				1134	}
				1135
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1136	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1137	_mm256_maskz_or_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				1138	{
				1139	return (__m256i) __builtin_ia32_porq256_mask ((__v4di) __A,
				1140	(__v4di) __B,
				1141	(__v4di)
				1142	_mm256_setzero_si256 (),
				1143	(__mmask8) __U);
				1144	}
				1145
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1146	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1147	_mm_mask_or_epi64 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)
				1148	{
				1149	return (__m128i) __builtin_ia32_porq128_mask ((__v2di) __A,
				1150	(__v2di) __B,
				1151	(__v2di) __W,
				1152	(__mmask8) __U);
				1153	}
				1154
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1155	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1156	_mm_maskz_or_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				1157	{
				1158	return (__m128i) __builtin_ia32_porq128_mask ((__v2di) __A,
				1159	(__v2di) __B,
				1160	(__v2di)
				1161	_mm_setzero_si128 (),
				1162	(__mmask8) __U);
				1163	}
				1164
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1165	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1166	_mm256_mask_xor_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				1167	__m256i __B)
				1168	{
				1169	return (__m256i) __builtin_ia32_pxorq256_mask ((__v4di) __A,
				1170	(__v4di) __B,
				1171	(__v4di) __W,
				1172	(__mmask8) __U);
				1173	}
				1174
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1175	static __inline__ __m256i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1176	_mm256_maskz_xor_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				1177	{
				1178	return (__m256i) __builtin_ia32_pxorq256_mask ((__v4di) __A,
				1179	(__v4di) __B,
				1180	(__v4di)
				1181	_mm256_setzero_si256 (),
				1182	(__mmask8) __U);
				1183	}
				1184
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1185	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1186	_mm_mask_xor_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				1187	__m128i __B)
				1188	{
				1189	return (__m128i) __builtin_ia32_pxorq128_mask ((__v2di) __A,
				1190	(__v2di) __B,
				1191	(__v2di) __W,
				1192	(__mmask8) __U);
				1193	}
				1194
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1195	static __inline__ __m128i __DEFAULT_FN_ATTRS
Elena Demikhovsky	35dc8c0	2015-04-28 13:28:01 +0000	[diff] [blame]	1196	_mm_maskz_xor_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				1197	{
				1198	return (__m128i) __builtin_ia32_pxorq128_mask ((__v2di) __A,
				1199	(__v2di) __B,
				1200	(__v2di)
				1201	_mm_setzero_si128 (),
				1202	(__mmask8) __U);
				1203	}
				1204
Craig Topper	2f25a5a	2015-01-26 08:11:49 +0000	[diff] [blame]	1205	#define _mm_cmp_epi32_mask(a, b, p) __extension__ ({ \
				1206	(__mmask8)__builtin_ia32_cmpd128_mask((__v4si)(__m128i)(a), \
				1207	(__v4si)(__m128i)(b), \
				1208	(p), (__mmask8)-1); })
				1209
				1210	#define _mm_mask_cmp_epi32_mask(m, a, b, p) __extension__ ({ \
				1211	(__mmask8)__builtin_ia32_cmpd128_mask((__v4si)(__m128i)(a), \
				1212	(__v4si)(__m128i)(b), \
				1213	(p), (__mmask8)(m)); })
				1214
				1215	#define _mm_cmp_epu32_mask(a, b, p) __extension__ ({ \
				1216	(__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)(__m128i)(a), \
				1217	(__v4si)(__m128i)(b), \
				1218	(p), (__mmask8)-1); })
				1219
				1220	#define _mm_mask_cmp_epu32_mask(m, a, b, p) __extension__ ({ \
				1221	(__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)(__m128i)(a), \
				1222	(__v4si)(__m128i)(b), \
				1223	(p), (__mmask8)(m)); })
				1224
				1225	#define _mm256_cmp_epi32_mask(a, b, p) __extension__ ({ \
				1226	(__mmask8)__builtin_ia32_cmpd256_mask((__v8si)(__m256i)(a), \
				1227	(__v8si)(__m256i)(b), \
				1228	(p), (__mmask8)-1); })
				1229
				1230	#define _mm256_mask_cmp_epi32_mask(m, a, b, p) __extension__ ({ \
				1231	(__mmask8)__builtin_ia32_cmpd256_mask((__v8si)(__m256i)(a), \
				1232	(__v8si)(__m256i)(b), \
				1233	(p), (__mmask8)(m)); })
				1234
				1235	#define _mm256_cmp_epu32_mask(a, b, p) __extension__ ({ \
				1236	(__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)(__m256i)(a), \
				1237	(__v8si)(__m256i)(b), \
				1238	(p), (__mmask8)-1); })
				1239
				1240	#define _mm256_mask_cmp_epu32_mask(m, a, b, p) __extension__ ({ \
				1241	(__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)(__m256i)(a), \
				1242	(__v8si)(__m256i)(b), \
				1243	(p), (__mmask8)(m)); })
				1244
				1245	#define _mm_cmp_epi64_mask(a, b, p) __extension__ ({ \
				1246	(__mmask8)__builtin_ia32_cmpq128_mask((__v2di)(__m128i)(a), \
				1247	(__v2di)(__m128i)(b), \
				1248	(p), (__mmask8)-1); })
				1249
				1250	#define _mm_mask_cmp_epi64_mask(m, a, b, p) __extension__ ({ \
				1251	(__mmask8)__builtin_ia32_cmpq128_mask((__v2di)(__m128i)(a), \
				1252	(__v2di)(__m128i)(b), \
				1253	(p), (__mmask8)(m)); })
				1254
				1255	#define _mm_cmp_epu64_mask(a, b, p) __extension__ ({ \
				1256	(__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)(__m128i)(a), \
				1257	(__v2di)(__m128i)(b), \
				1258	(p), (__mmask8)-1); })
				1259
				1260	#define _mm_mask_cmp_epu64_mask(m, a, b, p) __extension__ ({ \
				1261	(__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)(__m128i)(a), \
				1262	(__v2di)(__m128i)(b), \
				1263	(p), (__mmask8)(m)); })
				1264
				1265	#define _mm256_cmp_epi64_mask(a, b, p) __extension__ ({ \
				1266	(__mmask8)__builtin_ia32_cmpq256_mask((__v4di)(__m256i)(a), \
				1267	(__v4di)(__m256i)(b), \
				1268	(p), (__mmask8)-1); })
				1269
				1270	#define _mm256_mask_cmp_epi64_mask(m, a, b, p) __extension__ ({ \
				1271	(__mmask8)__builtin_ia32_cmpq256_mask((__v4di)(__m256i)(a), \
				1272	(__v4di)(__m256i)(b), \
				1273	(p), (__mmask8)(m)); })
				1274
				1275	#define _mm256_cmp_epu64_mask(a, b, p) __extension__ ({ \
				1276	(__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)(__m256i)(a), \
				1277	(__v4di)(__m256i)(b), \
				1278	(p), (__mmask8)-1); })
				1279
				1280	#define _mm256_mask_cmp_epu64_mask(m, a, b, p) __extension__ ({ \
				1281	(__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)(__m256i)(a), \
				1282	(__v4di)(__m256i)(b), \
				1283	(p), (__mmask8)(m)); })
				1284
Elena Demikhovsky	bd5c8b9	2015-05-07 11:26:36 +0000	[diff] [blame]	1285	#define _mm256_cmp_ps_mask(a, b, p) __extension__ ({ \
				1286	(__mmask8)__builtin_ia32_cmpps256_mask((__v8sf)(__m256)(a), \
				1287	(__v8sf)(__m256)(b), \
				1288	(p), (__mmask8)-1); })
				1289
				1290	#define _mm256_mask_cmp_ps_mask(m, a, b, p) __extension__ ({ \
				1291	(__mmask8)__builtin_ia32_cmpps256_mask((__v8sf)(__m256)(a), \
				1292	(__v8sf)(__m256)(b), \
				1293	(p), (__mmask8)(m)); })
				1294
				1295	#define _mm256_cmp_pd_mask(a, b, p) __extension__ ({ \
				1296	(__mmask8)__builtin_ia32_cmppd256_mask((__v4df)(__m256)(a), \
				1297	(__v4df)(__m256)(b), \
				1298	(p), (__mmask8)-1); })
				1299
				1300	#define _mm256_mask_cmp_pd_mask(m, a, b, p) __extension__ ({ \
				1301	(__mmask8)__builtin_ia32_cmppd256_mask((__v4df)(__m256)(a), \
				1302	(__v4df)(__m256)(b), \
				1303	(p), (__mmask8)(m)); })
				1304
				1305	#define _mm128_cmp_ps_mask(a, b, p) __extension__ ({ \
				1306	(__mmask8)__builtin_ia32_cmpps128_mask((__v4sf)(__m128)(a), \
				1307	(__v4sf)(__m128)(b), \
				1308	(p), (__mmask8)-1); })
				1309
				1310	#define _mm128_mask_cmp_ps_mask(m, a, b, p) __extension__ ({ \
				1311	(__mmask8)__builtin_ia32_cmpps128_mask((__v4sf)(__m128)(a), \
				1312	(__v4sf)(__m128)(b), \
				1313	(p), (__mmask8)(m)); })
				1314
				1315	#define _mm128_cmp_pd_mask(a, b, p) __extension__ ({ \
				1316	(__mmask8)__builtin_ia32_cmppd128_mask((__v2df)(__m128)(a), \
				1317	(__v2df)(__m128)(b), \
				1318	(p), (__mmask8)-1); })
				1319
				1320	#define _mm128_mask_cmp_pd_mask(m, a, b, p) __extension__ ({ \
				1321	(__mmask8)__builtin_ia32_cmppd128_mask((__v2df)(__m128)(a), \
				1322	(__v2df)(__m128)(b), \
				1323	(p), (__mmask8)(m)); })
Eric Christopher	4d185168	2015-06-17 07:09:20 +0000	[diff] [blame]	1324
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1325	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1326	_mm_mask_fmadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1327	{
				1328	return (__m128d) __builtin_ia32_vfmaddpd128_mask ((__v2df) __A,
				1329	(__v2df) __B,
				1330	(__v2df) __C,
				1331	(__mmask8) __U);
				1332	}
				1333
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1334	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1335	_mm_mask3_fmadd_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1336	{
				1337	return (__m128d) __builtin_ia32_vfmaddpd128_mask3 ((__v2df) __A,
				1338	(__v2df) __B,
				1339	(__v2df) __C,
				1340	(__mmask8) __U);
				1341	}
				1342
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1343	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1344	_mm_maskz_fmadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1345	{
				1346	return (__m128d) __builtin_ia32_vfmaddpd128_maskz ((__v2df) __A,
				1347	(__v2df) __B,
				1348	(__v2df) __C,
				1349	(__mmask8) __U);
				1350	}
				1351
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1352	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1353	_mm_mask_fmsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1354	{
				1355	return (__m128d) __builtin_ia32_vfmaddpd128_mask ((__v2df) __A,
				1356	(__v2df) __B,
				1357	-(__v2df) __C,
				1358	(__mmask8) __U);
				1359	}
				1360
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1361	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1362	_mm_maskz_fmsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1363	{
				1364	return (__m128d) __builtin_ia32_vfmaddpd128_maskz ((__v2df) __A,
				1365	(__v2df) __B,
				1366	-(__v2df) __C,
				1367	(__mmask8) __U);
				1368	}
				1369
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1370	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1371	_mm_mask3_fnmadd_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1372	{
				1373	return (__m128d) __builtin_ia32_vfmaddpd128_mask3 (-(__v2df) __A,
				1374	(__v2df) __B,
				1375	(__v2df) __C,
				1376	(__mmask8) __U);
				1377	}
				1378
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1379	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1380	_mm_maskz_fnmadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1381	{
				1382	return (__m128d) __builtin_ia32_vfmaddpd128_maskz (-(__v2df) __A,
				1383	(__v2df) __B,
				1384	(__v2df) __C,
				1385	(__mmask8) __U);
				1386	}
				1387
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1388	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1389	_mm_maskz_fnmsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1390	{
				1391	return (__m128d) __builtin_ia32_vfmaddpd128_maskz (-(__v2df) __A,
				1392	(__v2df) __B,
				1393	-(__v2df) __C,
				1394	(__mmask8) __U);
				1395	}
				1396
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1397	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1398	_mm256_mask_fmadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1399	{
				1400	return (__m256d) __builtin_ia32_vfmaddpd256_mask ((__v4df) __A,
				1401	(__v4df) __B,
				1402	(__v4df) __C,
				1403	(__mmask8) __U);
				1404	}
				1405
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1406	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1407	_mm256_mask3_fmadd_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1408	{
				1409	return (__m256d) __builtin_ia32_vfmaddpd256_mask3 ((__v4df) __A,
				1410	(__v4df) __B,
				1411	(__v4df) __C,
				1412	(__mmask8) __U);
				1413	}
				1414
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1415	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1416	_mm256_maskz_fmadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1417	{
				1418	return (__m256d) __builtin_ia32_vfmaddpd256_maskz ((__v4df) __A,
				1419	(__v4df) __B,
				1420	(__v4df) __C,
				1421	(__mmask8) __U);
				1422	}
				1423
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1424	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1425	_mm256_mask_fmsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1426	{
				1427	return (__m256d) __builtin_ia32_vfmaddpd256_mask ((__v4df) __A,
				1428	(__v4df) __B,
				1429	-(__v4df) __C,
				1430	(__mmask8) __U);
				1431	}
				1432
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1433	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1434	_mm256_maskz_fmsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1435	{
				1436	return (__m256d) __builtin_ia32_vfmaddpd256_maskz ((__v4df) __A,
				1437	(__v4df) __B,
				1438	-(__v4df) __C,
				1439	(__mmask8) __U);
				1440	}
				1441
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1442	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1443	_mm256_mask3_fnmadd_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1444	{
				1445	return (__m256d) __builtin_ia32_vfmaddpd256_mask3 (-(__v4df) __A,
				1446	(__v4df) __B,
				1447	(__v4df) __C,
				1448	(__mmask8) __U);
				1449	}
				1450
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1451	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1452	_mm256_maskz_fnmadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1453	{
				1454	return (__m256d) __builtin_ia32_vfmaddpd256_maskz (-(__v4df) __A,
				1455	(__v4df) __B,
				1456	(__v4df) __C,
				1457	(__mmask8) __U);
				1458	}
				1459
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1460	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1461	_mm256_maskz_fnmsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1462	{
				1463	return (__m256d) __builtin_ia32_vfmaddpd256_maskz (-(__v4df) __A,
				1464	(__v4df) __B,
				1465	-(__v4df) __C,
				1466	(__mmask8) __U);
				1467	}
				1468
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1469	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1470	_mm_mask_fmadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1471	{
				1472	return (__m128) __builtin_ia32_vfmaddps128_mask ((__v4sf) __A,
				1473	(__v4sf) __B,
				1474	(__v4sf) __C,
				1475	(__mmask8) __U);
				1476	}
				1477
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1478	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1479	_mm_mask3_fmadd_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1480	{
				1481	return (__m128) __builtin_ia32_vfmaddps128_mask3 ((__v4sf) __A,
				1482	(__v4sf) __B,
				1483	(__v4sf) __C,
				1484	(__mmask8) __U);
				1485	}
				1486
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1487	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1488	_mm_maskz_fmadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1489	{
				1490	return (__m128) __builtin_ia32_vfmaddps128_maskz ((__v4sf) __A,
				1491	(__v4sf) __B,
				1492	(__v4sf) __C,
				1493	(__mmask8) __U);
				1494	}
				1495
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1496	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1497	_mm_mask_fmsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1498	{
				1499	return (__m128) __builtin_ia32_vfmaddps128_mask ((__v4sf) __A,
				1500	(__v4sf) __B,
				1501	-(__v4sf) __C,
				1502	(__mmask8) __U);
				1503	}
				1504
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1505	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1506	_mm_maskz_fmsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1507	{
				1508	return (__m128) __builtin_ia32_vfmaddps128_maskz ((__v4sf) __A,
				1509	(__v4sf) __B,
				1510	-(__v4sf) __C,
				1511	(__mmask8) __U);
				1512	}
				1513
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1514	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1515	_mm_mask3_fnmadd_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1516	{
				1517	return (__m128) __builtin_ia32_vfmaddps128_mask3 (-(__v4sf) __A,
				1518	(__v4sf) __B,
				1519	(__v4sf) __C,
				1520	(__mmask8) __U);
				1521	}
				1522
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1523	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1524	_mm_maskz_fnmadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1525	{
				1526	return (__m128) __builtin_ia32_vfmaddps128_maskz (-(__v4sf) __A,
				1527	(__v4sf) __B,
				1528	(__v4sf) __C,
				1529	(__mmask8) __U);
				1530	}
				1531
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1532	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1533	_mm_maskz_fnmsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1534	{
				1535	return (__m128) __builtin_ia32_vfmaddps128_maskz (-(__v4sf) __A,
				1536	(__v4sf) __B,
				1537	-(__v4sf) __C,
				1538	(__mmask8) __U);
				1539	}
				1540
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1541	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1542	_mm256_mask_fmadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C)
				1543	{
				1544	return (__m256) __builtin_ia32_vfmaddps256_mask ((__v8sf) __A,
				1545	(__v8sf) __B,
				1546	(__v8sf) __C,
				1547	(__mmask8) __U);
				1548	}
				1549
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1550	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1551	_mm256_mask3_fmadd_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1552	{
				1553	return (__m256) __builtin_ia32_vfmaddps256_mask3 ((__v8sf) __A,
				1554	(__v8sf) __B,
				1555	(__v8sf) __C,
				1556	(__mmask8) __U);
				1557	}
				1558
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1559	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1560	_mm256_maskz_fmadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1561	{
				1562	return (__m256) __builtin_ia32_vfmaddps256_maskz ((__v8sf) __A,
				1563	(__v8sf) __B,
				1564	(__v8sf) __C,
				1565	(__mmask8) __U);
				1566	}
				1567
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1568	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1569	_mm256_mask_fmsub_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C)
				1570	{
				1571	return (__m256) __builtin_ia32_vfmaddps256_mask ((__v8sf) __A,
				1572	(__v8sf) __B,
				1573	-(__v8sf) __C,
				1574	(__mmask8) __U);
				1575	}
				1576
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1577	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1578	_mm256_maskz_fmsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1579	{
				1580	return (__m256) __builtin_ia32_vfmaddps256_maskz ((__v8sf) __A,
				1581	(__v8sf) __B,
				1582	-(__v8sf) __C,
				1583	(__mmask8) __U);
				1584	}
				1585
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1586	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1587	_mm256_mask3_fnmadd_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1588	{
				1589	return (__m256) __builtin_ia32_vfmaddps256_mask3 (-(__v8sf) __A,
				1590	(__v8sf) __B,
				1591	(__v8sf) __C,
				1592	(__mmask8) __U);
				1593	}
				1594
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1595	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1596	_mm256_maskz_fnmadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1597	{
				1598	return (__m256) __builtin_ia32_vfmaddps256_maskz (-(__v8sf) __A,
				1599	(__v8sf) __B,
				1600	(__v8sf) __C,
				1601	(__mmask8) __U);
				1602	}
				1603
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1604	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1605	_mm256_maskz_fnmsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1606	{
				1607	return (__m256) __builtin_ia32_vfmaddps256_maskz (-(__v8sf) __A,
				1608	(__v8sf) __B,
				1609	-(__v8sf) __C,
				1610	(__mmask8) __U);
				1611	}
				1612
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1613	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1614	_mm_mask_fmaddsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1615	{
				1616	return (__m128d) __builtin_ia32_vfmaddsubpd128_mask ((__v2df) __A,
				1617	(__v2df) __B,
				1618	(__v2df) __C,
				1619	(__mmask8) __U);
				1620	}
				1621
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1622	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1623	_mm_mask3_fmaddsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1624	{
				1625	return (__m128d) __builtin_ia32_vfmaddsubpd128_mask3 ((__v2df) __A,
				1626	(__v2df) __B,
				1627	(__v2df) __C,
				1628	(__mmask8)
				1629	__U);
				1630	}
				1631
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1632	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1633	_mm_maskz_fmaddsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1634	{
				1635	return (__m128d) __builtin_ia32_vfmaddsubpd128_maskz ((__v2df) __A,
				1636	(__v2df) __B,
				1637	(__v2df) __C,
				1638	(__mmask8)
				1639	__U);
				1640	}
				1641
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1642	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1643	_mm_mask_fmsubadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1644	{
				1645	return (__m128d) __builtin_ia32_vfmaddsubpd128_mask ((__v2df) __A,
				1646	(__v2df) __B,
				1647	-(__v2df) __C,
				1648	(__mmask8) __U);
				1649	}
				1650
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1651	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1652	_mm_maskz_fmsubadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
				1653	{
				1654	return (__m128d) __builtin_ia32_vfmaddsubpd128_maskz ((__v2df) __A,
				1655	(__v2df) __B,
				1656	-(__v2df) __C,
				1657	(__mmask8)
				1658	__U);
				1659	}
				1660
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1661	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1662	_mm256_mask_fmaddsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1663	{
				1664	return (__m256d) __builtin_ia32_vfmaddsubpd256_mask ((__v4df) __A,
				1665	(__v4df) __B,
				1666	(__v4df) __C,
				1667	(__mmask8) __U);
				1668	}
				1669
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1670	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1671	_mm256_mask3_fmaddsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1672	{
				1673	return (__m256d) __builtin_ia32_vfmaddsubpd256_mask3 ((__v4df) __A,
				1674	(__v4df) __B,
				1675	(__v4df) __C,
				1676	(__mmask8)
				1677	__U);
				1678	}
				1679
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1680	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1681	_mm256_maskz_fmaddsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1682	{
				1683	return (__m256d) __builtin_ia32_vfmaddsubpd256_maskz ((__v4df) __A,
				1684	(__v4df) __B,
				1685	(__v4df) __C,
				1686	(__mmask8)
				1687	__U);
				1688	}
				1689
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1690	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1691	_mm256_mask_fmsubadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1692	{
				1693	return (__m256d) __builtin_ia32_vfmaddsubpd256_mask ((__v4df) __A,
				1694	(__v4df) __B,
				1695	-(__v4df) __C,
				1696	(__mmask8) __U);
				1697	}
				1698
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1699	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1700	_mm256_maskz_fmsubadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)
				1701	{
				1702	return (__m256d) __builtin_ia32_vfmaddsubpd256_maskz ((__v4df) __A,
				1703	(__v4df) __B,
				1704	-(__v4df) __C,
				1705	(__mmask8)
				1706	__U);
				1707	}
				1708
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1709	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1710	_mm_mask_fmaddsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1711	{
				1712	return (__m128) __builtin_ia32_vfmaddsubps128_mask ((__v4sf) __A,
				1713	(__v4sf) __B,
				1714	(__v4sf) __C,
				1715	(__mmask8) __U);
				1716	}
				1717
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1718	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1719	_mm_mask3_fmaddsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1720	{
				1721	return (__m128) __builtin_ia32_vfmaddsubps128_mask3 ((__v4sf) __A,
				1722	(__v4sf) __B,
				1723	(__v4sf) __C,
				1724	(__mmask8) __U);
				1725	}
				1726
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1727	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1728	_mm_maskz_fmaddsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1729	{
				1730	return (__m128) __builtin_ia32_vfmaddsubps128_maskz ((__v4sf) __A,
				1731	(__v4sf) __B,
				1732	(__v4sf) __C,
				1733	(__mmask8) __U);
				1734	}
				1735
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1736	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1737	_mm_mask_fmsubadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1738	{
				1739	return (__m128) __builtin_ia32_vfmaddsubps128_mask ((__v4sf) __A,
				1740	(__v4sf) __B,
				1741	-(__v4sf) __C,
				1742	(__mmask8) __U);
				1743	}
				1744
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1745	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1746	_mm_maskz_fmsubadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
				1747	{
				1748	return (__m128) __builtin_ia32_vfmaddsubps128_maskz ((__v4sf) __A,
				1749	(__v4sf) __B,
				1750	-(__v4sf) __C,
				1751	(__mmask8) __U);
				1752	}
				1753
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1754	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1755	_mm256_mask_fmaddsub_ps(__m256 __A, __mmask8 __U, __m256 __B,
				1756	__m256 __C)
				1757	{
				1758	return (__m256) __builtin_ia32_vfmaddsubps256_mask ((__v8sf) __A,
				1759	(__v8sf) __B,
				1760	(__v8sf) __C,
				1761	(__mmask8) __U);
				1762	}
				1763
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1764	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1765	_mm256_mask3_fmaddsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1766	{
				1767	return (__m256) __builtin_ia32_vfmaddsubps256_mask3 ((__v8sf) __A,
				1768	(__v8sf) __B,
				1769	(__v8sf) __C,
				1770	(__mmask8) __U);
				1771	}
				1772
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1773	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1774	_mm256_maskz_fmaddsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1775	{
				1776	return (__m256) __builtin_ia32_vfmaddsubps256_maskz ((__v8sf) __A,
				1777	(__v8sf) __B,
				1778	(__v8sf) __C,
				1779	(__mmask8) __U);
				1780	}
				1781
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1782	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1783	_mm256_mask_fmsubadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C)
				1784	{
				1785	return (__m256) __builtin_ia32_vfmaddsubps256_mask ((__v8sf) __A,
				1786	(__v8sf) __B,
				1787	-(__v8sf) __C,
				1788	(__mmask8) __U);
				1789	}
				1790
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1791	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1792	_mm256_maskz_fmsubadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)
				1793	{
				1794	return (__m256) __builtin_ia32_vfmaddsubps256_maskz ((__v8sf) __A,
				1795	(__v8sf) __B,
				1796	-(__v8sf) __C,
				1797	(__mmask8) __U);
				1798	}
				1799
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1800	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1801	_mm_mask3_fmsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1802	{
				1803	return (__m128d) __builtin_ia32_vfmsubpd128_mask3 ((__v2df) __A,
				1804	(__v2df) __B,
				1805	(__v2df) __C,
				1806	(__mmask8) __U);
				1807	}
				1808
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1809	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1810	_mm256_mask3_fmsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1811	{
				1812	return (__m256d) __builtin_ia32_vfmsubpd256_mask3 ((__v4df) __A,
				1813	(__v4df) __B,
				1814	(__v4df) __C,
				1815	(__mmask8) __U);
				1816	}
				1817
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1818	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1819	_mm_mask3_fmsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1820	{
				1821	return (__m128) __builtin_ia32_vfmsubps128_mask3 ((__v4sf) __A,
				1822	(__v4sf) __B,
				1823	(__v4sf) __C,
				1824	(__mmask8) __U);
				1825	}
				1826
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1827	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1828	_mm256_mask3_fmsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1829	{
				1830	return (__m256) __builtin_ia32_vfmsubps256_mask3 ((__v8sf) __A,
				1831	(__v8sf) __B,
				1832	(__v8sf) __C,
				1833	(__mmask8) __U);
				1834	}
				1835
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1836	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1837	_mm_mask3_fmsubadd_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1838	{
				1839	return (__m128d) __builtin_ia32_vfmsubaddpd128_mask3 ((__v2df) __A,
				1840	(__v2df) __B,
				1841	(__v2df) __C,
				1842	(__mmask8)
				1843	__U);
				1844	}
				1845
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1846	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1847	_mm256_mask3_fmsubadd_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1848	{
				1849	return (__m256d) __builtin_ia32_vfmsubaddpd256_mask3 ((__v4df) __A,
				1850	(__v4df) __B,
				1851	(__v4df) __C,
				1852	(__mmask8)
				1853	__U);
				1854	}
				1855
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1856	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1857	_mm_mask3_fmsubadd_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1858	{
				1859	return (__m128) __builtin_ia32_vfmsubaddps128_mask3 ((__v4sf) __A,
				1860	(__v4sf) __B,
				1861	(__v4sf) __C,
				1862	(__mmask8) __U);
				1863	}
				1864
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1865	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1866	_mm256_mask3_fmsubadd_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1867	{
				1868	return (__m256) __builtin_ia32_vfmsubaddps256_mask3 ((__v8sf) __A,
				1869	(__v8sf) __B,
				1870	(__v8sf) __C,
				1871	(__mmask8) __U);
				1872	}
				1873
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1874	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1875	_mm_mask_fnmadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1876	{
				1877	return (__m128d) __builtin_ia32_vfnmaddpd128_mask ((__v2df) __A,
				1878	(__v2df) __B,
				1879	(__v2df) __C,
				1880	(__mmask8) __U);
				1881	}
				1882
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1883	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1884	_mm256_mask_fnmadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1885	{
				1886	return (__m256d) __builtin_ia32_vfnmaddpd256_mask ((__v4df) __A,
				1887	(__v4df) __B,
				1888	(__v4df) __C,
				1889	(__mmask8) __U);
				1890	}
				1891
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1892	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1893	_mm_mask_fnmadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1894	{
				1895	return (__m128) __builtin_ia32_vfnmaddps128_mask ((__v4sf) __A,
				1896	(__v4sf) __B,
				1897	(__v4sf) __C,
				1898	(__mmask8) __U);
				1899	}
				1900
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1901	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1902	_mm256_mask_fnmadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C)
				1903	{
				1904	return (__m256) __builtin_ia32_vfnmaddps256_mask ((__v8sf) __A,
				1905	(__v8sf) __B,
				1906	(__v8sf) __C,
				1907	(__mmask8) __U);
				1908	}
				1909
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1910	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1911	_mm_mask_fnmsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C)
				1912	{
				1913	return (__m128d) __builtin_ia32_vfnmsubpd128_mask ((__v2df) __A,
				1914	(__v2df) __B,
				1915	(__v2df) __C,
				1916	(__mmask8) __U);
				1917	}
				1918
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1919	static __inline__ __m128d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1920	_mm_mask3_fnmsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)
				1921	{
				1922	return (__m128d) __builtin_ia32_vfnmsubpd128_mask3 ((__v2df) __A,
				1923	(__v2df) __B,
				1924	(__v2df) __C,
				1925	(__mmask8) __U);
				1926	}
				1927
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1928	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1929	_mm256_mask_fnmsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C)
				1930	{
				1931	return (__m256d) __builtin_ia32_vfnmsubpd256_mask ((__v4df) __A,
				1932	(__v4df) __B,
				1933	(__v4df) __C,
				1934	(__mmask8) __U);
				1935	}
				1936
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1937	static __inline__ __m256d __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1938	_mm256_mask3_fnmsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)
				1939	{
				1940	return (__m256d) __builtin_ia32_vfnmsubpd256_mask3 ((__v4df) __A,
				1941	(__v4df) __B,
				1942	(__v4df) __C,
				1943	(__mmask8) __U);
				1944	}
				1945
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1946	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1947	_mm_mask_fnmsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C)
				1948	{
				1949	return (__m128) __builtin_ia32_vfnmsubps128_mask ((__v4sf) __A,
				1950	(__v4sf) __B,
				1951	(__v4sf) __C,
				1952	(__mmask8) __U);
				1953	}
				1954
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1955	static __inline__ __m128 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1956	_mm_mask3_fnmsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)
				1957	{
				1958	return (__m128) __builtin_ia32_vfnmsubps128_mask3 ((__v4sf) __A,
				1959	(__v4sf) __B,
				1960	(__v4sf) __C,
				1961	(__mmask8) __U);
				1962	}
				1963
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1964	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1965	_mm256_mask_fnmsub_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C)
				1966	{
				1967	return (__m256) __builtin_ia32_vfnmsubps256_mask ((__v8sf) __A,
				1968	(__v8sf) __B,
				1969	(__v8sf) __C,
				1970	(__mmask8) __U);
				1971	}
				1972
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	1973	static __inline__ __m256 __DEFAULT_FN_ATTRS
Elena Demikhovsky	c563c2c	2015-06-29 09:20:57 +0000	[diff] [blame]	1974	_mm256_mask3_fnmsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)
				1975	{
				1976	return (__m256) __builtin_ia32_vfnmsubps256_mask3 ((__v8sf) __A,
				1977	(__v8sf) __B,
				1978	(__v8sf) __C,
				1979	(__mmask8) __U);
				1980	}
				1981
Asaf Badouh	74da387	2015-07-28 08:26:14 +0000	[diff] [blame]	1982	static __inline__ __m128d __DEFAULT_FN_ATTRS
				1983	_mm_mask_add_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				1984	return (__m128d) __builtin_ia32_addpd128_mask ((__v2df) __A,
				1985	(__v2df) __B,
				1986	(__v2df) __W,
				1987	(__mmask8) __U);
				1988	}
				1989
				1990	static __inline__ __m128d __DEFAULT_FN_ATTRS
				1991	_mm_maskz_add_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				1992	return (__m128d) __builtin_ia32_addpd128_mask ((__v2df) __A,
				1993	(__v2df) __B,
				1994	(__v2df)
				1995	_mm_setzero_pd (),
				1996	(__mmask8) __U);
				1997	}
				1998
				1999	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2000	_mm256_mask_add_pd (__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
				2001	return (__m256d) __builtin_ia32_addpd256_mask ((__v4df) __A,
				2002	(__v4df) __B,
				2003	(__v4df) __W,
				2004	(__mmask8) __U);
				2005	}
				2006
				2007	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2008	_mm256_maskz_add_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				2009	return (__m256d) __builtin_ia32_addpd256_mask ((__v4df) __A,
				2010	(__v4df) __B,
				2011	(__v4df)
				2012	_mm256_setzero_pd (),
				2013	(__mmask8) __U);
				2014	}
				2015
				2016	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2017	_mm_mask_add_ps (__m128 __W, __mmask16 __U, __m128 __A, __m128 __B) {
				2018	return (__m128) __builtin_ia32_addps128_mask ((__v4sf) __A,
				2019	(__v4sf) __B,
				2020	(__v4sf) __W,
				2021	(__mmask8) __U);
				2022	}
				2023
				2024	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2025	_mm_maskz_add_ps (__mmask16 __U, __m128 __A, __m128 __B) {
				2026	return (__m128) __builtin_ia32_addps128_mask ((__v4sf) __A,
				2027	(__v4sf) __B,
				2028	(__v4sf)
				2029	_mm_setzero_ps (),
				2030	(__mmask8) __U);
				2031	}
				2032
				2033	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2034	_mm256_mask_add_ps (__m256 __W, __mmask16 __U, __m256 __A, __m256 __B) {
				2035	return (__m256) __builtin_ia32_addps256_mask ((__v8sf) __A,
				2036	(__v8sf) __B,
				2037	(__v8sf) __W,
				2038	(__mmask8) __U);
				2039	}
				2040
				2041	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2042	_mm256_maskz_add_ps (__mmask16 __U, __m256 __A, __m256 __B) {
				2043	return (__m256) __builtin_ia32_addps256_mask ((__v8sf) __A,
				2044	(__v8sf) __B,
				2045	(__v8sf)
				2046	_mm256_setzero_ps (),
				2047	(__mmask8) __U);
				2048	}
				2049
				2050	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2051	_mm_mask_blend_epi32 (__mmask8 __U, __m128i __A, __m128i __W) {
				2052	return (__m128i) __builtin_ia32_blendmd_128_mask ((__v4si) __A,
				2053	(__v4si) __W,
				2054	(__mmask8) __U);
				2055	}
				2056
				2057	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2058	_mm256_mask_blend_epi32 (__mmask8 __U, __m256i __A, __m256i __W) {
				2059	return (__m256i) __builtin_ia32_blendmd_256_mask ((__v8si) __A,
				2060	(__v8si) __W,
				2061	(__mmask8) __U);
				2062	}
				2063
				2064	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2065	_mm_mask_blend_pd (__mmask8 __U, __m128d __A, __m128d __W) {
				2066	return (__m128d) __builtin_ia32_blendmpd_128_mask ((__v2df) __A,
				2067	(__v2df) __W,
				2068	(__mmask8) __U);
				2069	}
				2070
				2071	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2072	_mm256_mask_blend_pd (__mmask8 __U, __m256d __A, __m256d __W) {
				2073	return (__m256d) __builtin_ia32_blendmpd_256_mask ((__v4df) __A,
				2074	(__v4df) __W,
				2075	(__mmask8) __U);
				2076	}
				2077
				2078	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2079	_mm_mask_blend_ps (__mmask8 __U, __m128 __A, __m128 __W) {
				2080	return (__m128) __builtin_ia32_blendmps_128_mask ((__v4sf) __A,
				2081	(__v4sf) __W,
				2082	(__mmask8) __U);
				2083	}
				2084
				2085	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2086	_mm256_mask_blend_ps (__mmask8 __U, __m256 __A, __m256 __W) {
				2087	return (__m256) __builtin_ia32_blendmps_256_mask ((__v8sf) __A,
				2088	(__v8sf) __W,
				2089	(__mmask8) __U);
				2090	}
				2091
				2092	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2093	_mm_mask_blend_epi64 (__mmask8 __U, __m128i __A, __m128i __W) {
				2094	return (__m128i) __builtin_ia32_blendmq_128_mask ((__v2di) __A,
				2095	(__v2di) __W,
				2096	(__mmask8) __U);
				2097	}
				2098
				2099	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2100	_mm256_mask_blend_epi64 (__mmask8 __U, __m256i __A, __m256i __W) {
				2101	return (__m256i) __builtin_ia32_blendmq_256_mask ((__v4di) __A,
				2102	(__v4di) __W,
				2103	(__mmask8) __U);
				2104	}
				2105
				2106	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2107	_mm_mask_compress_pd (__m128d __W, __mmask8 __U, __m128d __A) {
				2108	return (__m128d) __builtin_ia32_compressdf128_mask ((__v2df) __A,
				2109	(__v2df) __W,
				2110	(__mmask8) __U);
				2111	}
				2112
				2113	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2114	_mm_maskz_compress_pd (__mmask8 __U, __m128d __A) {
				2115	return (__m128d) __builtin_ia32_compressdf128_mask ((__v2df) __A,
				2116	(__v2df)
				2117	_mm_setzero_pd (),
				2118	(__mmask8) __U);
				2119	}
				2120
				2121	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2122	_mm256_mask_compress_pd (__m256d __W, __mmask8 __U, __m256d __A) {
				2123	return (__m256d) __builtin_ia32_compressdf256_mask ((__v4df) __A,
				2124	(__v4df) __W,
				2125	(__mmask8) __U);
				2126	}
				2127
				2128	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2129	_mm256_maskz_compress_pd (__mmask8 __U, __m256d __A) {
				2130	return (__m256d) __builtin_ia32_compressdf256_mask ((__v4df) __A,
				2131	(__v4df)
				2132	_mm256_setzero_pd (),
				2133	(__mmask8) __U);
				2134	}
				2135
				2136	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2137	_mm_mask_compress_epi64 (__m128i __W, __mmask8 __U, __m128i __A) {
				2138	return (__m128i) __builtin_ia32_compressdi128_mask ((__v2di) __A,
				2139	(__v2di) __W,
				2140	(__mmask8) __U);
				2141	}
				2142
				2143	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2144	_mm_maskz_compress_epi64 (__mmask8 __U, __m128i __A) {
				2145	return (__m128i) __builtin_ia32_compressdi128_mask ((__v2di) __A,
				2146	(__v2di)
				2147	_mm_setzero_si128 (),
				2148	(__mmask8) __U);
				2149	}
				2150
				2151	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2152	_mm256_mask_compress_epi64 (__m256i __W, __mmask8 __U, __m256i __A) {
				2153	return (__m256i) __builtin_ia32_compressdi256_mask ((__v4di) __A,
				2154	(__v4di) __W,
				2155	(__mmask8) __U);
				2156	}
				2157
				2158	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2159	_mm256_maskz_compress_epi64 (__mmask8 __U, __m256i __A) {
				2160	return (__m256i) __builtin_ia32_compressdi256_mask ((__v4di) __A,
				2161	(__v4di)
				2162	_mm256_setzero_si256 (),
				2163	(__mmask8) __U);
				2164	}
				2165
				2166	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2167	_mm_mask_compress_ps (__m128 __W, __mmask8 __U, __m128 __A) {
				2168	return (__m128) __builtin_ia32_compresssf128_mask ((__v4sf) __A,
				2169	(__v4sf) __W,
				2170	(__mmask8) __U);
				2171	}
				2172
				2173	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2174	_mm_maskz_compress_ps (__mmask8 __U, __m128 __A) {
				2175	return (__m128) __builtin_ia32_compresssf128_mask ((__v4sf) __A,
				2176	(__v4sf)
				2177	_mm_setzero_ps (),
				2178	(__mmask8) __U);
				2179	}
				2180
				2181	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2182	_mm256_mask_compress_ps (__m256 __W, __mmask8 __U, __m256 __A) {
				2183	return (__m256) __builtin_ia32_compresssf256_mask ((__v8sf) __A,
				2184	(__v8sf) __W,
				2185	(__mmask8) __U);
				2186	}
				2187
				2188	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2189	_mm256_maskz_compress_ps (__mmask8 __U, __m256 __A) {
				2190	return (__m256) __builtin_ia32_compresssf256_mask ((__v8sf) __A,
				2191	(__v8sf)
				2192	_mm256_setzero_ps (),
				2193	(__mmask8) __U);
				2194	}
				2195
				2196	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2197	_mm_mask_compress_epi32 (__m128i __W, __mmask8 __U, __m128i __A) {
				2198	return (__m128i) __builtin_ia32_compresssi128_mask ((__v4si) __A,
				2199	(__v4si) __W,
				2200	(__mmask8) __U);
				2201	}
				2202
				2203	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2204	_mm_maskz_compress_epi32 (__mmask8 __U, __m128i __A) {
				2205	return (__m128i) __builtin_ia32_compresssi128_mask ((__v4si) __A,
				2206	(__v4si)
				2207	_mm_setzero_si128 (),
				2208	(__mmask8) __U);
				2209	}
				2210
				2211	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2212	_mm256_mask_compress_epi32 (__m256i __W, __mmask8 __U, __m256i __A) {
				2213	return (__m256i) __builtin_ia32_compresssi256_mask ((__v8si) __A,
				2214	(__v8si) __W,
				2215	(__mmask8) __U);
				2216	}
				2217
				2218	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2219	_mm256_maskz_compress_epi32 (__mmask8 __U, __m256i __A) {
				2220	return (__m256i) __builtin_ia32_compresssi256_mask ((__v8si) __A,
				2221	(__v8si)
				2222	_mm256_setzero_si256 (),
				2223	(__mmask8) __U);
				2224	}
				2225
				2226	static __inline__ void __DEFAULT_FN_ATTRS
				2227	_mm_mask_compressstoreu_pd (void *__P, __mmask8 __U, __m128d __A) {
				2228	__builtin_ia32_compressstoredf128_mask ((__v2df *) __P,
				2229	(__v2df) __A,
				2230	(__mmask8) __U);
				2231	}
				2232
				2233	static __inline__ void __DEFAULT_FN_ATTRS
				2234	_mm256_mask_compressstoreu_pd (void *__P, __mmask8 __U, __m256d __A) {
				2235	__builtin_ia32_compressstoredf256_mask ((__v4df *) __P,
				2236	(__v4df) __A,
				2237	(__mmask8) __U);
				2238	}
				2239
				2240	static __inline__ void __DEFAULT_FN_ATTRS
				2241	_mm_mask_compressstoreu_epi64 (void *__P, __mmask8 __U, __m128i __A) {
				2242	__builtin_ia32_compressstoredi128_mask ((__v2di *) __P,
				2243	(__v2di) __A,
				2244	(__mmask8) __U);
				2245	}
				2246
				2247	static __inline__ void __DEFAULT_FN_ATTRS
				2248	_mm256_mask_compressstoreu_epi64 (void *__P, __mmask8 __U, __m256i __A) {
				2249	__builtin_ia32_compressstoredi256_mask ((__v4di *) __P,
				2250	(__v4di) __A,
				2251	(__mmask8) __U);
				2252	}
				2253
				2254	static __inline__ void __DEFAULT_FN_ATTRS
				2255	_mm_mask_compressstoreu_ps (void *__P, __mmask8 __U, __m128 __A) {
				2256	__builtin_ia32_compressstoresf128_mask ((__v4sf *) __P,
				2257	(__v4sf) __A,
				2258	(__mmask8) __U);
				2259	}
				2260
				2261	static __inline__ void __DEFAULT_FN_ATTRS
				2262	_mm256_mask_compressstoreu_ps (void *__P, __mmask8 __U, __m256 __A) {
				2263	__builtin_ia32_compressstoresf256_mask ((__v8sf *) __P,
				2264	(__v8sf) __A,
				2265	(__mmask8) __U);
				2266	}
				2267
				2268	static __inline__ void __DEFAULT_FN_ATTRS
				2269	_mm_mask_compressstoreu_epi32 (void *__P, __mmask8 __U, __m128i __A) {
				2270	__builtin_ia32_compressstoresi128_mask ((__v4si *) __P,
				2271	(__v4si) __A,
				2272	(__mmask8) __U);
				2273	}
				2274
				2275	static __inline__ void __DEFAULT_FN_ATTRS
				2276	_mm256_mask_compressstoreu_epi32 (void *__P, __mmask8 __U, __m256i __A) {
				2277	__builtin_ia32_compressstoresi256_mask ((__v8si *) __P,
				2278	(__v8si) __A,
				2279	(__mmask8) __U);
				2280	}
				2281
				2282	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2283	_mm_mask_cvtepi32_pd (__m128d __W, __mmask8 __U, __m128i __A) {
				2284	return (__m128d) __builtin_ia32_cvtdq2pd128_mask ((__v4si) __A,
				2285	(__v2df) __W,
				2286	(__mmask8) __U);
				2287	}
				2288
				2289	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2290	_mm_maskz_cvtepi32_pd (__mmask8 __U, __m128i __A) {
				2291	return (__m128d) __builtin_ia32_cvtdq2pd128_mask ((__v4si) __A,
				2292	(__v2df)
				2293	_mm_setzero_pd (),
				2294	(__mmask8) __U);
				2295	}
				2296
				2297	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2298	_mm256_mask_cvtepi32_pd (__m256d __W, __mmask8 __U, __m128i __A) {
				2299	return (__m256d) __builtin_ia32_cvtdq2pd256_mask ((__v4si) __A,
				2300	(__v4df) __W,
				2301	(__mmask8) __U);
				2302	}
				2303
				2304	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2305	_mm256_maskz_cvtepi32_pd (__mmask8 __U, __m128i __A) {
				2306	return (__m256d) __builtin_ia32_cvtdq2pd256_mask ((__v4si) __A,
				2307	(__v4df)
				2308	_mm256_setzero_pd (),
				2309	(__mmask8) __U);
				2310	}
				2311
				2312	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2313	_mm_mask_cvtepi32_ps (__m128 __W, __mmask8 __U, __m128i __A) {
				2314	return (__m128) __builtin_ia32_cvtdq2ps128_mask ((__v4si) __A,
				2315	(__v4sf) __W,
				2316	(__mmask8) __U);
				2317	}
				2318
				2319	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2320	_mm_maskz_cvtepi32_ps (__mmask16 __U, __m128i __A) {
				2321	return (__m128) __builtin_ia32_cvtdq2ps128_mask ((__v4si) __A,
				2322	(__v4sf)
				2323	_mm_setzero_ps (),
				2324	(__mmask8) __U);
				2325	}
				2326
				2327	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2328	_mm256_mask_cvtepi32_ps (__m256 __W, __mmask8 __U, __m256i __A) {
				2329	return (__m256) __builtin_ia32_cvtdq2ps256_mask ((__v8si) __A,
				2330	(__v8sf) __W,
				2331	(__mmask8) __U);
				2332	}
				2333
				2334	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2335	_mm256_maskz_cvtepi32_ps (__mmask16 __U, __m256i __A) {
				2336	return (__m256) __builtin_ia32_cvtdq2ps256_mask ((__v8si) __A,
				2337	(__v8sf)
				2338	_mm256_setzero_ps (),
				2339	(__mmask8) __U);
				2340	}
				2341
				2342	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2343	_mm_mask_cvtpd_epi32 (__m128i __W, __mmask8 __U, __m128d __A) {
				2344	return (__m128i) __builtin_ia32_cvtpd2dq128_mask ((__v2df) __A,
				2345	(__v4si) __W,
				2346	(__mmask8) __U);
				2347	}
				2348
				2349	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2350	_mm_maskz_cvtpd_epi32 (__mmask8 __U, __m128d __A) {
				2351	return (__m128i) __builtin_ia32_cvtpd2dq128_mask ((__v2df) __A,
				2352	(__v4si)
				2353	_mm_setzero_si128 (),
				2354	(__mmask8) __U);
				2355	}
				2356
				2357	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2358	_mm256_mask_cvtpd_epi32 (__m128i __W, __mmask8 __U, __m256d __A) {
				2359	return (__m128i) __builtin_ia32_cvtpd2dq256_mask ((__v4df) __A,
				2360	(__v4si) __W,
				2361	(__mmask8) __U);
				2362	}
				2363
				2364	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2365	_mm256_maskz_cvtpd_epi32 (__mmask8 __U, __m256d __A) {
				2366	return (__m128i) __builtin_ia32_cvtpd2dq256_mask ((__v4df) __A,
				2367	(__v4si)
				2368	_mm_setzero_si128 (),
				2369	(__mmask8) __U);
				2370	}
				2371
				2372	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2373	_mm_mask_cvtpd_ps (__m128 __W, __mmask8 __U, __m128d __A) {
				2374	return (__m128) __builtin_ia32_cvtpd2ps_mask ((__v2df) __A,
				2375	(__v4sf) __W,
				2376	(__mmask8) __U);
				2377	}
				2378
				2379	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2380	_mm_maskz_cvtpd_ps (__mmask8 __U, __m128d __A) {
				2381	return (__m128) __builtin_ia32_cvtpd2ps_mask ((__v2df) __A,
				2382	(__v4sf)
				2383	_mm_setzero_ps (),
				2384	(__mmask8) __U);
				2385	}
				2386
				2387	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2388	_mm256_mask_cvtpd_ps (__m128 __W, __mmask8 __U, __m256d __A) {
				2389	return (__m128) __builtin_ia32_cvtpd2ps256_mask ((__v4df) __A,
				2390	(__v4sf) __W,
				2391	(__mmask8) __U);
				2392	}
				2393
				2394	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2395	_mm256_maskz_cvtpd_ps (__mmask8 __U, __m256d __A) {
				2396	return (__m128) __builtin_ia32_cvtpd2ps256_mask ((__v4df) __A,
				2397	(__v4sf)
				2398	_mm_setzero_ps (),
				2399	(__mmask8) __U);
				2400	}
				2401
				2402	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2403	_mm_cvtpd_epu32 (__m128d __A) {
				2404	return (__m128i) __builtin_ia32_cvtpd2udq128_mask ((__v2df) __A,
				2405	(__v4si)
				2406	_mm_setzero_si128 (),
				2407	(__mmask8) -1);
				2408	}
				2409
				2410	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2411	_mm_mask_cvtpd_epu32 (__m128i __W, __mmask8 __U, __m128d __A) {
				2412	return (__m128i) __builtin_ia32_cvtpd2udq128_mask ((__v2df) __A,
				2413	(__v4si) __W,
				2414	(__mmask8) __U);
				2415	}
				2416
				2417	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2418	_mm_maskz_cvtpd_epu32 (__mmask8 __U, __m128d __A) {
				2419	return (__m128i) __builtin_ia32_cvtpd2udq128_mask ((__v2df) __A,
				2420	(__v4si)
				2421	_mm_setzero_si128 (),
				2422	(__mmask8) __U);
				2423	}
				2424
				2425	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2426	_mm256_cvtpd_epu32 (__m256d __A) {
				2427	return (__m128i) __builtin_ia32_cvtpd2udq256_mask ((__v4df) __A,
				2428	(__v4si)
				2429	_mm_setzero_si128 (),
				2430	(__mmask8) -1);
				2431	}
				2432
				2433	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2434	_mm256_mask_cvtpd_epu32 (__m128i __W, __mmask8 __U, __m256d __A) {
				2435	return (__m128i) __builtin_ia32_cvtpd2udq256_mask ((__v4df) __A,
				2436	(__v4si) __W,
				2437	(__mmask8) __U);
				2438	}
				2439
				2440	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2441	_mm256_maskz_cvtpd_epu32 (__mmask8 __U, __m256d __A) {
				2442	return (__m128i) __builtin_ia32_cvtpd2udq256_mask ((__v4df) __A,
				2443	(__v4si)
				2444	_mm_setzero_si128 (),
				2445	(__mmask8) __U);
				2446	}
				2447
				2448	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2449	_mm_mask_cvtps_epi32 (__m128i __W, __mmask8 __U, __m128 __A) {
				2450	return (__m128i) __builtin_ia32_cvtps2dq128_mask ((__v4sf) __A,
				2451	(__v4si) __W,
				2452	(__mmask8) __U);
				2453	}
				2454
				2455	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2456	_mm_maskz_cvtps_epi32 (__mmask8 __U, __m128 __A) {
				2457	return (__m128i) __builtin_ia32_cvtps2dq128_mask ((__v4sf) __A,
				2458	(__v4si)
				2459	_mm_setzero_si128 (),
				2460	(__mmask8) __U);
				2461	}
				2462
				2463	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2464	_mm256_mask_cvtps_epi32 (__m256i __W, __mmask8 __U, __m256 __A) {
				2465	return (__m256i) __builtin_ia32_cvtps2dq256_mask ((__v8sf) __A,
				2466	(__v8si) __W,
				2467	(__mmask8) __U);
				2468	}
				2469
				2470	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2471	_mm256_maskz_cvtps_epi32 (__mmask8 __U, __m256 __A) {
				2472	return (__m256i) __builtin_ia32_cvtps2dq256_mask ((__v8sf) __A,
				2473	(__v8si)
				2474	_mm256_setzero_si256 (),
				2475	(__mmask8) __U);
				2476	}
				2477
				2478	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2479	_mm_mask_cvtps_pd (__m128d __W, __mmask8 __U, __m128 __A) {
				2480	return (__m128d) __builtin_ia32_cvtps2pd128_mask ((__v4sf) __A,
				2481	(__v2df) __W,
				2482	(__mmask8) __U);
				2483	}
				2484
				2485	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2486	_mm_maskz_cvtps_pd (__mmask8 __U, __m128 __A) {
				2487	return (__m128d) __builtin_ia32_cvtps2pd128_mask ((__v4sf) __A,
				2488	(__v2df)
				2489	_mm_setzero_pd (),
				2490	(__mmask8) __U);
				2491	}
				2492
				2493	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2494	_mm256_mask_cvtps_pd (__m256d __W, __mmask8 __U, __m128 __A) {
				2495	return (__m256d) __builtin_ia32_cvtps2pd256_mask ((__v4sf) __A,
				2496	(__v4df) __W,
				2497	(__mmask8) __U);
				2498	}
				2499
				2500	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2501	_mm256_maskz_cvtps_pd (__mmask8 __U, __m128 __A) {
				2502	return (__m256d) __builtin_ia32_cvtps2pd256_mask ((__v4sf) __A,
				2503	(__v4df)
				2504	_mm256_setzero_pd (),
				2505	(__mmask8) __U);
				2506	}
				2507
				2508	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2509	_mm_cvtps_epu32 (__m128 __A) {
				2510	return (__m128i) __builtin_ia32_cvtps2udq128_mask ((__v4sf) __A,
				2511	(__v4si)
				2512	_mm_setzero_si128 (),
				2513	(__mmask8) -1);
				2514	}
				2515
				2516	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2517	_mm_mask_cvtps_epu32 (__m128i __W, __mmask8 __U, __m128 __A) {
				2518	return (__m128i) __builtin_ia32_cvtps2udq128_mask ((__v4sf) __A,
				2519	(__v4si) __W,
				2520	(__mmask8) __U);
				2521	}
				2522
				2523	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2524	_mm_maskz_cvtps_epu32 (__mmask8 __U, __m128 __A) {
				2525	return (__m128i) __builtin_ia32_cvtps2udq128_mask ((__v4sf) __A,
				2526	(__v4si)
				2527	_mm_setzero_si128 (),
				2528	(__mmask8) __U);
				2529	}
				2530
				2531	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2532	_mm256_cvtps_epu32 (__m256 __A) {
				2533	return (__m256i) __builtin_ia32_cvtps2udq256_mask ((__v8sf) __A,
				2534	(__v8si)
				2535	_mm256_setzero_si256 (),
				2536	(__mmask8) -1);
				2537	}
				2538
				2539	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2540	_mm256_mask_cvtps_epu32 (__m256i __W, __mmask8 __U, __m256 __A) {
				2541	return (__m256i) __builtin_ia32_cvtps2udq256_mask ((__v8sf) __A,
				2542	(__v8si) __W,
				2543	(__mmask8) __U);
				2544	}
				2545
				2546	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2547	_mm256_maskz_cvtps_epu32 (__mmask8 __U, __m256 __A) {
				2548	return (__m256i) __builtin_ia32_cvtps2udq256_mask ((__v8sf) __A,
				2549	(__v8si)
				2550	_mm256_setzero_si256 (),
				2551	(__mmask8) __U);
				2552	}
				2553
				2554	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2555	_mm_mask_cvttpd_epi32 (__m128i __W, __mmask8 __U, __m128d __A) {
				2556	return (__m128i) __builtin_ia32_cvttpd2dq128_mask ((__v2df) __A,
				2557	(__v4si) __W,
				2558	(__mmask8) __U);
				2559	}
				2560
				2561	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2562	_mm_maskz_cvttpd_epi32 (__mmask8 __U, __m128d __A) {
				2563	return (__m128i) __builtin_ia32_cvttpd2dq128_mask ((__v2df) __A,
				2564	(__v4si)
				2565	_mm_setzero_si128 (),
				2566	(__mmask8) __U);
				2567	}
				2568
				2569	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2570	_mm256_mask_cvttpd_epi32 (__m128i __W, __mmask8 __U, __m256d __A) {
				2571	return (__m128i) __builtin_ia32_cvttpd2dq256_mask ((__v4df) __A,
				2572	(__v4si) __W,
				2573	(__mmask8) __U);
				2574	}
				2575
				2576	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2577	_mm256_maskz_cvttpd_epi32 (__mmask8 __U, __m256d __A) {
				2578	return (__m128i) __builtin_ia32_cvttpd2dq256_mask ((__v4df) __A,
				2579	(__v4si)
				2580	_mm_setzero_si128 (),
				2581	(__mmask8) __U);
				2582	}
				2583
				2584	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2585	_mm_cvttpd_epu32 (__m128d __A) {
				2586	return (__m128i) __builtin_ia32_cvttpd2udq128_mask ((__v2df) __A,
				2587	(__v4si)
				2588	_mm_setzero_si128 (),
				2589	(__mmask8) -1);
				2590	}
				2591
				2592	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2593	_mm_mask_cvttpd_epu32 (__m128i __W, __mmask8 __U, __m128d __A) {
				2594	return (__m128i) __builtin_ia32_cvttpd2udq128_mask ((__v2df) __A,
				2595	(__v4si) __W,
				2596	(__mmask8) __U);
				2597	}
				2598
				2599	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2600	_mm_maskz_cvttpd_epu32 (__mmask8 __U, __m128d __A) {
				2601	return (__m128i) __builtin_ia32_cvttpd2udq128_mask ((__v2df) __A,
				2602	(__v4si)
				2603	_mm_setzero_si128 (),
				2604	(__mmask8) __U);
				2605	}
				2606
				2607	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2608	_mm256_cvttpd_epu32 (__m256d __A) {
				2609	return (__m128i) __builtin_ia32_cvttpd2udq256_mask ((__v4df) __A,
				2610	(__v4si)
				2611	_mm_setzero_si128 (),
				2612	(__mmask8) -1);
				2613	}
				2614
				2615	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2616	_mm256_mask_cvttpd_epu32 (__m128i __W, __mmask8 __U, __m256d __A) {
				2617	return (__m128i) __builtin_ia32_cvttpd2udq256_mask ((__v4df) __A,
				2618	(__v4si) __W,
				2619	(__mmask8) __U);
				2620	}
				2621
				2622	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2623	_mm256_maskz_cvttpd_epu32 (__mmask8 __U, __m256d __A) {
				2624	return (__m128i) __builtin_ia32_cvttpd2udq256_mask ((__v4df) __A,
				2625	(__v4si)
				2626	_mm_setzero_si128 (),
				2627	(__mmask8) __U);
				2628	}
				2629
				2630	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2631	_mm_mask_cvttps_epi32 (__m128i __W, __mmask8 __U, __m128 __A) {
				2632	return (__m128i) __builtin_ia32_cvttps2dq128_mask ((__v4sf) __A,
				2633	(__v4si) __W,
				2634	(__mmask8) __U);
				2635	}
				2636
				2637	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2638	_mm_maskz_cvttps_epi32 (__mmask8 __U, __m128 __A) {
				2639	return (__m128i) __builtin_ia32_cvttps2dq128_mask ((__v4sf) __A,
				2640	(__v4si)
				2641	_mm_setzero_si128 (),
				2642	(__mmask8) __U);
				2643	}
				2644
				2645	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2646	_mm256_mask_cvttps_epi32 (__m256i __W, __mmask8 __U, __m256 __A) {
				2647	return (__m256i) __builtin_ia32_cvttps2dq256_mask ((__v8sf) __A,
				2648	(__v8si) __W,
				2649	(__mmask8) __U);
				2650	}
				2651
				2652	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2653	_mm256_maskz_cvttps_epi32 (__mmask8 __U, __m256 __A) {
				2654	return (__m256i) __builtin_ia32_cvttps2dq256_mask ((__v8sf) __A,
				2655	(__v8si)
				2656	_mm256_setzero_si256 (),
				2657	(__mmask8) __U);
				2658	}
				2659
				2660	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2661	_mm_cvttps_epu32 (__m128 __A) {
				2662	return (__m128i) __builtin_ia32_cvttps2udq128_mask ((__v4sf) __A,
				2663	(__v4si)
				2664	_mm_setzero_si128 (),
				2665	(__mmask8) -1);
				2666	}
				2667
				2668	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2669	_mm_mask_cvttps_epu32 (__m128i __W, __mmask8 __U, __m128 __A) {
				2670	return (__m128i) __builtin_ia32_cvttps2udq128_mask ((__v4sf) __A,
				2671	(__v4si) __W,
				2672	(__mmask8) __U);
				2673	}
				2674
				2675	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2676	_mm_maskz_cvttps_epu32 (__mmask8 __U, __m128 __A) {
				2677	return (__m128i) __builtin_ia32_cvttps2udq128_mask ((__v4sf) __A,
				2678	(__v4si)
				2679	_mm_setzero_si128 (),
				2680	(__mmask8) __U);
				2681	}
				2682
				2683	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2684	_mm256_cvttps_epu32 (__m256 __A) {
				2685	return (__m256i) __builtin_ia32_cvttps2udq256_mask ((__v8sf) __A,
				2686	(__v8si)
				2687	_mm256_setzero_si256 (),
				2688	(__mmask8) -1);
				2689	}
				2690
				2691	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2692	_mm256_mask_cvttps_epu32 (__m256i __W, __mmask8 __U, __m256 __A) {
				2693	return (__m256i) __builtin_ia32_cvttps2udq256_mask ((__v8sf) __A,
				2694	(__v8si) __W,
				2695	(__mmask8) __U);
				2696	}
				2697
				2698	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2699	_mm256_maskz_cvttps_epu32 (__mmask8 __U, __m256 __A) {
				2700	return (__m256i) __builtin_ia32_cvttps2udq256_mask ((__v8sf) __A,
				2701	(__v8si)
				2702	_mm256_setzero_si256 (),
				2703	(__mmask8) __U);
				2704	}
				2705
				2706	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2707	_mm_cvtepu32_pd (__m128i __A) {
				2708	return (__m128d) __builtin_ia32_cvtudq2pd128_mask ((__v4si) __A,
				2709	(__v2df)
				2710	_mm_setzero_pd (),
				2711	(__mmask8) -1);
				2712	}
				2713
				2714	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2715	_mm_mask_cvtepu32_pd (__m128d __W, __mmask8 __U, __m128i __A) {
				2716	return (__m128d) __builtin_ia32_cvtudq2pd128_mask ((__v4si) __A,
				2717	(__v2df) __W,
				2718	(__mmask8) __U);
				2719	}
				2720
				2721	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2722	_mm_maskz_cvtepu32_pd (__mmask8 __U, __m128i __A) {
				2723	return (__m128d) __builtin_ia32_cvtudq2pd128_mask ((__v4si) __A,
				2724	(__v2df)
				2725	_mm_setzero_pd (),
				2726	(__mmask8) __U);
				2727	}
				2728
				2729	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2730	_mm256_cvtepu32_pd (__m128i __A) {
				2731	return (__m256d) __builtin_ia32_cvtudq2pd256_mask ((__v4si) __A,
				2732	(__v4df)
				2733	_mm256_setzero_pd (),
				2734	(__mmask8) -1);
				2735	}
				2736
				2737	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2738	_mm256_mask_cvtepu32_pd (__m256d __W, __mmask8 __U, __m128i __A) {
				2739	return (__m256d) __builtin_ia32_cvtudq2pd256_mask ((__v4si) __A,
				2740	(__v4df) __W,
				2741	(__mmask8) __U);
				2742	}
				2743
				2744	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2745	_mm256_maskz_cvtepu32_pd (__mmask8 __U, __m128i __A) {
				2746	return (__m256d) __builtin_ia32_cvtudq2pd256_mask ((__v4si) __A,
				2747	(__v4df)
				2748	_mm256_setzero_pd (),
				2749	(__mmask8) __U);
				2750	}
				2751
				2752	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2753	_mm_cvtepu32_ps (__m128i __A) {
				2754	return (__m128) __builtin_ia32_cvtudq2ps128_mask ((__v4si) __A,
				2755	(__v4sf)
				2756	_mm_setzero_ps (),
				2757	(__mmask8) -1);
				2758	}
				2759
				2760	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2761	_mm_mask_cvtepu32_ps (__m128 __W, __mmask8 __U, __m128i __A) {
				2762	return (__m128) __builtin_ia32_cvtudq2ps128_mask ((__v4si) __A,
				2763	(__v4sf) __W,
				2764	(__mmask8) __U);
				2765	}
				2766
				2767	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2768	_mm_maskz_cvtepu32_ps (__mmask8 __U, __m128i __A) {
				2769	return (__m128) __builtin_ia32_cvtudq2ps128_mask ((__v4si) __A,
				2770	(__v4sf)
				2771	_mm_setzero_ps (),
				2772	(__mmask8) __U);
				2773	}
				2774
				2775	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2776	_mm256_cvtepu32_ps (__m256i __A) {
				2777	return (__m256) __builtin_ia32_cvtudq2ps256_mask ((__v8si) __A,
				2778	(__v8sf)
				2779	_mm256_setzero_ps (),
				2780	(__mmask8) -1);
				2781	}
				2782
				2783	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2784	_mm256_mask_cvtepu32_ps (__m256 __W, __mmask8 __U, __m256i __A) {
				2785	return (__m256) __builtin_ia32_cvtudq2ps256_mask ((__v8si) __A,
				2786	(__v8sf) __W,
				2787	(__mmask8) __U);
				2788	}
				2789
				2790	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2791	_mm256_maskz_cvtepu32_ps (__mmask8 __U, __m256i __A) {
				2792	return (__m256) __builtin_ia32_cvtudq2ps256_mask ((__v8si) __A,
				2793	(__v8sf)
				2794	_mm256_setzero_ps (),
				2795	(__mmask8) __U);
				2796	}
				2797
Asaf Badouh	78ee5cc	2015-07-28 10:30:56 +0000	[diff] [blame]	2798	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2799	_mm_mask_div_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				2800	return (__m128d) __builtin_ia32_divpd_mask ((__v2df) __A,
				2801	(__v2df) __B,
				2802	(__v2df) __W,
				2803	(__mmask8) __U);
				2804	}
				2805
				2806	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2807	_mm_maskz_div_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				2808	return (__m128d) __builtin_ia32_divpd_mask ((__v2df) __A,
				2809	(__v2df) __B,
				2810	(__v2df)
				2811	_mm_setzero_pd (),
				2812	(__mmask8) __U);
				2813	}
				2814
				2815	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2816	_mm256_mask_div_pd (__m256d __W, __mmask8 __U, __m256d __A,
				2817	__m256d __B) {
				2818	return (__m256d) __builtin_ia32_divpd256_mask ((__v4df) __A,
				2819	(__v4df) __B,
				2820	(__v4df) __W,
				2821	(__mmask8) __U);
				2822	}
				2823
				2824	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2825	_mm256_maskz_div_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				2826	return (__m256d) __builtin_ia32_divpd256_mask ((__v4df) __A,
				2827	(__v4df) __B,
				2828	(__v4df)
				2829	_mm256_setzero_pd (),
				2830	(__mmask8) __U);
				2831	}
				2832
				2833	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2834	_mm_mask_div_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
				2835	return (__m128) __builtin_ia32_divps_mask ((__v4sf) __A,
				2836	(__v4sf) __B,
				2837	(__v4sf) __W,
				2838	(__mmask8) __U);
				2839	}
				2840
				2841	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2842	_mm_maskz_div_ps (__mmask8 __U, __m128 __A, __m128 __B) {
				2843	return (__m128) __builtin_ia32_divps_mask ((__v4sf) __A,
				2844	(__v4sf) __B,
				2845	(__v4sf)
				2846	_mm_setzero_ps (),
				2847	(__mmask8) __U);
				2848	}
				2849
				2850	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2851	_mm256_mask_div_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
				2852	return (__m256) __builtin_ia32_divps256_mask ((__v8sf) __A,
				2853	(__v8sf) __B,
				2854	(__v8sf) __W,
				2855	(__mmask8) __U);
				2856	}
				2857
				2858	static __inline__ __m256 __DEFAULT_FN_ATTRS
				2859	_mm256_maskz_div_ps (__mmask8 __U, __m256 __A, __m256 __B) {
				2860	return (__m256) __builtin_ia32_divps256_mask ((__v8sf) __A,
				2861	(__v8sf) __B,
				2862	(__v8sf)
				2863	_mm256_setzero_ps (),
				2864	(__mmask8) __U);
				2865	}
				2866
				2867	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2868	_mm_mask_expand_pd (__m128d __W, __mmask8 __U, __m128d __A) {
				2869	return (__m128d) __builtin_ia32_expanddf128_mask ((__v2df) __A,
				2870	(__v2df) __W,
				2871	(__mmask8) __U);
				2872	}
				2873
				2874	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2875	_mm_maskz_expand_pd (__mmask8 __U, __m128d __A) {
				2876	return (__m128d) __builtin_ia32_expanddf128_mask ((__v2df) __A,
				2877	(__v2df)
				2878	_mm_setzero_pd (),
				2879	(__mmask8) __U);
				2880	}
				2881
				2882	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2883	_mm256_mask_expand_pd (__m256d __W, __mmask8 __U, __m256d __A) {
				2884	return (__m256d) __builtin_ia32_expanddf256_mask ((__v4df) __A,
				2885	(__v4df) __W,
				2886	(__mmask8) __U);
				2887	}
				2888
				2889	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2890	_mm256_maskz_expand_pd (__mmask8 __U, __m256d __A) {
				2891	return (__m256d) __builtin_ia32_expanddf256_mask ((__v4df) __A,
				2892	(__v4df)
				2893	_mm256_setzero_pd (),
				2894	(__mmask8) __U);
				2895	}
				2896
				2897	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2898	_mm_mask_expand_epi64 (__m128i __W, __mmask8 __U, __m128i __A) {
				2899	return (__m128i) __builtin_ia32_expanddi128_mask ((__v2di) __A,
				2900	(__v2di) __W,
				2901	(__mmask8) __U);
				2902	}
				2903
				2904	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2905	_mm_maskz_expand_epi64 (__mmask8 __U, __m128i __A) {
				2906	return (__m128i) __builtin_ia32_expanddi128_mask ((__v2di) __A,
				2907	(__v2di)
				2908	_mm_setzero_si128 (),
				2909	(__mmask8) __U);
				2910	}
				2911
				2912	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2913	_mm256_mask_expand_epi64 (__m256i __W, __mmask8 __U, __m256i __A) {
				2914	return (__m256i) __builtin_ia32_expanddi256_mask ((__v4di) __A,
				2915	(__v4di) __W,
				2916	(__mmask8) __U);
				2917	}
				2918
				2919	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2920	_mm256_maskz_expand_epi64 (__mmask8 __U, __m256i __A) {
				2921	return (__m256i) __builtin_ia32_expanddi256_mask ((__v4di) __A,
				2922	(__v4di)
				2923	_mm256_setzero_si256 (),
				2924	(__mmask8) __U);
				2925	}
				2926
				2927	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2928	_mm_mask_expandloadu_pd (__m128d __W, __mmask8 __U, void const *__P) {
				2929	return (__m128d) __builtin_ia32_expandloaddf128_mask ((__v2df *) __P,
				2930	(__v2df) __W,
				2931	(__mmask8)
				2932	__U);
				2933	}
				2934
				2935	static __inline__ __m128d __DEFAULT_FN_ATTRS
				2936	_mm_maskz_expandloadu_pd (__mmask8 __U, void const *__P) {
				2937	return (__m128d) __builtin_ia32_expandloaddf128_mask ((__v2df *) __P,
				2938	(__v2df)
				2939	_mm_setzero_pd (),
				2940	(__mmask8)
				2941	__U);
				2942	}
				2943
				2944	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2945	_mm256_mask_expandloadu_pd (__m256d __W, __mmask8 __U, void const *__P) {
				2946	return (__m256d) __builtin_ia32_expandloaddf256_mask ((__v4df *) __P,
				2947	(__v4df) __W,
				2948	(__mmask8)
				2949	__U);
				2950	}
				2951
				2952	static __inline__ __m256d __DEFAULT_FN_ATTRS
				2953	_mm256_maskz_expandloadu_pd (__mmask8 __U, void const *__P) {
				2954	return (__m256d) __builtin_ia32_expandloaddf256_mask ((__v4df *) __P,
				2955	(__v4df)
				2956	_mm256_setzero_pd (),
				2957	(__mmask8)
				2958	__U);
				2959	}
				2960
				2961	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2962	_mm_mask_expandloadu_epi64 (__m128i __W, __mmask8 __U, void const *__P) {
				2963	return (__m128i) __builtin_ia32_expandloaddi128_mask ((__v2di *) __P,
				2964	(__v2di) __W,
				2965	(__mmask8)
				2966	__U);
				2967	}
				2968
				2969	static __inline__ __m128i __DEFAULT_FN_ATTRS
				2970	_mm_maskz_expandloadu_epi64 (__mmask8 __U, void const *__P) {
				2971	return (__m128i) __builtin_ia32_expandloaddi128_mask ((__v2di *) __P,
				2972	(__v2di)
				2973	_mm_setzero_si128 (),
				2974	(__mmask8)
				2975	__U);
				2976	}
				2977
				2978	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2979	_mm256_mask_expandloadu_epi64 (__m256i __W, __mmask8 __U,
				2980	void const *__P) {
				2981	return (__m256i) __builtin_ia32_expandloaddi256_mask ((__v4di *) __P,
				2982	(__v4di) __W,
				2983	(__mmask8)
				2984	__U);
				2985	}
				2986
				2987	static __inline__ __m256i __DEFAULT_FN_ATTRS
				2988	_mm256_maskz_expandloadu_epi64 (__mmask8 __U, void const *__P) {
				2989	return (__m256i) __builtin_ia32_expandloaddi256_mask ((__v4di *) __P,
				2990	(__v4di)
				2991	_mm256_setzero_si256 (),
				2992	(__mmask8)
				2993	__U);
				2994	}
				2995
				2996	static __inline__ __m128 __DEFAULT_FN_ATTRS
				2997	_mm_mask_expandloadu_ps (__m128 __W, __mmask8 __U, void const *__P) {
				2998	return (__m128) __builtin_ia32_expandloadsf128_mask ((__v4sf *) __P,
				2999	(__v4sf) __W,
				3000	(__mmask8) __U);
				3001	}
				3002
				3003	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3004	_mm_maskz_expandloadu_ps (__mmask8 __U, void const *__P) {
				3005	return (__m128) __builtin_ia32_expandloadsf128_mask ((__v4sf *) __P,
				3006	(__v4sf)
				3007	_mm_setzero_ps (),
				3008	(__mmask8)
				3009	__U);
				3010	}
				3011
				3012	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3013	_mm256_mask_expandloadu_ps (__m256 __W, __mmask8 __U, void const *__P) {
				3014	return (__m256) __builtin_ia32_expandloadsf256_mask ((__v8sf *) __P,
				3015	(__v8sf) __W,
				3016	(__mmask8) __U);
				3017	}
				3018
				3019	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3020	_mm256_maskz_expandloadu_ps (__mmask8 __U, void const *__P) {
				3021	return (__m256) __builtin_ia32_expandloadsf256_mask ((__v8sf *) __P,
				3022	(__v8sf)
				3023	_mm256_setzero_ps (),
				3024	(__mmask8)
				3025	__U);
				3026	}
				3027
				3028	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3029	_mm_mask_expandloadu_epi32 (__m128i __W, __mmask8 __U, void const *__P) {
				3030	return (__m128i) __builtin_ia32_expandloadsi128_mask ((__v4si *) __P,
				3031	(__v4si) __W,
				3032	(__mmask8)
				3033	__U);
				3034	}
				3035
				3036	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3037	_mm_maskz_expandloadu_epi32 (__mmask8 __U, void const *__P) {
				3038	return (__m128i) __builtin_ia32_expandloadsi128_mask ((__v4si *) __P,
				3039	(__v4si)
				3040	_mm_setzero_si128 (),
				3041	(__mmask8) __U);
				3042	}
				3043
				3044	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3045	_mm256_mask_expandloadu_epi32 (__m256i __W, __mmask8 __U,
				3046	void const *__P) {
				3047	return (__m256i) __builtin_ia32_expandloadsi256_mask ((__v8si *) __P,
				3048	(__v8si) __W,
				3049	(__mmask8)
				3050	__U);
				3051	}
				3052
				3053	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3054	_mm256_maskz_expandloadu_epi32 (__mmask8 __U, void const *__P) {
				3055	return (__m256i) __builtin_ia32_expandloadsi256_mask ((__v8si *) __P,
				3056	(__v8si)
				3057	_mm256_setzero_si256 (),
				3058	(__mmask8)
				3059	__U);
				3060	}
				3061
				3062	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3063	_mm_mask_expand_ps (__m128 __W, __mmask8 __U, __m128 __A) {
				3064	return (__m128) __builtin_ia32_expandsf128_mask ((__v4sf) __A,
				3065	(__v4sf) __W,
				3066	(__mmask8) __U);
				3067	}
				3068
				3069	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3070	_mm_maskz_expand_ps (__mmask8 __U, __m128 __A) {
				3071	return (__m128) __builtin_ia32_expandsf128_mask ((__v4sf) __A,
				3072	(__v4sf)
				3073	_mm_setzero_ps (),
				3074	(__mmask8) __U);
				3075	}
				3076
				3077	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3078	_mm256_mask_expand_ps (__m256 __W, __mmask8 __U, __m256 __A) {
				3079	return (__m256) __builtin_ia32_expandsf256_mask ((__v8sf) __A,
				3080	(__v8sf) __W,
				3081	(__mmask8) __U);
				3082	}
				3083
				3084	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3085	_mm256_maskz_expand_ps (__mmask8 __U, __m256 __A) {
				3086	return (__m256) __builtin_ia32_expandsf256_mask ((__v8sf) __A,
				3087	(__v8sf)
				3088	_mm256_setzero_ps (),
				3089	(__mmask8) __U);
				3090	}
				3091
				3092	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3093	_mm_mask_expand_epi32 (__m128i __W, __mmask8 __U, __m128i __A) {
				3094	return (__m128i) __builtin_ia32_expandsi128_mask ((__v4si) __A,
				3095	(__v4si) __W,
				3096	(__mmask8) __U);
				3097	}
				3098
				3099	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3100	_mm_maskz_expand_epi32 (__mmask8 __U, __m128i __A) {
				3101	return (__m128i) __builtin_ia32_expandsi128_mask ((__v4si) __A,
				3102	(__v4si)
				3103	_mm_setzero_si128 (),
				3104	(__mmask8) __U);
				3105	}
				3106
				3107	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3108	_mm256_mask_expand_epi32 (__m256i __W, __mmask8 __U, __m256i __A) {
				3109	return (__m256i) __builtin_ia32_expandsi256_mask ((__v8si) __A,
				3110	(__v8si) __W,
				3111	(__mmask8) __U);
				3112	}
				3113
				3114	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3115	_mm256_maskz_expand_epi32 (__mmask8 __U, __m256i __A) {
				3116	return (__m256i) __builtin_ia32_expandsi256_mask ((__v8si) __A,
				3117	(__v8si)
				3118	_mm256_setzero_si256 (),
				3119	(__mmask8) __U);
				3120	}
				3121
				3122	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3123	_mm_getexp_pd (__m128d __A) {
				3124	return (__m128d) __builtin_ia32_getexppd128_mask ((__v2df) __A,
				3125	(__v2df)
				3126	_mm_setzero_pd (),
				3127	(__mmask8) -1);
				3128	}
				3129
				3130	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3131	_mm_mask_getexp_pd (__m128d __W, __mmask8 __U, __m128d __A) {
				3132	return (__m128d) __builtin_ia32_getexppd128_mask ((__v2df) __A,
				3133	(__v2df) __W,
				3134	(__mmask8) __U);
				3135	}
				3136
				3137	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3138	_mm_maskz_getexp_pd (__mmask8 __U, __m128d __A) {
				3139	return (__m128d) __builtin_ia32_getexppd128_mask ((__v2df) __A,
				3140	(__v2df)
				3141	_mm_setzero_pd (),
				3142	(__mmask8) __U);
				3143	}
				3144
				3145	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3146	_mm256_getexp_pd (__m256d __A) {
				3147	return (__m256d) __builtin_ia32_getexppd256_mask ((__v4df) __A,
				3148	(__v4df)
				3149	_mm256_setzero_pd (),
				3150	(__mmask8) -1);
				3151	}
				3152
				3153	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3154	_mm256_mask_getexp_pd (__m256d __W, __mmask8 __U, __m256d __A) {
				3155	return (__m256d) __builtin_ia32_getexppd256_mask ((__v4df) __A,
				3156	(__v4df) __W,
				3157	(__mmask8) __U);
				3158	}
				3159
				3160	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3161	_mm256_maskz_getexp_pd (__mmask8 __U, __m256d __A) {
				3162	return (__m256d) __builtin_ia32_getexppd256_mask ((__v4df) __A,
				3163	(__v4df)
				3164	_mm256_setzero_pd (),
				3165	(__mmask8) __U);
				3166	}
				3167
				3168	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3169	_mm_getexp_ps (__m128 __A) {
				3170	return (__m128) __builtin_ia32_getexpps128_mask ((__v4sf) __A,
				3171	(__v4sf)
				3172	_mm_setzero_ps (),
				3173	(__mmask8) -1);
				3174	}
				3175
				3176	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3177	_mm_mask_getexp_ps (__m128 __W, __mmask8 __U, __m128 __A) {
				3178	return (__m128) __builtin_ia32_getexpps128_mask ((__v4sf) __A,
				3179	(__v4sf) __W,
				3180	(__mmask8) __U);
				3181	}
				3182
				3183	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3184	_mm_maskz_getexp_ps (__mmask8 __U, __m128 __A) {
				3185	return (__m128) __builtin_ia32_getexpps128_mask ((__v4sf) __A,
				3186	(__v4sf)
				3187	_mm_setzero_ps (),
				3188	(__mmask8) __U);
				3189	}
				3190
				3191	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3192	_mm256_getexp_ps (__m256 __A) {
				3193	return (__m256) __builtin_ia32_getexpps256_mask ((__v8sf) __A,
				3194	(__v8sf)
				3195	_mm256_setzero_ps (),
				3196	(__mmask8) -1);
				3197	}
				3198
				3199	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3200	_mm256_mask_getexp_ps (__m256 __W, __mmask8 __U, __m256 __A) {
				3201	return (__m256) __builtin_ia32_getexpps256_mask ((__v8sf) __A,
				3202	(__v8sf) __W,
				3203	(__mmask8) __U);
				3204	}
				3205
				3206	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3207	_mm256_maskz_getexp_ps (__mmask8 __U, __m256 __A) {
				3208	return (__m256) __builtin_ia32_getexpps256_mask ((__v8sf) __A,
				3209	(__v8sf)
				3210	_mm256_setzero_ps (),
				3211	(__mmask8) __U);
				3212	}
				3213
				3214	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3215	_mm_mask_max_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				3216	return (__m128d) __builtin_ia32_maxpd_mask ((__v2df) __A,
				3217	(__v2df) __B,
				3218	(__v2df) __W,
				3219	(__mmask8) __U);
				3220	}
				3221
				3222	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3223	_mm_maskz_max_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				3224	return (__m128d) __builtin_ia32_maxpd_mask ((__v2df) __A,
				3225	(__v2df) __B,
				3226	(__v2df)
				3227	_mm_setzero_pd (),
				3228	(__mmask8) __U);
				3229	}
				3230
				3231	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3232	_mm256_mask_max_pd (__m256d __W, __mmask8 __U, __m256d __A,
				3233	__m256d __B) {
				3234	return (__m256d) __builtin_ia32_maxpd256_mask ((__v4df) __A,
				3235	(__v4df) __B,
				3236	(__v4df) __W,
				3237	(__mmask8) __U);
				3238	}
				3239
				3240	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3241	_mm256_maskz_max_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				3242	return (__m256d) __builtin_ia32_maxpd256_mask ((__v4df) __A,
				3243	(__v4df) __B,
				3244	(__v4df)
				3245	_mm256_setzero_pd (),
				3246	(__mmask8) __U);
				3247	}
				3248
				3249	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3250	_mm_mask_max_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
				3251	return (__m128) __builtin_ia32_maxps_mask ((__v4sf) __A,
				3252	(__v4sf) __B,
				3253	(__v4sf) __W,
				3254	(__mmask8) __U);
				3255	}
				3256
				3257	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3258	_mm_maskz_max_ps (__mmask8 __U, __m128 __A, __m128 __B) {
				3259	return (__m128) __builtin_ia32_maxps_mask ((__v4sf) __A,
				3260	(__v4sf) __B,
				3261	(__v4sf)
				3262	_mm_setzero_ps (),
				3263	(__mmask8) __U);
				3264	}
				3265
				3266	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3267	_mm256_mask_max_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
				3268	return (__m256) __builtin_ia32_maxps256_mask ((__v8sf) __A,
				3269	(__v8sf) __B,
				3270	(__v8sf) __W,
				3271	(__mmask8) __U);
				3272	}
				3273
				3274	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3275	_mm256_maskz_max_ps (__mmask8 __U, __m256 __A, __m256 __B) {
				3276	return (__m256) __builtin_ia32_maxps256_mask ((__v8sf) __A,
				3277	(__v8sf) __B,
				3278	(__v8sf)
				3279	_mm256_setzero_ps (),
				3280	(__mmask8) __U);
				3281	}
				3282
				3283	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3284	_mm_mask_min_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				3285	return (__m128d) __builtin_ia32_minpd_mask ((__v2df) __A,
				3286	(__v2df) __B,
				3287	(__v2df) __W,
				3288	(__mmask8) __U);
				3289	}
				3290
				3291	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3292	_mm_maskz_min_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				3293	return (__m128d) __builtin_ia32_minpd_mask ((__v2df) __A,
				3294	(__v2df) __B,
				3295	(__v2df)
				3296	_mm_setzero_pd (),
				3297	(__mmask8) __U);
				3298	}
				3299
				3300	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3301	_mm256_mask_min_pd (__m256d __W, __mmask8 __U, __m256d __A,
				3302	__m256d __B) {
				3303	return (__m256d) __builtin_ia32_minpd256_mask ((__v4df) __A,
				3304	(__v4df) __B,
				3305	(__v4df) __W,
				3306	(__mmask8) __U);
				3307	}
				3308
				3309	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3310	_mm256_maskz_min_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				3311	return (__m256d) __builtin_ia32_minpd256_mask ((__v4df) __A,
				3312	(__v4df) __B,
				3313	(__v4df)
				3314	_mm256_setzero_pd (),
				3315	(__mmask8) __U);
				3316	}
				3317
				3318	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3319	_mm_mask_min_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
				3320	return (__m128) __builtin_ia32_minps_mask ((__v4sf) __A,
				3321	(__v4sf) __B,
				3322	(__v4sf) __W,
				3323	(__mmask8) __U);
				3324	}
				3325
				3326	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3327	_mm_maskz_min_ps (__mmask8 __U, __m128 __A, __m128 __B) {
				3328	return (__m128) __builtin_ia32_minps_mask ((__v4sf) __A,
				3329	(__v4sf) __B,
				3330	(__v4sf)
				3331	_mm_setzero_ps (),
				3332	(__mmask8) __U);
				3333	}
				3334
				3335	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3336	_mm256_mask_min_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
				3337	return (__m256) __builtin_ia32_minps256_mask ((__v8sf) __A,
				3338	(__v8sf) __B,
				3339	(__v8sf) __W,
				3340	(__mmask8) __U);
				3341	}
				3342
				3343	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3344	_mm256_maskz_min_ps (__mmask8 __U, __m256 __A, __m256 __B) {
				3345	return (__m256) __builtin_ia32_minps256_mask ((__v8sf) __A,
				3346	(__v8sf) __B,
				3347	(__v8sf)
				3348	_mm256_setzero_ps (),
				3349	(__mmask8) __U);
				3350	}
				3351
				3352	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3353	_mm_mask_mul_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				3354	return (__m128d) __builtin_ia32_mulpd_mask ((__v2df) __A,
				3355	(__v2df) __B,
				3356	(__v2df) __W,
				3357	(__mmask8) __U);
				3358	}
				3359
				3360	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3361	_mm_maskz_mul_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				3362	return (__m128d) __builtin_ia32_mulpd_mask ((__v2df) __A,
				3363	(__v2df) __B,
				3364	(__v2df)
				3365	_mm_setzero_pd (),
				3366	(__mmask8) __U);
				3367	}
				3368
				3369	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3370	_mm256_mask_mul_pd (__m256d __W, __mmask8 __U, __m256d __A,
				3371	__m256d __B) {
				3372	return (__m256d) __builtin_ia32_mulpd256_mask ((__v4df) __A,
				3373	(__v4df) __B,
				3374	(__v4df) __W,
				3375	(__mmask8) __U);
				3376	}
				3377
				3378	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3379	_mm256_maskz_mul_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				3380	return (__m256d) __builtin_ia32_mulpd256_mask ((__v4df) __A,
				3381	(__v4df) __B,
				3382	(__v4df)
				3383	_mm256_setzero_pd (),
				3384	(__mmask8) __U);
				3385	}
				3386
				3387	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3388	_mm_mask_mul_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
				3389	return (__m128) __builtin_ia32_mulps_mask ((__v4sf) __A,
				3390	(__v4sf) __B,
				3391	(__v4sf) __W,
				3392	(__mmask8) __U);
				3393	}
				3394
				3395	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3396	_mm_maskz_mul_ps (__mmask8 __U, __m128 __A, __m128 __B) {
				3397	return (__m128) __builtin_ia32_mulps_mask ((__v4sf) __A,
				3398	(__v4sf) __B,
				3399	(__v4sf)
				3400	_mm_setzero_ps (),
				3401	(__mmask8) __U);
				3402	}
				3403
				3404	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3405	_mm256_mask_mul_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
				3406	return (__m256) __builtin_ia32_mulps256_mask ((__v8sf) __A,
				3407	(__v8sf) __B,
				3408	(__v8sf) __W,
				3409	(__mmask8) __U);
				3410	}
				3411
				3412	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3413	_mm256_maskz_mul_ps (__mmask8 __U, __m256 __A, __m256 __B) {
				3414	return (__m256) __builtin_ia32_mulps256_mask ((__v8sf) __A,
				3415	(__v8sf) __B,
				3416	(__v8sf)
				3417	_mm256_setzero_ps (),
				3418	(__mmask8) __U);
				3419	}
				3420
				3421	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3422	_mm_mask_abs_epi32 (__m128i __W, __mmask8 __U, __m128i __A) {
				3423	return (__m128i) __builtin_ia32_pabsd128_mask ((__v4si) __A,
				3424	(__v4si) __W,
				3425	(__mmask8) __U);
				3426	}
				3427
				3428	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3429	_mm_maskz_abs_epi32 (__mmask8 __U, __m128i __A) {
				3430	return (__m128i) __builtin_ia32_pabsd128_mask ((__v4si) __A,
				3431	(__v4si)
				3432	_mm_setzero_si128 (),
				3433	(__mmask8) __U);
				3434	}
				3435
				3436	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3437	_mm256_mask_abs_epi32 (__m256i __W, __mmask8 __U, __m256i __A) {
				3438	return (__m256i) __builtin_ia32_pabsd256_mask ((__v8si) __A,
				3439	(__v8si) __W,
				3440	(__mmask8) __U);
				3441	}
				3442
				3443	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3444	_mm256_maskz_abs_epi32 (__mmask8 __U, __m256i __A) {
				3445	return (__m256i) __builtin_ia32_pabsd256_mask ((__v8si) __A,
				3446	(__v8si)
				3447	_mm256_setzero_si256 (),
				3448	(__mmask8) __U);
				3449	}
				3450
				3451	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3452	_mm_abs_epi64 (__m128i __A) {
				3453	return (__m128i) __builtin_ia32_pabsq128_mask ((__v2di) __A,
				3454	(__v2di)
				3455	_mm_setzero_si128 (),
				3456	(__mmask8) -1);
				3457	}
				3458
				3459	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3460	_mm_mask_abs_epi64 (__m128i __W, __mmask8 __U, __m128i __A) {
				3461	return (__m128i) __builtin_ia32_pabsq128_mask ((__v2di) __A,
				3462	(__v2di) __W,
				3463	(__mmask8) __U);
				3464	}
				3465
				3466	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3467	_mm_maskz_abs_epi64 (__mmask8 __U, __m128i __A) {
				3468	return (__m128i) __builtin_ia32_pabsq128_mask ((__v2di) __A,
				3469	(__v2di)
				3470	_mm_setzero_si128 (),
				3471	(__mmask8) __U);
				3472	}
				3473
				3474	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3475	_mm256_abs_epi64 (__m256i __A) {
				3476	return (__m256i) __builtin_ia32_pabsq256_mask ((__v4di) __A,
				3477	(__v4di)
				3478	_mm256_setzero_si256 (),
				3479	(__mmask8) -1);
				3480	}
				3481
				3482	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3483	_mm256_mask_abs_epi64 (__m256i __W, __mmask8 __U, __m256i __A) {
				3484	return (__m256i) __builtin_ia32_pabsq256_mask ((__v4di) __A,
				3485	(__v4di) __W,
				3486	(__mmask8) __U);
				3487	}
				3488
				3489	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3490	_mm256_maskz_abs_epi64 (__mmask8 __U, __m256i __A) {
				3491	return (__m256i) __builtin_ia32_pabsq256_mask ((__v4di) __A,
				3492	(__v4di)
				3493	_mm256_setzero_si256 (),
				3494	(__mmask8) __U);
				3495	}
				3496
Asaf Badouh	b7cf71b	2015-07-28 11:14:09 +0000	[diff] [blame]	3497	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3498	_mm_maskz_max_epi32 (__mmask8 __M, __m128i __A, __m128i __B) {
				3499	return (__m128i) __builtin_ia32_pmaxsd128_mask ((__v4si) __A,
				3500	(__v4si) __B,
				3501	(__v4si)
				3502	_mm_setzero_si128 (),
				3503	__M);
				3504	}
				3505
				3506	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3507	_mm_mask_max_epi32 (__m128i __W, __mmask8 __M, __m128i __A,
				3508	__m128i __B) {
				3509	return (__m128i) __builtin_ia32_pmaxsd128_mask ((__v4si) __A,
				3510	(__v4si) __B,
				3511	(__v4si) __W, __M);
				3512	}
				3513
				3514	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3515	_mm256_maskz_max_epi32 (__mmask8 __M, __m256i __A, __m256i __B) {
				3516	return (__m256i) __builtin_ia32_pmaxsd256_mask ((__v8si) __A,
				3517	(__v8si) __B,
				3518	(__v8si)
				3519	_mm256_setzero_si256 (),
				3520	__M);
				3521	}
				3522
				3523	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3524	_mm256_mask_max_epi32 (__m256i __W, __mmask8 __M, __m256i __A,
				3525	__m256i __B) {
				3526	return (__m256i) __builtin_ia32_pmaxsd256_mask ((__v8si) __A,
				3527	(__v8si) __B,
				3528	(__v8si) __W, __M);
				3529	}
				3530
				3531	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3532	_mm_maskz_max_epi64 (__mmask8 __M, __m128i __A, __m128i __B) {
				3533	return (__m128i) __builtin_ia32_pmaxsq128_mask ((__v2di) __A,
				3534	(__v2di) __B,
				3535	(__v2di)
				3536	_mm_setzero_si128 (),
				3537	__M);
				3538	}
				3539
				3540	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3541	_mm_mask_max_epi64 (__m128i __W, __mmask8 __M, __m128i __A,
				3542	__m128i __B) {
				3543	return (__m128i) __builtin_ia32_pmaxsq128_mask ((__v2di) __A,
				3544	(__v2di) __B,
				3545	(__v2di) __W, __M);
				3546	}
				3547
				3548	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3549	_mm_max_epi64 (__m128i __A, __m128i __B) {
				3550	return (__m128i) __builtin_ia32_pmaxsq128_mask ((__v2di) __A,
				3551	(__v2di) __B,
				3552	(__v2di)
				3553	_mm_setzero_si128 (),
				3554	(__mmask8) -1);
				3555	}
				3556
				3557	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3558	_mm256_maskz_max_epi64 (__mmask8 __M, __m256i __A, __m256i __B) {
				3559	return (__m256i) __builtin_ia32_pmaxsq256_mask ((__v4di) __A,
				3560	(__v4di) __B,
				3561	(__v4di)
				3562	_mm256_setzero_si256 (),
				3563	__M);
				3564	}
				3565
				3566	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3567	_mm256_mask_max_epi64 (__m256i __W, __mmask8 __M, __m256i __A,
				3568	__m256i __B) {
				3569	return (__m256i) __builtin_ia32_pmaxsq256_mask ((__v4di) __A,
				3570	(__v4di) __B,
				3571	(__v4di) __W, __M);
				3572	}
				3573
				3574	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3575	_mm256_max_epi64 (__m256i __A, __m256i __B) {
				3576	return (__m256i) __builtin_ia32_pmaxsq256_mask ((__v4di) __A,
				3577	(__v4di) __B,
				3578	(__v4di)
				3579	_mm256_setzero_si256 (),
				3580	(__mmask8) -1);
				3581	}
				3582
				3583	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3584	_mm_maskz_max_epu32 (__mmask8 __M, __m128i __A, __m128i __B) {
				3585	return (__m128i) __builtin_ia32_pmaxud128_mask ((__v4si) __A,
				3586	(__v4si) __B,
				3587	(__v4si)
				3588	_mm_setzero_si128 (),
				3589	__M);
				3590	}
				3591
				3592	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3593	_mm_mask_max_epu32 (__m128i __W, __mmask8 __M, __m128i __A,
				3594	__m128i __B) {
				3595	return (__m128i) __builtin_ia32_pmaxud128_mask ((__v4si) __A,
				3596	(__v4si) __B,
				3597	(__v4si) __W, __M);
				3598	}
				3599
				3600	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3601	_mm256_maskz_max_epu32 (__mmask8 __M, __m256i __A, __m256i __B) {
				3602	return (__m256i) __builtin_ia32_pmaxud256_mask ((__v8si) __A,
				3603	(__v8si) __B,
				3604	(__v8si)
				3605	_mm256_setzero_si256 (),
				3606	__M);
				3607	}
				3608
				3609	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3610	_mm256_mask_max_epu32 (__m256i __W, __mmask8 __M, __m256i __A,
				3611	__m256i __B) {
				3612	return (__m256i) __builtin_ia32_pmaxud256_mask ((__v8si) __A,
				3613	(__v8si) __B,
				3614	(__v8si) __W, __M);
				3615	}
				3616
				3617	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3618	_mm_maskz_max_epu64 (__mmask8 __M, __m128i __A, __m128i __B) {
				3619	return (__m128i) __builtin_ia32_pmaxuq128_mask ((__v2di) __A,
				3620	(__v2di) __B,
				3621	(__v2di)
				3622	_mm_setzero_si128 (),
				3623	__M);
				3624	}
				3625
				3626	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3627	_mm_max_epu64 (__m128i __A, __m128i __B) {
				3628	return (__m128i) __builtin_ia32_pmaxuq128_mask ((__v2di) __A,
				3629	(__v2di) __B,
				3630	(__v2di)
				3631	_mm_setzero_si128 (),
				3632	(__mmask8) -1);
				3633	}
				3634
				3635	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3636	_mm_mask_max_epu64 (__m128i __W, __mmask8 __M, __m128i __A,
				3637	__m128i __B) {
				3638	return (__m128i) __builtin_ia32_pmaxuq128_mask ((__v2di) __A,
				3639	(__v2di) __B,
				3640	(__v2di) __W, __M);
				3641	}
				3642
				3643	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3644	_mm256_maskz_max_epu64 (__mmask8 __M, __m256i __A, __m256i __B) {
				3645	return (__m256i) __builtin_ia32_pmaxuq256_mask ((__v4di) __A,
				3646	(__v4di) __B,
				3647	(__v4di)
				3648	_mm256_setzero_si256 (),
				3649	__M);
				3650	}
				3651
				3652	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3653	_mm256_max_epu64 (__m256i __A, __m256i __B) {
				3654	return (__m256i) __builtin_ia32_pmaxuq256_mask ((__v4di) __A,
				3655	(__v4di) __B,
				3656	(__v4di)
				3657	_mm256_setzero_si256 (),
				3658	(__mmask8) -1);
				3659	}
				3660
				3661	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3662	_mm256_mask_max_epu64 (__m256i __W, __mmask8 __M, __m256i __A,
				3663	__m256i __B) {
				3664	return (__m256i) __builtin_ia32_pmaxuq256_mask ((__v4di) __A,
				3665	(__v4di) __B,
				3666	(__v4di) __W, __M);
				3667	}
				3668
				3669	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3670	_mm_maskz_min_epi32 (__mmask8 __M, __m128i __A, __m128i __B) {
				3671	return (__m128i) __builtin_ia32_pminsd128_mask ((__v4si) __A,
				3672	(__v4si) __B,
				3673	(__v4si)
				3674	_mm_setzero_si128 (),
				3675	__M);
				3676	}
				3677
				3678	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3679	_mm_mask_min_epi32 (__m128i __W, __mmask8 __M, __m128i __A,
				3680	__m128i __B) {
				3681	return (__m128i) __builtin_ia32_pminsd128_mask ((__v4si) __A,
				3682	(__v4si) __B,
				3683	(__v4si) __W, __M);
				3684	}
				3685
				3686	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3687	_mm256_maskz_min_epi32 (__mmask8 __M, __m256i __A, __m256i __B) {
				3688	return (__m256i) __builtin_ia32_pminsd256_mask ((__v8si) __A,
				3689	(__v8si) __B,
				3690	(__v8si)
				3691	_mm256_setzero_si256 (),
				3692	__M);
				3693	}
				3694
				3695	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3696	_mm256_mask_min_epi32 (__m256i __W, __mmask8 __M, __m256i __A,
				3697	__m256i __B) {
				3698	return (__m256i) __builtin_ia32_pminsd256_mask ((__v8si) __A,
				3699	(__v8si) __B,
				3700	(__v8si) __W, __M);
				3701	}
				3702
				3703	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3704	_mm_min_epi64 (__m128i __A, __m128i __B) {
				3705	return (__m128i) __builtin_ia32_pminsq128_mask ((__v2di) __A,
				3706	(__v2di) __B,
				3707	(__v2di)
				3708	_mm_setzero_si128 (),
				3709	(__mmask8) -1);
				3710	}
				3711
				3712	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3713	_mm_mask_min_epi64 (__m128i __W, __mmask8 __M, __m128i __A,
				3714	__m128i __B) {
				3715	return (__m128i) __builtin_ia32_pminsq128_mask ((__v2di) __A,
				3716	(__v2di) __B,
				3717	(__v2di) __W, __M);
				3718	}
				3719
				3720	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3721	_mm_maskz_min_epi64 (__mmask8 __M, __m128i __A, __m128i __B) {
				3722	return (__m128i) __builtin_ia32_pminsq128_mask ((__v2di) __A,
				3723	(__v2di) __B,
				3724	(__v2di)
				3725	_mm_setzero_si128 (),
				3726	__M);
				3727	}
				3728
				3729	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3730	_mm256_min_epi64 (__m256i __A, __m256i __B) {
				3731	return (__m256i) __builtin_ia32_pminsq256_mask ((__v4di) __A,
				3732	(__v4di) __B,
				3733	(__v4di)
				3734	_mm256_setzero_si256 (),
				3735	(__mmask8) -1);
				3736	}
				3737
				3738	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3739	_mm256_mask_min_epi64 (__m256i __W, __mmask8 __M, __m256i __A,
				3740	__m256i __B) {
				3741	return (__m256i) __builtin_ia32_pminsq256_mask ((__v4di) __A,
				3742	(__v4di) __B,
				3743	(__v4di) __W, __M);
				3744	}
				3745
				3746	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3747	_mm256_maskz_min_epi64 (__mmask8 __M, __m256i __A, __m256i __B) {
				3748	return (__m256i) __builtin_ia32_pminsq256_mask ((__v4di) __A,
				3749	(__v4di) __B,
				3750	(__v4di)
				3751	_mm256_setzero_si256 (),
				3752	__M);
				3753	}
				3754
				3755	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3756	_mm_maskz_min_epu32 (__mmask8 __M, __m128i __A, __m128i __B) {
				3757	return (__m128i) __builtin_ia32_pminud128_mask ((__v4si) __A,
				3758	(__v4si) __B,
				3759	(__v4si)
				3760	_mm_setzero_si128 (),
				3761	__M);
				3762	}
				3763
				3764	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3765	_mm_mask_min_epu32 (__m128i __W, __mmask8 __M, __m128i __A,
				3766	__m128i __B) {
				3767	return (__m128i) __builtin_ia32_pminud128_mask ((__v4si) __A,
				3768	(__v4si) __B,
				3769	(__v4si) __W, __M);
				3770	}
				3771
				3772	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3773	_mm256_maskz_min_epu32 (__mmask8 __M, __m256i __A, __m256i __B) {
				3774	return (__m256i) __builtin_ia32_pminud256_mask ((__v8si) __A,
				3775	(__v8si) __B,
				3776	(__v8si)
				3777	_mm256_setzero_si256 (),
				3778	__M);
				3779	}
				3780
				3781	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3782	_mm256_mask_min_epu32 (__m256i __W, __mmask8 __M, __m256i __A,
				3783	__m256i __B) {
				3784	return (__m256i) __builtin_ia32_pminud256_mask ((__v8si) __A,
				3785	(__v8si) __B,
				3786	(__v8si) __W, __M);
				3787	}
				3788
				3789	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3790	_mm_min_epu64 (__m128i __A, __m128i __B) {
				3791	return (__m128i) __builtin_ia32_pminuq128_mask ((__v2di) __A,
				3792	(__v2di) __B,
				3793	(__v2di)
				3794	_mm_setzero_si128 (),
				3795	(__mmask8) -1);
				3796	}
				3797
				3798	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3799	_mm_mask_min_epu64 (__m128i __W, __mmask8 __M, __m128i __A,
				3800	__m128i __B) {
				3801	return (__m128i) __builtin_ia32_pminuq128_mask ((__v2di) __A,
				3802	(__v2di) __B,
				3803	(__v2di) __W, __M);
				3804	}
				3805
				3806	static __inline__ __m128i __DEFAULT_FN_ATTRS
				3807	_mm_maskz_min_epu64 (__mmask8 __M, __m128i __A, __m128i __B) {
				3808	return (__m128i) __builtin_ia32_pminuq128_mask ((__v2di) __A,
				3809	(__v2di) __B,
				3810	(__v2di)
				3811	_mm_setzero_si128 (),
				3812	__M);
				3813	}
				3814
				3815	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3816	_mm256_min_epu64 (__m256i __A, __m256i __B) {
				3817	return (__m256i) __builtin_ia32_pminuq256_mask ((__v4di) __A,
				3818	(__v4di) __B,
				3819	(__v4di)
				3820	_mm256_setzero_si256 (),
				3821	(__mmask8) -1);
				3822	}
				3823
				3824	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3825	_mm256_mask_min_epu64 (__m256i __W, __mmask8 __M, __m256i __A,
				3826	__m256i __B) {
				3827	return (__m256i) __builtin_ia32_pminuq256_mask ((__v4di) __A,
				3828	(__v4di) __B,
				3829	(__v4di) __W, __M);
				3830	}
				3831
				3832	static __inline__ __m256i __DEFAULT_FN_ATTRS
				3833	_mm256_maskz_min_epu64 (__mmask8 __M, __m256i __A, __m256i __B) {
				3834	return (__m256i) __builtin_ia32_pminuq256_mask ((__v4di) __A,
				3835	(__v4di) __B,
				3836	(__v4di)
				3837	_mm256_setzero_si256 (),
				3838	__M);
				3839	}
				3840
				3841	#define _mm_roundscale_pd(__A, __imm) __extension__ ({ \
				3842	(__m128d) __builtin_ia32_rndscalepd_128_mask ((__v2df) __A, \
				3843	__imm, (__v2df) _mm_setzero_pd (), (__mmask8) -1); })
				3844
				3845
				3846	#define _mm_mask_roundscale_pd(__W, __U, __A, __imm) __extension__ ({ \
				3847	(__m128d) __builtin_ia32_rndscalepd_128_mask ((__v2df) __A, __imm, \
				3848	(__v2df) __W, (__mmask8) __U); })
				3849
				3850
				3851	#define _mm_maskz_roundscale_pd(__U, __A, __imm) __extension__ ({ \
				3852	(__m128d) __builtin_ia32_rndscalepd_128_mask ((__v2df) __A, __imm, \
				3853	(__v2df) _mm_setzero_pd (), (__mmask8) __U); })
				3854
				3855
				3856	#define _mm256_roundscale_pd(__A, __imm) __extension__ ({ \
				3857	(__m256d) __builtin_ia32_rndscalepd_256_mask ((__v4df) __A, __imm, \
				3858	(__v4df) _mm256_setzero_pd (), (__mmask8) -1); })
				3859
				3860
				3861	#define _mm256_mask_roundscale_pd(__W, __U, __A, __imm) __extension__ ({ \
				3862	(__m256d) __builtin_ia32_rndscalepd_256_mask ((__v4df) __A, __imm, \
				3863	(__v4df) __W, (__mmask8) __U); })
				3864
				3865
				3866	#define _mm256_maskz_roundscale_pd(__U, __A, __imm) __extension__ ({ \
				3867	(__m256d) __builtin_ia32_rndscalepd_256_mask ((__v4df) __A, __imm, \
				3868	(__v4df) _mm256_setzero_pd(), (__mmask8) __U); })
				3869
				3870	#define _mm_roundscale_ps(__A, __imm) __extension__ ({ \
				3871	(__m128) __builtin_ia32_rndscaleps_128_mask ((__v4sf) __A, __imm, \
				3872	(__v4sf) _mm_setzero_ps(), (__mmask8) -1); })
				3873
				3874
				3875	#define _mm_mask_roundscale_ps(__W, __U, __A, __imm) __extension__ ({ \
				3876	(__m128) __builtin_ia32_rndscaleps_128_mask ((__v4sf) __A, __imm, \
				3877	(__v4sf) __W, (__mmask8) __U); })
				3878
				3879
				3880	#define _mm_maskz_roundscale_ps(__U, __A, __imm) __extension__ ({ \
				3881	(__m128) __builtin_ia32_rndscaleps_128_mask ((__v4sf) __A, __imm, \
				3882	(__v4sf) _mm_setzero_ps(), (__mmask8) __U); })
				3883
				3884	#define _mm256_roundscale_ps(__A, __imm) __extension__ ({ \
				3885	(__m256) __builtin_ia32_rndscaleps_256_mask ((__v8sf) __A,__imm, \
				3886	(__v8sf) _mm256_setzero_ps(), (__mmask8) -1); })
				3887
				3888	#define _mm256_mask_roundscale_ps(__W, __U, __A,__imm) __extension__ ({ \
				3889	(__m256) __builtin_ia32_rndscaleps_256_mask ((__v8sf) __A, __imm, \
				3890	(__v8sf) __W, (__mmask8) __U); })
				3891
				3892
				3893	#define _mm256_maskz_roundscale_ps(__U, __A, __imm) __extension__ ({ \
				3894	(__m256) __builtin_ia32_rndscaleps_256_mask ((__v8sf) __A, __imm, \
				3895	(__v8sf) _mm256_setzero_ps(), (__mmask8) __U); })
				3896
				3897	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3898	_mm_scalef_pd (__m128d __A, __m128d __B) {
				3899	return (__m128d) __builtin_ia32_scalefpd128_mask ((__v2df) __A,
				3900	(__v2df) __B,
				3901	(__v2df)
				3902	_mm_setzero_pd (),
				3903	(__mmask8) -1);
				3904	}
				3905
				3906	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3907	_mm_mask_scalef_pd (__m128d __W, __mmask8 __U, __m128d __A,
				3908	__m128d __B) {
				3909	return (__m128d) __builtin_ia32_scalefpd128_mask ((__v2df) __A,
				3910	(__v2df) __B,
				3911	(__v2df) __W,
				3912	(__mmask8) __U);
				3913	}
				3914
				3915	static __inline__ __m128d __DEFAULT_FN_ATTRS
				3916	_mm_maskz_scalef_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				3917	return (__m128d) __builtin_ia32_scalefpd128_mask ((__v2df) __A,
				3918	(__v2df) __B,
				3919	(__v2df)
				3920	_mm_setzero_pd (),
				3921	(__mmask8) __U);
				3922	}
				3923
				3924	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3925	_mm256_scalef_pd (__m256d __A, __m256d __B) {
				3926	return (__m256d) __builtin_ia32_scalefpd256_mask ((__v4df) __A,
				3927	(__v4df) __B,
				3928	(__v4df)
				3929	_mm256_setzero_pd (),
				3930	(__mmask8) -1);
				3931	}
				3932
				3933	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3934	_mm256_mask_scalef_pd (__m256d __W, __mmask8 __U, __m256d __A,
				3935	__m256d __B) {
				3936	return (__m256d) __builtin_ia32_scalefpd256_mask ((__v4df) __A,
				3937	(__v4df) __B,
				3938	(__v4df) __W,
				3939	(__mmask8) __U);
				3940	}
				3941
				3942	static __inline__ __m256d __DEFAULT_FN_ATTRS
				3943	_mm256_maskz_scalef_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				3944	return (__m256d) __builtin_ia32_scalefpd256_mask ((__v4df) __A,
				3945	(__v4df) __B,
				3946	(__v4df)
				3947	_mm256_setzero_pd (),
				3948	(__mmask8) __U);
				3949	}
				3950
				3951	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3952	_mm_scalef_ps (__m128 __A, __m128 __B) {
				3953	return (__m128) __builtin_ia32_scalefps128_mask ((__v4sf) __A,
				3954	(__v4sf) __B,
				3955	(__v4sf)
				3956	_mm_setzero_ps (),
				3957	(__mmask8) -1);
				3958	}
				3959
				3960	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3961	_mm_mask_scalef_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
				3962	return (__m128) __builtin_ia32_scalefps128_mask ((__v4sf) __A,
				3963	(__v4sf) __B,
				3964	(__v4sf) __W,
				3965	(__mmask8) __U);
				3966	}
				3967
				3968	static __inline__ __m128 __DEFAULT_FN_ATTRS
				3969	_mm_maskz_scalef_ps (__mmask8 __U, __m128 __A, __m128 __B) {
				3970	return (__m128) __builtin_ia32_scalefps128_mask ((__v4sf) __A,
				3971	(__v4sf) __B,
				3972	(__v4sf)
				3973	_mm_setzero_ps (),
				3974	(__mmask8) __U);
				3975	}
				3976
				3977	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3978	_mm256_scalef_ps (__m256 __A, __m256 __B) {
				3979	return (__m256) __builtin_ia32_scalefps256_mask ((__v8sf) __A,
				3980	(__v8sf) __B,
				3981	(__v8sf)
				3982	_mm256_setzero_ps (),
				3983	(__mmask8) -1);
				3984	}
				3985
				3986	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3987	_mm256_mask_scalef_ps (__m256 __W, __mmask8 __U, __m256 __A,
				3988	__m256 __B) {
				3989	return (__m256) __builtin_ia32_scalefps256_mask ((__v8sf) __A,
				3990	(__v8sf) __B,
				3991	(__v8sf) __W,
				3992	(__mmask8) __U);
				3993	}
				3994
				3995	static __inline__ __m256 __DEFAULT_FN_ATTRS
				3996	_mm256_maskz_scalef_ps (__mmask8 __U, __m256 __A, __m256 __B) {
				3997	return (__m256) __builtin_ia32_scalefps256_mask ((__v8sf) __A,
				3998	(__v8sf) __B,
				3999	(__v8sf)
				4000	_mm256_setzero_ps (),
				4001	(__mmask8) __U);
				4002	}
				4003
				4004	#define _mm_i64scatter_pd(__addr,__index, __v1, __scale) __extension__ ({ \
				4005	__builtin_ia32_scatterdiv2df(__addr, (__mmask8) 0xFF, (__v2di) __index, \
				4006	(__v2df) __v1, __scale); })
				4007
				4008	#define _mm_mask_i64scatter_pd(__addr, __mask, __index, __v1, \
				4009	__scale) __extension__ ({ \
				4010	__builtin_ia32_scatterdiv2df (__addr, __mask, (__v2di) __index, \
				4011	(__v2df) __v1, __scale); })
				4012
				4013
				4014	#define _mm_i64scatter_epi64(__addr, __index, __v1, __scale) __extension__ ({ \
				4015	__builtin_ia32_scatterdiv2di (__addr, (__mmask8) 0xFF, \
				4016	(__v2di) __index, (__v2di) __v1, __scale); })
				4017
				4018	#define _mm_mask_i64scatter_epi64(__addr, __mask, __index, __v1,\
				4019	__scale) __extension__ ({ \
				4020	__builtin_ia32_scatterdiv2di (__addr, __mask, (__v2di) __index,\
				4021	(__v2di) __v1, __scale); })
				4022
				4023	#define _mm256_i64scatter_pd(__addr, __index, __v1, __scale) __extension__ ({ \
				4024	__builtin_ia32_scatterdiv4df (__addr, (__mmask8) 0xFF,\
				4025	(__v4di) __index, (__v4df) __v1, __scale); })
				4026
				4027	#define _mm256_mask_i64scatter_pd(__addr, __mask, __index, __v1,\
				4028	__scale) __extension__ ({ \
				4029	__builtin_ia32_scatterdiv4df (__addr, __mask, (__v4di) __index,\
				4030	(__v4df) __v1, __scale); })
				4031
				4032	#define _mm256_i64scatter_epi64(__addr, __index, __v1, __scale) __extension__ ({ \
				4033	__builtin_ia32_scatterdiv4di (__addr, (__mmask8) 0xFF, (__v4di) __index,\
				4034	(__v4di) __v1, __scale); })
				4035
				4036	#define _mm256_mask_i64scatter_epi64(__addr, __mask, __index, __v1,\
				4037	__scale) __extension__ ({ \
				4038	__builtin_ia32_scatterdiv4di (__addr, __mask, (__v4di) __index,\
				4039	(__v4di) __v1, __scale); })
				4040
				4041	#define _mm_i64scatter_ps(__addr, __index, __v1, __scale) __extension__ ({ \
				4042	__builtin_ia32_scatterdiv4sf (__addr, (__mmask8) 0xFF,\
				4043	(__v2di) __index, (__v4sf) __v1, __scale); })
				4044
				4045	#define _mm_mask_i64scatter_ps(__addr, __mask, __index, __v1, \
				4046	__scale) __extension__ ({ \
				4047	__builtin_ia32_scatterdiv4sf (__addr, __mask, (__v2di) __index,\
				4048	(__v4sf) __v1, __scale); })
				4049
				4050	#define _mm_i64scatter_epi32(__addr, __index, __v1, \
				4051	__scale) __extension__ ({ \
				4052	__builtin_ia32_scatterdiv4si (__addr, (__mmask8) 0xFF,\
				4053	(__v2di) __index, (__v4si) __v1, __scale); })
				4054
				4055	#define _mm_mask_i64scatter_epi32(__addr, __mask, __index, __v1,\
				4056	__scale) __extension__ ({ \
				4057	__builtin_ia32_scatterdiv4si (__addr, __mask, (__v2di) __index,\
				4058	(__v4si) __v1, __scale); })
				4059
				4060	#define _mm256_i64scatter_ps(__addr, __index, __v1, __scale) __extension__ ({ \
				4061	__builtin_ia32_scatterdiv8sf (__addr, (__mmask8) 0xFF, (__v4di) __index, \
				4062	(__v4sf) __v1, __scale); })
				4063
				4064	#define _mm256_mask_i64scatter_ps(__addr, __mask, __index, __v1, \
				4065	__scale) __extension__ ({ \
				4066	__builtin_ia32_scatterdiv8sf (__addr, __mask, (__v4di) __index, \
				4067	(__v4sf) __v1, __scale); })
				4068
				4069	#define _mm256_i64scatter_epi32(__addr, __index, __v1, __scale) __extension__ ({ \
				4070	__builtin_ia32_scatterdiv8si (__addr, (__mmask8) 0xFF, \
				4071	(__v4di) __index, (__v4si) __v1, __scale); })
				4072
				4073	#define _mm256_mask_i64scatter_epi32(__addr, __mask, __index, __v1, \
				4074	__scale) __extension__ ({ \
				4075	__builtin_ia32_scatterdiv8si(__addr, __mask, (__v4di) __index, \
				4076	(__v4si) __v1, __scale); })
				4077
				4078	#define _mm_i32scatter_pd(__addr, __index, __v1, \
				4079	__scale) __extension__ ({ \
				4080	__builtin_ia32_scattersiv2df (__addr, (__mmask8) 0xFF, \
				4081	(__v4si) __index, (__v2df) __v1, __scale); })
				4082
				4083	#define _mm_mask_i32scatter_pd(__addr, __mask, __index, __v1, \
				4084	__scale) __extension__ ({ \
				4085	__builtin_ia32_scattersiv2df (__addr, __mask, (__v4si) __index,\
				4086	(__v2df) __v1, __scale); })
				4087
				4088	#define _mm_i32scatter_epi64(__addr, __index, __v1, __scale) __extension__ ({ \
				4089	__builtin_ia32_scattersiv2di (__addr, (__mmask8) 0xFF, \
				4090	(__v4si) __index, (__v2di) __v1, __scale); })
				4091
				4092	#define _mm_mask_i32scatter_epi64(__addr, __mask, __index, __v1, \
				4093	__scale) __extension__ ({ \
				4094	__builtin_ia32_scattersiv2di (__addr, __mask, (__v4si) __index, \
				4095	(__v2di) __v1, __scale); })
				4096
				4097	#define _mm256_i32scatter_pd(__addr, __index, __v1, __scale) __extension__ ({ \
				4098	__builtin_ia32_scattersiv4df (__addr, (__mmask8) 0xFF, \
				4099	(__v4si) __index, (__v4df) __v1, __scale); })
				4100
				4101	#define _mm256_mask_i32scatter_pd(__addr, __mask, __index, __v1, \
				4102	__scale) __extension__ ({ \
				4103	__builtin_ia32_scattersiv4df (__addr, __mask, (__v4si) __index, \
				4104	(__v4df) __v1, __scale); })
				4105
				4106	#define _mm256_i32scatter_epi64(__addr, __index, __v1, \
				4107	__scale) __extension__ ({ \
				4108	__builtin_ia32_scattersiv4di (__addr, (__mmask8) 0xFF, \
				4109	(__v4si) __index, (__v4di) __v1, __scale); })
				4110
				4111	#define _mm256_mask_i32scatter_epi64(__addr, __mask, __index, __v1, \
				4112	__scale) __extension__ ({ \
				4113	__builtin_ia32_scattersiv4di (__addr, __mask, (__v4si) __index, \
				4114	(__v4di) __v1, __scale); })
				4115
				4116	#define _mm_i32scatter_ps(__addr, __index, __v1, __scale) __extension__ ({ \
				4117	__builtin_ia32_scattersiv4sf (__addr, (__mmask8) 0xFF, \
				4118	(__v4si) __index, (__v4sf) __v1, __scale); })
				4119
				4120	#define _mm_mask_i32scatter_ps(__addr, __mask, __index, __v1, \
				4121	__scale) __extension__ ({ \
				4122	__builtin_ia32_scattersiv4sf (__addr, __mask, (__v4si) __index, \
				4123	(__v4sf) __v1, __scale); })
				4124
				4125	#define _mm_i32scatter_epi32(__addr, __index, __v1, __scale) __extension__ ({ \
				4126	__builtin_ia32_scattersiv4si (__addr, (__mmask8) 0xFF, \
				4127	(__v4si) __index, (__v4si) __v1, __scale); })
				4128
				4129	#define _mm_mask_i32scatter_epi32(__addr, __mask, __index, __v1, \
				4130	__scale) __extension__ ({ \
				4131	__builtin_ia32_scattersiv4si (__addr, __mask, (__v4si) __index,\
				4132	(__v4si) __v1, __scale); })
				4133
				4134	#define _mm256_i32scatter_ps(__addr, __index, __v1, __scale) __extension__ ({ \
				4135	__builtin_ia32_scattersiv8sf (__addr, (__mmask8) 0xFF, \
				4136	(__v8si) __index, (__v8sf) __v1, __scale); })
				4137
				4138	#define _mm256_mask_i32scatter_ps(__addr, __mask, __index, __v1, \
				4139	__scale) __extension__ ({ \
				4140	__builtin_ia32_scattersiv8sf (__addr, __mask, (__v8si) __index,\
				4141	(__v8sf) __v1, __scale); })
				4142
				4143	#define _mm256_i32scatter_epi32(__addr, __index, __v1, __scale) __extension__ ({ \
				4144	__builtin_ia32_scattersiv8si (__addr, (__mmask8) 0xFF, \
				4145	(__v8si) __index, (__v8si) __v1, __scale); })
				4146
				4147	#define _mm256_mask_i32scatter_epi32(__addr, __mask, __index, __v1, \
				4148	__scale) __extension__ ({ \
				4149	__builtin_ia32_scattersiv8si (__addr, __mask, (__v8si) __index, \
				4150	(__v8si) __v1, __scale); })
				4151
Asaf Badouh	93aa4c8	2015-07-28 12:04:40 +0000	[diff] [blame]	4152	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4153	_mm_mask_sqrt_pd (__m128d __W, __mmask8 __U, __m128d __A) {
				4154	return (__m128d) __builtin_ia32_sqrtpd128_mask ((__v2df) __A,
				4155	(__v2df) __W,
				4156	(__mmask8) __U);
				4157	}
				4158
				4159	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4160	_mm_maskz_sqrt_pd (__mmask8 __U, __m128d __A) {
				4161	return (__m128d) __builtin_ia32_sqrtpd128_mask ((__v2df) __A,
				4162	(__v2df)
				4163	_mm_setzero_pd (),
				4164	(__mmask8) __U);
				4165	}
				4166
				4167	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4168	_mm256_mask_sqrt_pd (__m256d __W, __mmask8 __U, __m256d __A) {
				4169	return (__m256d) __builtin_ia32_sqrtpd256_mask ((__v4df) __A,
				4170	(__v4df) __W,
				4171	(__mmask8) __U);
				4172	}
				4173
				4174	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4175	_mm256_maskz_sqrt_pd (__mmask8 __U, __m256d __A) {
				4176	return (__m256d) __builtin_ia32_sqrtpd256_mask ((__v4df) __A,
				4177	(__v4df)
				4178	_mm256_setzero_pd (),
				4179	(__mmask8) __U);
				4180	}
				4181
				4182	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4183	_mm_mask_sqrt_ps (__m128 __W, __mmask8 __U, __m128 __A) {
				4184	return (__m128) __builtin_ia32_sqrtps128_mask ((__v4sf) __A,
				4185	(__v4sf) __W,
				4186	(__mmask8) __U);
				4187	}
				4188
				4189	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4190	_mm_maskz_sqrt_ps (__mmask8 __U, __m128 __A) {
				4191	return (__m128) __builtin_ia32_sqrtps128_mask ((__v4sf) __A,
				4192	(__v4sf)
				4193	_mm_setzero_ps (),
				4194	(__mmask8) __U);
				4195	}
				4196
				4197	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4198	_mm256_mask_sqrt_ps (__m256 __W, __mmask8 __U, __m256 __A) {
				4199	return (__m256) __builtin_ia32_sqrtps256_mask ((__v8sf) __A,
				4200	(__v8sf) __W,
				4201	(__mmask8) __U);
				4202	}
				4203
				4204	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4205	_mm256_maskz_sqrt_ps (__mmask8 __U, __m256 __A) {
				4206	return (__m256) __builtin_ia32_sqrtps256_mask ((__v8sf) __A,
				4207	(__v8sf)
				4208	_mm256_setzero_ps (),
				4209	(__mmask8) __U);
				4210	}
				4211
				4212	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4213	_mm_mask_sub_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
				4214	return (__m128d) __builtin_ia32_subpd128_mask ((__v2df) __A,
				4215	(__v2df) __B,
				4216	(__v2df) __W,
				4217	(__mmask8) __U);
				4218	}
				4219
				4220	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4221	_mm_maskz_sub_pd (__mmask8 __U, __m128d __A, __m128d __B) {
				4222	return (__m128d) __builtin_ia32_subpd128_mask ((__v2df) __A,
				4223	(__v2df) __B,
				4224	(__v2df)
				4225	_mm_setzero_pd (),
				4226	(__mmask8) __U);
				4227	}
				4228
				4229	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4230	_mm256_mask_sub_pd (__m256d __W, __mmask8 __U, __m256d __A,
				4231	__m256d __B) {
				4232	return (__m256d) __builtin_ia32_subpd256_mask ((__v4df) __A,
				4233	(__v4df) __B,
				4234	(__v4df) __W,
				4235	(__mmask8) __U);
				4236	}
				4237
				4238	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4239	_mm256_maskz_sub_pd (__mmask8 __U, __m256d __A, __m256d __B) {
				4240	return (__m256d) __builtin_ia32_subpd256_mask ((__v4df) __A,
				4241	(__v4df) __B,
				4242	(__v4df)
				4243	_mm256_setzero_pd (),
				4244	(__mmask8) __U);
				4245	}
				4246
				4247	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4248	_mm_mask_sub_ps (__m128 __W, __mmask16 __U, __m128 __A, __m128 __B) {
				4249	return (__m128) __builtin_ia32_subps128_mask ((__v4sf) __A,
				4250	(__v4sf) __B,
				4251	(__v4sf) __W,
				4252	(__mmask8) __U);
				4253	}
				4254
				4255	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4256	_mm_maskz_sub_ps (__mmask16 __U, __m128 __A, __m128 __B) {
				4257	return (__m128) __builtin_ia32_subps128_mask ((__v4sf) __A,
				4258	(__v4sf) __B,
				4259	(__v4sf)
				4260	_mm_setzero_ps (),
				4261	(__mmask8) __U);
				4262	}
				4263
				4264	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4265	_mm256_mask_sub_ps (__m256 __W, __mmask16 __U, __m256 __A, __m256 __B) {
				4266	return (__m256) __builtin_ia32_subps256_mask ((__v8sf) __A,
				4267	(__v8sf) __B,
				4268	(__v8sf) __W,
				4269	(__mmask8) __U);
				4270	}
				4271
				4272	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4273	_mm256_maskz_sub_ps (__mmask16 __U, __m256 __A, __m256 __B) {
				4274	return (__m256) __builtin_ia32_subps256_mask ((__v8sf) __A,
				4275	(__v8sf) __B,
				4276	(__v8sf)
				4277	_mm256_setzero_ps (),
				4278	(__mmask8) __U);
				4279	}
				4280
				4281	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4282	_mm_mask2_permutex2var_epi32 (__m128i __A, __m128i __I, __mmask8 __U,
				4283	__m128i __B) {
				4284	return (__m128i) __builtin_ia32_vpermi2vard128_mask ((__v4si) __A,
				4285	(__v4si) __I
				4286	/* idx */ ,
				4287	(__v4si) __B,
				4288	(__mmask8) __U);
				4289	}
				4290
				4291	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4292	_mm256_mask2_permutex2var_epi32 (__m256i __A, __m256i __I,
				4293	__mmask8 __U, __m256i __B) {
				4294	return (__m256i) __builtin_ia32_vpermi2vard256_mask ((__v8si) __A,
				4295	(__v8si) __I
				4296	/* idx */ ,
				4297	(__v8si) __B,
				4298	(__mmask8) __U);
				4299	}
				4300
				4301	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4302	_mm_mask2_permutex2var_pd (__m128d __A, __m128i __I, __mmask8 __U,
				4303	__m128d __B) {
				4304	return (__m128d) __builtin_ia32_vpermi2varpd128_mask ((__v2df) __A,
				4305	(__v2di) __I
				4306	/* idx */ ,
				4307	(__v2df) __B,
				4308	(__mmask8)
				4309	__U);
				4310	}
				4311
				4312	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4313	_mm256_mask2_permutex2var_pd (__m256d __A, __m256i __I, __mmask8 __U,
				4314	__m256d __B) {
				4315	return (__m256d) __builtin_ia32_vpermi2varpd256_mask ((__v4df) __A,
				4316	(__v4di) __I
				4317	/* idx */ ,
				4318	(__v4df) __B,
				4319	(__mmask8)
				4320	__U);
				4321	}
				4322
				4323	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4324	_mm_mask2_permutex2var_ps (__m128 __A, __m128i __I, __mmask8 __U,
				4325	__m128 __B) {
				4326	return (__m128) __builtin_ia32_vpermi2varps128_mask ((__v4sf) __A,
				4327	(__v4si) __I
				4328	/* idx */ ,
				4329	(__v4sf) __B,
				4330	(__mmask8) __U);
				4331	}
				4332
				4333	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4334	_mm256_mask2_permutex2var_ps (__m256 __A, __m256i __I, __mmask8 __U,
				4335	__m256 __B) {
				4336	return (__m256) __builtin_ia32_vpermi2varps256_mask ((__v8sf) __A,
				4337	(__v8si) __I
				4338	/* idx */ ,
				4339	(__v8sf) __B,
				4340	(__mmask8) __U);
				4341	}
				4342
				4343	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4344	_mm_mask2_permutex2var_epi64 (__m128i __A, __m128i __I, __mmask8 __U,
				4345	__m128i __B) {
				4346	return (__m128i) __builtin_ia32_vpermi2varq128_mask ((__v2di) __A,
				4347	(__v2di) __I
				4348	/* idx */ ,
				4349	(__v2di) __B,
				4350	(__mmask8) __U);
				4351	}
				4352
				4353	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4354	_mm256_mask2_permutex2var_epi64 (__m256i __A, __m256i __I,
				4355	__mmask8 __U, __m256i __B) {
				4356	return (__m256i) __builtin_ia32_vpermi2varq256_mask ((__v4di) __A,
				4357	(__v4di) __I
				4358	/* idx */ ,
				4359	(__v4di) __B,
				4360	(__mmask8) __U);
				4361	}
				4362
				4363	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4364	_mm_permutex2var_epi32 (__m128i __A, __m128i __I, __m128i __B) {
				4365	return (__m128i) __builtin_ia32_vpermt2vard128_mask ((__v4si) __I
				4366	/* idx */ ,
				4367	(__v4si) __A,
				4368	(__v4si) __B,
				4369	(__mmask8) -1);
				4370	}
				4371
				4372	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4373	_mm_mask_permutex2var_epi32 (__m128i __A, __mmask8 __U, __m128i __I,
				4374	__m128i __B) {
				4375	return (__m128i) __builtin_ia32_vpermt2vard128_mask ((__v4si) __I
				4376	/* idx */ ,
				4377	(__v4si) __A,
				4378	(__v4si) __B,
				4379	(__mmask8) __U);
				4380	}
				4381
				4382	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4383	_mm_maskz_permutex2var_epi32 (__mmask8 __U, __m128i __A, __m128i __I,
				4384	__m128i __B) {
				4385	return (__m128i) __builtin_ia32_vpermt2vard128_maskz ((__v4si) __I
				4386	/* idx */ ,
				4387	(__v4si) __A,
				4388	(__v4si) __B,
				4389	(__mmask8)
				4390	__U);
				4391	}
				4392
				4393	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4394	_mm256_permutex2var_epi32 (__m256i __A, __m256i __I, __m256i __B) {
				4395	return (__m256i) __builtin_ia32_vpermt2vard256_mask ((__v8si) __I
				4396	/* idx */ ,
				4397	(__v8si) __A,
				4398	(__v8si) __B,
				4399	(__mmask8) -1);
				4400	}
				4401
				4402	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4403	_mm256_mask_permutex2var_epi32 (__m256i __A, __mmask8 __U, __m256i __I,
				4404	__m256i __B) {
				4405	return (__m256i) __builtin_ia32_vpermt2vard256_mask ((__v8si) __I
				4406	/* idx */ ,
				4407	(__v8si) __A,
				4408	(__v8si) __B,
				4409	(__mmask8) __U);
				4410	}
				4411
				4412	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4413	_mm256_maskz_permutex2var_epi32 (__mmask8 __U, __m256i __A,
				4414	__m256i __I, __m256i __B) {
				4415	return (__m256i) __builtin_ia32_vpermt2vard256_maskz ((__v8si) __I
				4416	/* idx */ ,
				4417	(__v8si) __A,
				4418	(__v8si) __B,
				4419	(__mmask8)
				4420	__U);
				4421	}
				4422
				4423	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4424	_mm_permutex2var_pd (__m128d __A, __m128i __I, __m128d __B) {
				4425	return (__m128d) __builtin_ia32_vpermt2varpd128_mask ((__v2di) __I
				4426	/* idx */ ,
				4427	(__v2df) __A,
				4428	(__v2df) __B,
				4429	(__mmask8) -
				4430	1);
				4431	}
				4432
				4433	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4434	_mm_mask_permutex2var_pd (__m128d __A, __mmask8 __U, __m128i __I,
				4435	__m128d __B) {
				4436	return (__m128d) __builtin_ia32_vpermt2varpd128_mask ((__v2di) __I
				4437	/* idx */ ,
				4438	(__v2df) __A,
				4439	(__v2df) __B,
				4440	(__mmask8)
				4441	__U);
				4442	}
				4443
				4444	static __inline__ __m128d __DEFAULT_FN_ATTRS
				4445	_mm_maskz_permutex2var_pd (__mmask8 __U, __m128d __A, __m128i __I,
				4446	__m128d __B) {
				4447	return (__m128d) __builtin_ia32_vpermt2varpd128_maskz ((__v2di) __I
				4448	/* idx */ ,
				4449	(__v2df) __A,
				4450	(__v2df) __B,
				4451	(__mmask8)
				4452	__U);
				4453	}
				4454
				4455	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4456	_mm256_permutex2var_pd (__m256d __A, __m256i __I, __m256d __B) {
				4457	return (__m256d) __builtin_ia32_vpermt2varpd256_mask ((__v4di) __I
				4458	/* idx */ ,
				4459	(__v4df) __A,
				4460	(__v4df) __B,
				4461	(__mmask8) -
				4462	1);
				4463	}
				4464
				4465	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4466	_mm256_mask_permutex2var_pd (__m256d __A, __mmask8 __U, __m256i __I,
				4467	__m256d __B) {
				4468	return (__m256d) __builtin_ia32_vpermt2varpd256_mask ((__v4di) __I
				4469	/* idx */ ,
				4470	(__v4df) __A,
				4471	(__v4df) __B,
				4472	(__mmask8)
				4473	__U);
				4474	}
				4475
				4476	static __inline__ __m256d __DEFAULT_FN_ATTRS
				4477	_mm256_maskz_permutex2var_pd (__mmask8 __U, __m256d __A, __m256i __I,
				4478	__m256d __B) {
				4479	return (__m256d) __builtin_ia32_vpermt2varpd256_maskz ((__v4di) __I
				4480	/* idx */ ,
				4481	(__v4df) __A,
				4482	(__v4df) __B,
				4483	(__mmask8)
				4484	__U);
				4485	}
				4486
				4487	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4488	_mm_permutex2var_ps (__m128 __A, __m128i __I, __m128 __B) {
				4489	return (__m128) __builtin_ia32_vpermt2varps128_mask ((__v4si) __I
				4490	/* idx */ ,
				4491	(__v4sf) __A,
				4492	(__v4sf) __B,
				4493	(__mmask8) -1);
				4494	}
				4495
				4496	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4497	_mm_mask_permutex2var_ps (__m128 __A, __mmask8 __U, __m128i __I,
				4498	__m128 __B) {
				4499	return (__m128) __builtin_ia32_vpermt2varps128_mask ((__v4si) __I
				4500	/* idx */ ,
				4501	(__v4sf) __A,
				4502	(__v4sf) __B,
				4503	(__mmask8) __U);
				4504	}
				4505
				4506	static __inline__ __m128 __DEFAULT_FN_ATTRS
				4507	_mm_maskz_permutex2var_ps (__mmask8 __U, __m128 __A, __m128i __I,
				4508	__m128 __B) {
				4509	return (__m128) __builtin_ia32_vpermt2varps128_maskz ((__v4si) __I
				4510	/* idx */ ,
				4511	(__v4sf) __A,
				4512	(__v4sf) __B,
				4513	(__mmask8)
				4514	__U);
				4515	}
				4516
				4517	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4518	_mm256_permutex2var_ps (__m256 __A, __m256i __I, __m256 __B) {
				4519	return (__m256) __builtin_ia32_vpermt2varps256_mask ((__v8si) __I
				4520	/* idx */ ,
				4521	(__v8sf) __A,
				4522	(__v8sf) __B,
				4523	(__mmask8) -1);
				4524	}
				4525
				4526	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4527	_mm256_mask_permutex2var_ps (__m256 __A, __mmask8 __U, __m256i __I,
				4528	__m256 __B) {
				4529	return (__m256) __builtin_ia32_vpermt2varps256_mask ((__v8si) __I
				4530	/* idx */ ,
				4531	(__v8sf) __A,
				4532	(__v8sf) __B,
				4533	(__mmask8) __U);
				4534	}
				4535
				4536	static __inline__ __m256 __DEFAULT_FN_ATTRS
				4537	_mm256_maskz_permutex2var_ps (__mmask8 __U, __m256 __A, __m256i __I,
				4538	__m256 __B) {
				4539	return (__m256) __builtin_ia32_vpermt2varps256_maskz ((__v8si) __I
				4540	/* idx */ ,
				4541	(__v8sf) __A,
				4542	(__v8sf) __B,
				4543	(__mmask8)
				4544	__U);
				4545	}
				4546
				4547	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4548	_mm_permutex2var_epi64 (__m128i __A, __m128i __I, __m128i __B) {
				4549	return (__m128i) __builtin_ia32_vpermt2varq128_mask ((__v2di) __I
				4550	/* idx */ ,
				4551	(__v2di) __A,
				4552	(__v2di) __B,
				4553	(__mmask8) -1);
				4554	}
				4555
				4556	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4557	_mm_mask_permutex2var_epi64 (__m128i __A, __mmask8 __U, __m128i __I,
				4558	__m128i __B) {
				4559	return (__m128i) __builtin_ia32_vpermt2varq128_mask ((__v2di) __I
				4560	/* idx */ ,
				4561	(__v2di) __A,
				4562	(__v2di) __B,
				4563	(__mmask8) __U);
				4564	}
				4565
				4566	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4567	_mm_maskz_permutex2var_epi64 (__mmask8 __U, __m128i __A, __m128i __I,
				4568	__m128i __B) {
				4569	return (__m128i) __builtin_ia32_vpermt2varq128_maskz ((__v2di) __I
				4570	/* idx */ ,
				4571	(__v2di) __A,
				4572	(__v2di) __B,
				4573	(__mmask8)
				4574	__U);
				4575	}
				4576
				4577
				4578	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4579	_mm256_permutex2var_epi64 (__m256i __A, __m256i __I, __m256i __B) {
				4580	return (__m256i) __builtin_ia32_vpermt2varq256_mask ((__v4di) __I
				4581	/* idx */ ,
				4582	(__v4di) __A,
				4583	(__v4di) __B,
				4584	(__mmask8) -1);
				4585	}
				4586
				4587	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4588	_mm256_mask_permutex2var_epi64 (__m256i __A, __mmask8 __U, __m256i __I,
				4589	__m256i __B) {
				4590	return (__m256i) __builtin_ia32_vpermt2varq256_mask ((__v4di) __I
				4591	/* idx */ ,
				4592	(__v4di) __A,
				4593	(__v4di) __B,
				4594	(__mmask8) __U);
				4595	}
				4596
				4597	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4598	_mm256_maskz_permutex2var_epi64 (__mmask8 __U, __m256i __A,
				4599	__m256i __I, __m256i __B) {
				4600	return (__m256i) __builtin_ia32_vpermt2varq256_maskz ((__v4di) __I
				4601	/* idx */ ,
				4602	(__v4di) __A,
				4603	(__v4di) __B,
				4604	(__mmask8)
				4605	__U);
				4606	}
				4607
Michael Zuckerman	7cdb72f	2016-02-18 09:09:34 +0000	[diff] [blame]	4608	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4609	_mm_mask_cvtepi8_epi32 (__m128i __W, __mmask8 __U, __m128i __A)
				4610	{
				4611	return (__m128i) __builtin_ia32_pmovsxbd128_mask ((__v16qi) __A,
				4612	(__v4si) __W,
				4613	(__mmask8) __U);
				4614	}
				4615
				4616	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4617	_mm_maskz_cvtepi8_epi32 (__mmask8 __U, __m128i __A)
				4618	{
				4619	return (__m128i) __builtin_ia32_pmovsxbd128_mask ((__v16qi) __A,
				4620	(__v4si)
				4621	_mm_setzero_si128 (),
				4622	(__mmask8) __U);
				4623	}
				4624
				4625	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4626	_mm256_mask_cvtepi8_epi32 (__m256i __W, __mmask8 __U, __m128i __A)
				4627	{
				4628	return (__m256i) __builtin_ia32_pmovsxbd256_mask ((__v16qi) __A,
				4629	(__v8si) __W,
				4630	(__mmask8) __U);
				4631	}
				4632
				4633	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4634	_mm256_maskz_cvtepi8_epi32 (__mmask8 __U, __m128i __A)
				4635	{
				4636	return (__m256i) __builtin_ia32_pmovsxbd256_mask ((__v16qi) __A,
				4637	(__v8si)
				4638	_mm256_setzero_si256 (),
				4639	(__mmask8) __U);
				4640	}
				4641
				4642	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4643	_mm_mask_cvtepi8_epi64 (__m128i __W, __mmask8 __U, __m128i __A)
				4644	{
				4645	return (__m128i) __builtin_ia32_pmovsxbq128_mask ((__v16qi) __A,
				4646	(__v2di) __W,
				4647	(__mmask8) __U);
				4648	}
				4649
				4650	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4651	_mm_maskz_cvtepi8_epi64 (__mmask8 __U, __m128i __A)
				4652	{
				4653	return (__m128i) __builtin_ia32_pmovsxbq128_mask ((__v16qi) __A,
				4654	(__v2di)
				4655	_mm_setzero_si128 (),
				4656	(__mmask8) __U);
				4657	}
				4658
				4659	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4660	_mm256_mask_cvtepi8_epi64 (__m256i __W, __mmask8 __U, __m128i __A)
				4661	{
				4662	return (__m256i) __builtin_ia32_pmovsxbq256_mask ((__v16qi) __A,
				4663	(__v4di) __W,
				4664	(__mmask8) __U);
				4665	}
				4666
				4667	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4668	_mm256_maskz_cvtepi8_epi64 (__mmask8 __U, __m128i __A)
				4669	{
				4670	return (__m256i) __builtin_ia32_pmovsxbq256_mask ((__v16qi) __A,
				4671	(__v4di)
				4672	_mm256_setzero_si256 (),
				4673	(__mmask8) __U);
				4674	}
				4675
				4676	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4677	_mm_mask_cvtepi32_epi64 (__m128i __W, __mmask8 __U, __m128i __X)
				4678	{
				4679	return (__m128i) __builtin_ia32_pmovsxdq128_mask ((__v4si) __X,
				4680	(__v2di) __W,
				4681	(__mmask8) __U);
				4682	}
				4683
				4684	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4685	_mm_maskz_cvtepi32_epi64 (__mmask8 __U, __m128i __X)
				4686	{
				4687	return (__m128i) __builtin_ia32_pmovsxdq128_mask ((__v4si) __X,
				4688	(__v2di)
				4689	_mm_setzero_si128 (),
				4690	(__mmask8) __U);
				4691	}
				4692
				4693	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4694	_mm256_mask_cvtepi32_epi64 (__m256i __W, __mmask8 __U, __m128i __X)
				4695	{
				4696	return (__m256i) __builtin_ia32_pmovsxdq256_mask ((__v4si) __X,
				4697	(__v4di) __W,
				4698	(__mmask8) __U);
				4699	}
				4700
				4701	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4702	_mm256_maskz_cvtepi32_epi64 (__mmask8 __U, __m128i __X)
				4703	{
				4704	return (__m256i) __builtin_ia32_pmovsxdq256_mask ((__v4si) __X,
				4705	(__v4di)
				4706	_mm256_setzero_si256 (),
				4707	(__mmask8) __U);
				4708	}
				4709
				4710	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4711	_mm_mask_cvtepi16_epi32 (__m128i __W, __mmask8 __U, __m128i __A)
				4712	{
				4713	return (__m128i) __builtin_ia32_pmovsxwd128_mask ((__v8hi) __A,
				4714	(__v4si) __W,
				4715	(__mmask8) __U);
				4716	}
				4717
				4718	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4719	_mm_maskz_cvtepi16_epi32 (__mmask8 __U, __m128i __A)
				4720	{
				4721	return (__m128i) __builtin_ia32_pmovsxwd128_mask ((__v8hi) __A,
				4722	(__v4si)
				4723	_mm_setzero_si128 (),
				4724	(__mmask8) __U);
				4725	}
				4726
				4727	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4728	_mm256_mask_cvtepi16_epi32 (__m256i __W, __mmask8 __U, __m128i __A)
				4729	{
				4730	return (__m256i) __builtin_ia32_pmovsxwd256_mask ((__v8hi) __A,
				4731	(__v8si) __W,
				4732	(__mmask8) __U);
				4733	}
				4734
				4735	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4736	_mm256_maskz_cvtepi16_epi32 (__mmask8 __U, __m128i __A)
				4737	{
				4738	return (__m256i) __builtin_ia32_pmovsxwd256_mask ((__v8hi) __A,
				4739	(__v8si)
				4740	_mm256_setzero_si256 (),
				4741	(__mmask8) __U);
				4742	}
				4743
				4744	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4745	_mm_mask_cvtepi16_epi64 (__m128i __W, __mmask8 __U, __m128i __A)
				4746	{
				4747	return (__m128i) __builtin_ia32_pmovsxwq128_mask ((__v8hi) __A,
				4748	(__v2di) __W,
				4749	(__mmask8) __U);
				4750	}
				4751
				4752	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4753	_mm_maskz_cvtepi16_epi64 (__mmask8 __U, __m128i __A)
				4754	{
				4755	return (__m128i) __builtin_ia32_pmovsxwq128_mask ((__v8hi) __A,
				4756	(__v2di)
				4757	_mm_setzero_si128 (),
				4758	(__mmask8) __U);
				4759	}
				4760
				4761	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4762	_mm256_mask_cvtepi16_epi64 (__m256i __W, __mmask8 __U, __m128i __A)
				4763	{
				4764	return (__m256i) __builtin_ia32_pmovsxwq256_mask ((__v8hi) __A,
				4765	(__v4di) __W,
				4766	(__mmask8) __U);
				4767	}
				4768
				4769	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4770	_mm256_maskz_cvtepi16_epi64 (__mmask8 __U, __m128i __A)
				4771	{
				4772	return (__m256i) __builtin_ia32_pmovsxwq256_mask ((__v8hi) __A,
				4773	(__v4di)
				4774	_mm256_setzero_si256 (),
				4775	(__mmask8) __U);
				4776	}
				4777
				4778
Michael Zuckerman	7a33dce	2016-02-21 14:00:11 +0000	[diff] [blame]	4779	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4780	_mm_mask_cvtepu8_epi32 (__m128i __W, __mmask8 __U, __m128i __A)
				4781	{
				4782	return (__m128i) __builtin_ia32_pmovzxbd128_mask ((__v16qi) __A,
				4783	(__v4si) __W,
				4784	(__mmask8) __U);
				4785	}
				4786
				4787	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4788	_mm_maskz_cvtepu8_epi32 (__mmask8 __U, __m128i __A)
				4789	{
				4790	return (__m128i) __builtin_ia32_pmovzxbd128_mask ((__v16qi) __A,
				4791	(__v4si)
				4792	_mm_setzero_si128 (),
				4793	(__mmask8) __U);
				4794	}
				4795
				4796	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4797	_mm256_mask_cvtepu8_epi32 (__m256i __W, __mmask8 __U, __m128i __A)
				4798	{
				4799	return (__m256i) __builtin_ia32_pmovzxbd256_mask ((__v16qi) __A,
				4800	(__v8si) __W,
				4801	(__mmask8) __U);
				4802	}
				4803
				4804	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4805	_mm256_maskz_cvtepu8_epi32 (__mmask8 __U, __m128i __A)
				4806	{
				4807	return (__m256i) __builtin_ia32_pmovzxbd256_mask ((__v16qi) __A,
				4808	(__v8si)
				4809	_mm256_setzero_si256 (),
				4810	(__mmask8) __U);
				4811	}
				4812
				4813	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4814	_mm_mask_cvtepu8_epi64 (__m128i __W, __mmask8 __U, __m128i __A)
				4815	{
				4816	return (__m128i) __builtin_ia32_pmovzxbq128_mask ((__v16qi) __A,
				4817	(__v2di) __W,
				4818	(__mmask8) __U);
				4819	}
				4820
				4821	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4822	_mm_maskz_cvtepu8_epi64 (__mmask8 __U, __m128i __A)
				4823	{
				4824	return (__m128i) __builtin_ia32_pmovzxbq128_mask ((__v16qi) __A,
				4825	(__v2di)
				4826	_mm_setzero_si128 (),
				4827	(__mmask8) __U);
				4828	}
				4829
				4830	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4831	_mm256_mask_cvtepu8_epi64 (__m256i __W, __mmask8 __U, __m128i __A)
				4832	{
				4833	return (__m256i) __builtin_ia32_pmovzxbq256_mask ((__v16qi) __A,
				4834	(__v4di) __W,
				4835	(__mmask8) __U);
				4836	}
				4837
				4838	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4839	_mm256_maskz_cvtepu8_epi64 (__mmask8 __U, __m128i __A)
				4840	{
				4841	return (__m256i) __builtin_ia32_pmovzxbq256_mask ((__v16qi) __A,
				4842	(__v4di)
				4843	_mm256_setzero_si256 (),
				4844	(__mmask8) __U);
				4845	}
				4846
				4847	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4848	_mm_mask_cvtepu32_epi64 (__m128i __W, __mmask8 __U, __m128i __X)
				4849	{
				4850	return (__m128i) __builtin_ia32_pmovzxdq128_mask ((__v4si) __X,
				4851	(__v2di) __W,
				4852	(__mmask8) __U);
				4853	}
				4854
				4855	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4856	_mm_maskz_cvtepu32_epi64 (__mmask8 __U, __m128i __X)
				4857	{
				4858	return (__m128i) __builtin_ia32_pmovzxdq128_mask ((__v4si) __X,
				4859	(__v2di)
				4860	_mm_setzero_si128 (),
				4861	(__mmask8) __U);
				4862	}
				4863
				4864	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4865	_mm256_mask_cvtepu32_epi64 (__m256i __W, __mmask8 __U, __m128i __X)
				4866	{
				4867	return (__m256i) __builtin_ia32_pmovzxdq256_mask ((__v4si) __X,
				4868	(__v4di) __W,
				4869	(__mmask8) __U);
				4870	}
				4871
				4872	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4873	_mm256_maskz_cvtepu32_epi64 (__mmask8 __U, __m128i __X)
				4874	{
				4875	return (__m256i) __builtin_ia32_pmovzxdq256_mask ((__v4si) __X,
				4876	(__v4di)
				4877	_mm256_setzero_si256 (),
				4878	(__mmask8) __U);
				4879	}
				4880
				4881	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4882	_mm_mask_cvtepu16_epi32 (__m128i __W, __mmask8 __U, __m128i __A)
				4883	{
				4884	return (__m128i) __builtin_ia32_pmovzxwd128_mask ((__v8hi) __A,
				4885	(__v4si) __W,
				4886	(__mmask8) __U);
				4887	}
				4888
				4889	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4890	_mm_maskz_cvtepu16_epi32 (__mmask8 __U, __m128i __A)
				4891	{
				4892	return (__m128i) __builtin_ia32_pmovzxwd128_mask ((__v8hi) __A,
				4893	(__v4si)
				4894	_mm_setzero_si128 (),
				4895	(__mmask8) __U);
				4896	}
				4897
				4898	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4899	_mm256_mask_cvtepu16_epi32 (__m256i __W, __mmask8 __U, __m128i __A)
				4900	{
				4901	return (__m256i) __builtin_ia32_pmovzxwd256_mask ((__v8hi) __A,
				4902	(__v8si) __W,
				4903	(__mmask8) __U);
				4904	}
				4905
				4906	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4907	_mm256_maskz_cvtepu16_epi32 (__mmask8 __U, __m128i __A)
				4908	{
				4909	return (__m256i) __builtin_ia32_pmovzxwd256_mask ((__v8hi) __A,
				4910	(__v8si)
				4911	_mm256_setzero_si256 (),
				4912	(__mmask8) __U);
				4913	}
				4914
				4915	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4916	_mm_mask_cvtepu16_epi64 (__m128i __W, __mmask8 __U, __m128i __A)
				4917	{
				4918	return (__m128i) __builtin_ia32_pmovzxwq128_mask ((__v8hi) __A,
				4919	(__v2di) __W,
				4920	(__mmask8) __U);
				4921	}
				4922
				4923	static __inline__ __m128i __DEFAULT_FN_ATTRS
				4924	_mm_maskz_cvtepu16_epi64 (__mmask8 __U, __m128i __A)
				4925	{
				4926	return (__m128i) __builtin_ia32_pmovzxwq128_mask ((__v8hi) __A,
				4927	(__v2di)
				4928	_mm_setzero_si128 (),
				4929	(__mmask8) __U);
				4930	}
				4931
				4932	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4933	_mm256_mask_cvtepu16_epi64 (__m256i __W, __mmask8 __U, __m128i __A)
				4934	{
				4935	return (__m256i) __builtin_ia32_pmovzxwq256_mask ((__v8hi) __A,
				4936	(__v4di) __W,
				4937	(__mmask8) __U);
				4938	}
				4939
				4940	static __inline__ __m256i __DEFAULT_FN_ATTRS
				4941	_mm256_maskz_cvtepu16_epi64 (__mmask8 __U, __m128i __A)
				4942	{
				4943	return (__m256i) __builtin_ia32_pmovzxwq256_mask ((__v8hi) __A,
				4944	(__v4di)
				4945	_mm256_setzero_si256 (),
				4946	(__mmask8) __U);
				4947	}
				4948
				4949
Michael Zuckerman	38a2727	2016-02-22 09:05:41 +0000	[diff] [blame]	4950	#define _mm_rol_epi32(a, b) __extension__ ({\
				4951	(__m128i)__builtin_ia32_prold128_mask((__v4si) (a), (b),\
				4952	(__v4si)\
				4953	_mm_setzero_si128 (),\
				4954	(__mmask8) -1); })
				4955
				4956	#define _mm_mask_rol_epi32(w, u, a, b) __extension__ ({\
				4957	(__m128i)__builtin_ia32_prold128_mask((__v4si) (a), (b),\
				4958	(__v4si) (w),\
				4959	(__mmask8) (u)); })
				4960
				4961	#define _mm_maskz_rol_epi32(u, a, b) __extension__ ({\
				4962	(__m128i)__builtin_ia32_prold128_mask((__v4si) (a), (b),\
				4963	(__v4si)\
				4964	_mm_setzero_si128 (),\
				4965	(__mmask8) (u)); })
				4966
				4967	#define _mm256_rol_epi32(a, b) __extension__ ({\
				4968	(__m256i)__builtin_ia32_prold256_mask((__v8si) (a), (b),\
				4969	(__v8si)\
				4970	_mm256_setzero_si256 (),\
				4971	(__mmask8) -1); })
				4972
				4973	#define _mm256_mask_rol_epi32(w, u, a, b) __extension__ ({\
				4974	(__m256i)__builtin_ia32_prold256_mask((__v8si) (a), (b),\
				4975	(__v8si) (w),\
				4976	(__mmask8) (u)); })
				4977
				4978	#define _mm256_maskz_rol_epi32(u, a, b) __extension__ ({\
				4979	(__m256i)__builtin_ia32_prold256_mask((__v8si) (a), (b),\
				4980	(__v8si)\
				4981	_mm256_setzero_si256 (),\
				4982	(__mmask8) (u)); })
				4983
Michael Zuckerman	477e0a3	2016-02-22 09:42:57 +0000	[diff] [blame]	4984	#define _mm_rol_epi64(a, b) __extension__ ({\
Michael Zuckerman	38a2727	2016-02-22 09:05:41 +0000	[diff] [blame]	4985	(__m128i)__builtin_ia32_prolq128_mask((__v2di) (a), (b),\
				4986	(__v2di)\
				4987	_mm_setzero_di (),\
				4988	(__mmask8) -1); })
				4989
				4990	#define _mm_mask_rol_epi64(w, u, a, b) __extension__ ({\
				4991	(__m128i)__builtin_ia32_prolq128_mask((__v2di) (a), (b),\
				4992	(__v2di) (w),\
				4993	(__mmask8) (u)); })
				4994
				4995	#define _mm_maskz_rol_epi64(u, a, b) __extension__ ({\
				4996	(__m128i)__builtin_ia32_prolq128_mask((__v2di) (a), (b),\
				4997	(__v2di)\
				4998	_mm_setzero_di(),\
				4999	(__mmask8) (u)); })
				5000
				5001	#define _mm256_rol_epi64(a, b) __extension__ ({\
				5002	(__m256i)__builtin_ia32_prolq256_mask((__v4di) (a), (b),\
				5003	(__v4di)\
				5004	_mm256_setzero_si256 (),\
				5005	(__mmask8) -1); })
				5006
				5007	#define _mm256_mask_rol_epi64(w, u, a, b) __extension__ ({\
				5008	(__m256i)__builtin_ia32_prolq256_mask((__v4di) (a), (b),\
				5009	(__v4di) (w),\
				5010	(__mmask8) (u)); })
				5011
				5012	#define _mm256_maskz_rol_epi64(u, a, b) __extension__ ({\
				5013	(__m256i)__builtin_ia32_prolq256_mask((__v4di) (a), (b),\
				5014	(__v4di)\
				5015	_mm256_setzero_si256 (),\
				5016	(__mmask8) (u)); })
				5017
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5018	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5019	_mm_rolv_epi32 (__m128i __A, __m128i __B)
				5020	{
				5021	return (__m128i) __builtin_ia32_prolvd128_mask ((__v4si) __A,
				5022	(__v4si) __B,
				5023	(__v4si)
				5024	_mm_setzero_si128 (),
				5025	(__mmask8) -1);
				5026	}
				5027
				5028	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5029	_mm_mask_rolv_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				5030	__m128i __B)
				5031	{
				5032	return (__m128i) __builtin_ia32_prolvd128_mask ((__v4si) __A,
				5033	(__v4si) __B,
				5034	(__v4si) __W,
				5035	(__mmask8) __U);
				5036	}
				5037
				5038	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5039	_mm_maskz_rolv_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				5040	{
				5041	return (__m128i) __builtin_ia32_prolvd128_mask ((__v4si) __A,
				5042	(__v4si) __B,
				5043	(__v4si)
				5044	_mm_setzero_si128 (),
				5045	(__mmask8) __U);
				5046	}
				5047
				5048	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5049	_mm256_rolv_epi32 (__m256i __A, __m256i __B)
				5050	{
				5051	return (__m256i) __builtin_ia32_prolvd256_mask ((__v8si) __A,
				5052	(__v8si) __B,
				5053	(__v8si)
				5054	_mm256_setzero_si256 (),
				5055	(__mmask8) -1);
				5056	}
				5057
				5058	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5059	_mm256_mask_rolv_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				5060	__m256i __B)
				5061	{
				5062	return (__m256i) __builtin_ia32_prolvd256_mask ((__v8si) __A,
				5063	(__v8si) __B,
				5064	(__v8si) __W,
				5065	(__mmask8) __U);
				5066	}
				5067
				5068	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5069	_mm256_maskz_rolv_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				5070	{
				5071	return (__m256i) __builtin_ia32_prolvd256_mask ((__v8si) __A,
				5072	(__v8si) __B,
				5073	(__v8si)
				5074	_mm256_setzero_si256 (),
				5075	(__mmask8) __U);
				5076	}
				5077
				5078	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5079	_mm_rolv_epi64 (__m128i __A, __m128i __B)
				5080	{
				5081	return (__m128i) __builtin_ia32_prolvq128_mask ((__v2di) __A,
				5082	(__v2di) __B,
				5083	(__v2di)
				5084	_mm_setzero_di (),
				5085	(__mmask8) -1);
				5086	}
				5087
				5088	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5089	_mm_mask_rolv_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				5090	__m128i __B)
				5091	{
				5092	return (__m128i) __builtin_ia32_prolvq128_mask ((__v2di) __A,
				5093	(__v2di) __B,
				5094	(__v2di) __W,
				5095	(__mmask8) __U);
				5096	}
				5097
				5098	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5099	_mm_maskz_rolv_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				5100	{
				5101	return (__m128i) __builtin_ia32_prolvq128_mask ((__v2di) __A,
				5102	(__v2di) __B,
				5103	(__v2di)
				5104	_mm_setzero_di (),
				5105	(__mmask8) __U);
				5106	}
				5107
				5108	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5109	_mm256_rolv_epi64 (__m256i __A, __m256i __B)
				5110	{
				5111	return (__m256i) __builtin_ia32_prolvq256_mask ((__v4di) __A,
				5112	(__v4di) __B,
				5113	(__v4di)
				5114	_mm256_setzero_si256 (),
				5115	(__mmask8) -1);
				5116	}
				5117
				5118	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5119	_mm256_mask_rolv_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				5120	__m256i __B)
				5121	{
				5122	return (__m256i) __builtin_ia32_prolvq256_mask ((__v4di) __A,
				5123	(__v4di) __B,
				5124	(__v4di) __W,
				5125	(__mmask8) __U);
				5126	}
				5127
				5128	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5129	_mm256_maskz_rolv_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				5130	{
				5131	return (__m256i) __builtin_ia32_prolvq256_mask ((__v4di) __A,
				5132	(__v4di) __B,
				5133	(__v4di)
				5134	_mm256_setzero_si256 (),
				5135	(__mmask8) __U);
				5136	}
				5137
				5138	#define _mm_ror_epi32( __A, __B) __extension__ ({ \
				5139	__builtin_ia32_prord128_mask ((__v4si)( __A),( __B),\
				5140	(__v4si)\
				5141	_mm_setzero_si128 (),\
				5142	(__mmask8) -1);\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5143	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5144
				5145	#define _mm_mask_ror_epi32( __W, __U, __A ,__B) __extension__ ({ \
				5146	__builtin_ia32_prord128_mask ((__v4si) __A, __B,\
				5147	(__v4si)( __W),\
				5148	(__mmask8)( __U));\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5149	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5150
				5151	#define _mm_maskz_ror_epi32( __U, __A, __B) __extension__ ({ \
				5152	__builtin_ia32_prord128_mask ((__v4si)( __A),( __B),\
				5153	(__v4si)\
				5154	_mm_setzero_si128 (),\
				5155	(__mmask8)( __U));\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5156	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5157
				5158	#define _mm256_ror_epi32( __A, __B) __extension__ ({ \
				5159	__builtin_ia32_prord256_mask ((__v8si)( __A),( __B),\
				5160	(__v8si)\
				5161	_mm256_setzero_si256 (),\
				5162	(__mmask8) -1);\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5163	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5164
				5165	#define _mm256_mask_ror_epi32( __W, __U, __A ,__B) __extension__ ({ \
				5166	__builtin_ia32_prord256_mask ((__v8si) __A, __B,\
				5167	(__v8si)( __W),\
				5168	(__mmask8)( __U));\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5169	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5170
				5171	#define _mm256_maskz_ror_epi32( __U, __A, __B) __extension__ ({ \
				5172	__builtin_ia32_prord256_mask ((__v8si)( __A),( __B),\
				5173	(__v8si)\
				5174	_mm256_setzero_si256 (),\
				5175	(__mmask8)( __U));\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5176	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5177
				5178	#define _mm_ror_epi64( __A, __B) __extension__ ({ \
				5179	__builtin_ia32_prorq128_mask ((__v2di)( __A),( __B),\
				5180	(__v2di)\
				5181	_mm_setzero_di (),\
				5182	(__mmask8) -1);\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5183	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5184
				5185	#define _mm_mask_ror_epi64( __W, __U, __A ,__B) __extension__ ({ \
				5186	__builtin_ia32_prorq128_mask ((__v2di) __A, __B,\
				5187	(__v2di)( __W),\
				5188	(__mmask8)( __U));\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5189	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5190
				5191	#define _mm_maskz_ror_epi64( __U, __A, __B) __extension__ ({ \
				5192	__builtin_ia32_prorq128_mask ((__v2di)( __A),( __B),\
				5193	(__v2di)\
				5194	_mm_setzero_di (),\
				5195	(__mmask8)( __U));\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5196	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5197
				5198	#define _mm256_ror_epi64( __A, __B) __extension__ ({ \
				5199	__builtin_ia32_prorq256_mask ((__v4di)( __A),( __B),\
				5200	(__v4di)\
				5201	_mm256_setzero_si256 (),\
				5202	(__mmask8) -1);\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5203	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5204
				5205	#define _mm256_mask_ror_epi64( __W, __U, __A ,__B) __extension__ ({ \
				5206	__builtin_ia32_prorq256_mask ((__v4di) __A, __B,\
				5207	(__v4di)( __W),\
				5208	(__mmask8)( __U));\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5209	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5210
				5211	#define _mm256_maskz_ror_epi64( __U, __A, __B) __extension__ ({ \
				5212	__builtin_ia32_prorq256_mask ((__v4di)( __A),( __B),\
				5213	(__v4di)\
				5214	_mm256_setzero_si256 (),\
				5215	(__mmask8)( __U));\
Michael Zuckerman	4924c7a	2016-02-23 14:23:53 +0000	[diff] [blame]	5216	})
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5217
Michael Zuckerman	1ac360c	2016-03-01 11:38:16 +0000	[diff] [blame]	5218	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5219	_mm_mask_sll_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				5220	__m128i __B)
				5221	{
				5222	return (__m128i) __builtin_ia32_pslld128_mask ((__v4si) __A,
				5223	(__v4si) __B,
				5224	(__v4si) __W,
				5225	(__mmask8) __U);
				5226	}
				5227
				5228	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5229	_mm_maskz_sll_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				5230	{
				5231	return (__m128i) __builtin_ia32_pslld128_mask ((__v4si) __A,
				5232	(__v4si) __B,
				5233	(__v4si)
				5234	_mm_setzero_si128 (),
				5235	(__mmask8) __U);
				5236	}
				5237
				5238	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5239	_mm256_mask_sll_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				5240	__m128i __B)
				5241	{
				5242	return (__m256i) __builtin_ia32_pslld256_mask ((__v8si) __A,
				5243	(__v4si) __B,
				5244	(__v8si) __W,
				5245	(__mmask8) __U);
				5246	}
				5247
				5248	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5249	_mm256_maskz_sll_epi32 (__mmask8 __U, __m256i __A, __m128i __B)
				5250	{
				5251	return (__m256i) __builtin_ia32_pslld256_mask ((__v8si) __A,
				5252	(__v4si) __B,
				5253	(__v8si)
				5254	_mm256_setzero_si256 (),
				5255	(__mmask8) __U);
				5256	}
				5257
				5258	#define _mm_mask_slli_epi32( __W, __U, __A, __B) __extension__ ({ \
				5259	__builtin_ia32_pslldi128_mask ((__v4si)( __A),( __B),\
				5260	(__v4si)( __W),\
				5261	(__mmask8)( __U));\
				5262	})
				5263
				5264	#define _mm_maskz_slli_epi32( __U, __A, __B) __extension__ ({ \
				5265	__builtin_ia32_pslldi128_mask ((__v4si)( __A),( __B),\
				5266	(__v4si)\
				5267	_mm_setzero_si128 (),\
				5268	(__mmask8)( __U));\
				5269	})
				5270
				5271	#define _mm256_mask_slli_epi32( __W, __U, __A ,__B) __extension__ ({ \
				5272	__builtin_ia32_pslldi256_mask ((__v8si) (__A), (__B),\
				5273	(__v8si)( __W),\
				5274	(__mmask8)( __U));\
				5275	})
				5276
				5277	#define _mm256_maskz_slli_epi32( __U, __A, __B) __extension__ ({ \
				5278	__builtin_ia32_pslldi256_mask ((__v8si)( __A),( __B),\
				5279	(__v8si)\
				5280	_mm256_setzero_si256 (),\
				5281	(__mmask8)( __U));\
				5282	})
				5283
				5284	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5285	_mm_mask_sll_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				5286	__m128i __B)
				5287	{
				5288	return (__m128i) __builtin_ia32_psllq128_mask ((__v2di) __A,
				5289	(__v2di) __B,
				5290	(__v2di) __W,
				5291	(__mmask8) __U);
				5292	}
				5293
				5294	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5295	_mm_maskz_sll_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				5296	{
				5297	return (__m128i) __builtin_ia32_psllq128_mask ((__v2di) __A,
				5298	(__v2di) __B,
				5299	(__v2di)
				5300	_mm_setzero_di (),
				5301	(__mmask8) __U);
				5302	}
				5303
				5304	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5305	_mm256_mask_sll_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				5306	__m128i __B)
				5307	{
				5308	return (__m256i) __builtin_ia32_psllq256_mask ((__v4di) __A,
				5309	(__v2di) __B,
				5310	(__v4di) __W,
				5311	(__mmask8) __U);
				5312	}
				5313
				5314	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5315	_mm256_maskz_sll_epi64 (__mmask8 __U, __m256i __A, __m128i __B)
				5316	{
				5317	return (__m256i) __builtin_ia32_psllq256_mask ((__v4di) __A,
				5318	(__v2di) __B,
				5319	(__v4di)
				5320	_mm256_setzero_si256 (),
				5321	(__mmask8) __U);
				5322	}
				5323
				5324	#define _mm_mask_slli_epi64( __W, __U, __A, __B) __extension__ ({ \
				5325	__builtin_ia32_psllqi128_mask ((__v2di)( __A),( __B),\
				5326	(__v2di)( __W),\
				5327	(__mmask8)( __U));\
				5328	})
				5329
				5330	#define _mm_maskz_slli_epi64( __U, __A, __B) __extension__ ({ \
				5331	__builtin_ia32_psllqi128_mask ((__v2di)( __A),( __B),\
				5332	(__v2di)\
				5333	_mm_setzero_di (),\
				5334	(__mmask8)( __U));\
				5335	})
				5336
				5337	#define _mm256_mask_slli_epi64( __W, __U, __A ,__B) __extension__ ({ \
				5338	__builtin_ia32_psllqi256_mask ((__v4di) (__A), (__B),\
				5339	(__v4di)( __W),\
				5340	(__mmask8)( __U));\
				5341	})
				5342
				5343	#define _mm256_maskz_slli_epi64( __U, __A, __B) __extension__ ({ \
				5344	__builtin_ia32_psllqi256_mask ((__v4di)( __A),( __B),\
				5345	(__v4di)\
				5346	_mm256_setzero_si256 (),\
				5347	(__mmask8)( __U));\
				5348	})
				5349
Michael Zuckerman	0231f16	2016-02-23 13:41:13 +0000	[diff] [blame]	5350
Michael Zuckerman	e98cc74	2016-02-23 15:59:47 +0000	[diff] [blame]	5351	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5352	_mm_rorv_epi32 (__m128i __A, __m128i __B)
				5353	{
				5354	return (__m128i) __builtin_ia32_prorvd128_mask ((__v4si) __A,
				5355	(__v4si) __B,
				5356	(__v4si)
				5357	_mm_setzero_si128 (),
				5358	(__mmask8) -1);
				5359	}
				5360
				5361	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5362	_mm_mask_rorv_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				5363	__m128i __B)
				5364	{
				5365	return (__m128i) __builtin_ia32_prorvd128_mask ((__v4si) __A,
				5366	(__v4si) __B,
				5367	(__v4si) __W,
				5368	(__mmask8) __U);
				5369	}
				5370
				5371	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5372	_mm_maskz_rorv_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				5373	{
				5374	return (__m128i) __builtin_ia32_prorvd128_mask ((__v4si) __A,
				5375	(__v4si) __B,
				5376	(__v4si)
				5377	_mm_setzero_si128 (),
				5378	(__mmask8) __U);
				5379	}
				5380
				5381	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5382	_mm256_rorv_epi32 (__m256i __A, __m256i __B)
				5383	{
				5384	return (__m256i) __builtin_ia32_prorvd256_mask ((__v8si) __A,
				5385	(__v8si) __B,
				5386	(__v8si)
				5387	_mm256_setzero_si256 (),
				5388	(__mmask8) -1);
				5389	}
				5390
				5391	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5392	_mm256_mask_rorv_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				5393	__m256i __B)
				5394	{
				5395	return (__m256i) __builtin_ia32_prorvd256_mask ((__v8si) __A,
				5396	(__v8si) __B,
				5397	(__v8si) __W,
				5398	(__mmask8) __U);
				5399	}
				5400
				5401	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5402	_mm256_maskz_rorv_epi32 (__mmask8 __U, __m256i __A, __m256i __B)
				5403	{
				5404	return (__m256i) __builtin_ia32_prorvd256_mask ((__v8si) __A,
				5405	(__v8si) __B,
				5406	(__v8si)
				5407	_mm256_setzero_si256 (),
				5408	(__mmask8) __U);
				5409	}
				5410
				5411	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5412	_mm_rorv_epi64 (__m128i __A, __m128i __B)
				5413	{
				5414	return (__m128i) __builtin_ia32_prorvq128_mask ((__v2di) __A,
				5415	(__v2di) __B,
				5416	(__v2di)
				5417	_mm_setzero_di (),
				5418	(__mmask8) -1);
				5419	}
				5420
				5421	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5422	_mm_mask_rorv_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				5423	__m128i __B)
				5424	{
				5425	return (__m128i) __builtin_ia32_prorvq128_mask ((__v2di) __A,
				5426	(__v2di) __B,
				5427	(__v2di) __W,
				5428	(__mmask8) __U);
				5429	}
				5430
				5431	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5432	_mm_maskz_rorv_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				5433	{
				5434	return (__m128i) __builtin_ia32_prorvq128_mask ((__v2di) __A,
				5435	(__v2di) __B,
				5436	(__v2di)
				5437	_mm_setzero_di (),
				5438	(__mmask8) __U);
				5439	}
				5440
				5441	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5442	_mm256_rorv_epi64 (__m256i __A, __m256i __B)
				5443	{
				5444	return (__m256i) __builtin_ia32_prorvq256_mask ((__v4di) __A,
				5445	(__v4di) __B,
				5446	(__v4di)
				5447	_mm256_setzero_si256 (),
				5448	(__mmask8) -1);
				5449	}
				5450
				5451	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5452	_mm256_mask_rorv_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				5453	__m256i __B)
				5454	{
				5455	return (__m256i) __builtin_ia32_prorvq256_mask ((__v4di) __A,
				5456	(__v4di) __B,
				5457	(__v4di) __W,
				5458	(__mmask8) __U);
				5459	}
				5460
				5461	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5462	_mm256_maskz_rorv_epi64 (__mmask8 __U, __m256i __A, __m256i __B)
				5463	{
				5464	return (__m256i) __builtin_ia32_prorvq256_mask ((__v4di) __A,
				5465	(__v4di) __B,
				5466	(__v4di)
				5467	_mm256_setzero_si256 (),
				5468	(__mmask8) __U);
				5469	}
				5470
Michael Zuckerman	431b0e1	2016-02-28 07:39:34 +0000	[diff] [blame]	5471	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5472	_mm_mask_sllv_epi64 (__m128i __W, __mmask8 __U, __m128i __X,
				5473	__m128i __Y)
				5474	{
				5475	return (__m128i) __builtin_ia32_psllv2di_mask ((__v2di) __X,
				5476	(__v2di) __Y,
				5477	(__v2di) __W,
				5478	(__mmask8) __U);
				5479	}
				5480
				5481	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5482	_mm_maskz_sllv_epi64 (__mmask8 __U, __m128i __X, __m128i __Y)
				5483	{
				5484	return (__m128i) __builtin_ia32_psllv2di_mask ((__v2di) __X,
				5485	(__v2di) __Y,
				5486	(__v2di)
				5487	_mm_setzero_di (),
				5488	(__mmask8) __U);
				5489	}
				5490
				5491	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5492	_mm256_mask_sllv_epi64 (__m256i __W, __mmask8 __U, __m256i __X,
				5493	__m256i __Y)
				5494	{
				5495	return (__m256i) __builtin_ia32_psllv4di_mask ((__v4di) __X,
				5496	(__v4di) __Y,
				5497	(__v4di) __W,
				5498	(__mmask8) __U);
				5499	}
				5500
				5501	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5502	_mm256_maskz_sllv_epi64 (__mmask8 __U, __m256i __X, __m256i __Y)
				5503	{
				5504	return (__m256i) __builtin_ia32_psllv4di_mask ((__v4di) __X,
				5505	(__v4di) __Y,
				5506	(__v4di)
				5507	_mm256_setzero_si256 (),
				5508	(__mmask8) __U);
				5509	}
				5510
				5511	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5512	_mm_mask_sllv_epi32 (__m128i __W, __mmask8 __U, __m128i __X,
				5513	__m128i __Y)
				5514	{
				5515	return (__m128i) __builtin_ia32_psllv4si_mask ((__v4si) __X,
				5516	(__v4si) __Y,
				5517	(__v4si) __W,
				5518	(__mmask8) __U);
				5519	}
				5520
				5521	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5522	_mm_maskz_sllv_epi32 (__mmask8 __U, __m128i __X, __m128i __Y)
				5523	{
				5524	return (__m128i) __builtin_ia32_psllv4si_mask ((__v4si) __X,
				5525	(__v4si) __Y,
				5526	(__v4si)
				5527	_mm_setzero_si128 (),
				5528	(__mmask8) __U);
				5529	}
				5530
				5531	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5532	_mm256_mask_sllv_epi32 (__m256i __W, __mmask8 __U, __m256i __X,
				5533	__m256i __Y)
				5534	{
				5535	return (__m256i) __builtin_ia32_psllv8si_mask ((__v8si) __X,
				5536	(__v8si) __Y,
				5537	(__v8si) __W,
				5538	(__mmask8) __U);
				5539	}
				5540
				5541	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5542	_mm256_maskz_sllv_epi32 (__mmask8 __U, __m256i __X, __m256i __Y)
				5543	{
				5544	return (__m256i) __builtin_ia32_psllv8si_mask ((__v8si) __X,
				5545	(__v8si) __Y,
				5546	(__v8si)
				5547	_mm256_setzero_si256 (),
				5548	(__mmask8) __U);
				5549	}
				5550
Michael Zuckerman	0165e76	2016-03-01 13:03:45 +0000	[diff] [blame]	5551
				5552
				5553	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5554	_mm_mask_srlv_epi64 (__m128i __W, __mmask8 __U, __m128i __X,
				5555	__m128i __Y)
				5556	{
				5557	return (__m128i) __builtin_ia32_psrlv2di_mask ((__v2di) __X,
				5558	(__v2di) __Y,
				5559	(__v2di) __W,
				5560	(__mmask8) __U);
				5561	}
				5562
				5563	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5564	_mm_maskz_srlv_epi64 (__mmask8 __U, __m128i __X, __m128i __Y)
				5565	{
				5566	return (__m128i) __builtin_ia32_psrlv2di_mask ((__v2di) __X,
				5567	(__v2di) __Y,
				5568	(__v2di)
				5569	_mm_setzero_di (),
				5570	(__mmask8) __U);
				5571	}
				5572
				5573	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5574	_mm256_mask_srlv_epi64 (__m256i __W, __mmask8 __U, __m256i __X,
				5575	__m256i __Y)
				5576	{
				5577	return (__m256i) __builtin_ia32_psrlv4di_mask ((__v4di) __X,
				5578	(__v4di) __Y,
				5579	(__v4di) __W,
				5580	(__mmask8) __U);
				5581	}
				5582
				5583	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5584	_mm256_maskz_srlv_epi64 (__mmask8 __U, __m256i __X, __m256i __Y)
				5585	{
				5586	return (__m256i) __builtin_ia32_psrlv4di_mask ((__v4di) __X,
				5587	(__v4di) __Y,
				5588	(__v4di)
				5589	_mm256_setzero_si256 (),
				5590	(__mmask8) __U);
				5591	}
				5592
				5593	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5594	_mm_mask_srlv_epi32 (__m128i __W, __mmask8 __U, __m128i __X,
				5595	__m128i __Y)
				5596	{
				5597	return (__m128i) __builtin_ia32_psrlv4si_mask ((__v4si) __X,
				5598	(__v4si) __Y,
				5599	(__v4si) __W,
				5600	(__mmask8) __U);
				5601	}
				5602
				5603	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5604	_mm_maskz_srlv_epi32 (__mmask8 __U, __m128i __X, __m128i __Y)
				5605	{
				5606	return (__m128i) __builtin_ia32_psrlv4si_mask ((__v4si) __X,
				5607	(__v4si) __Y,
				5608	(__v4si)
				5609	_mm_setzero_si128 (),
				5610	(__mmask8) __U);
				5611	}
				5612
				5613	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5614	_mm256_mask_srlv_epi32 (__m256i __W, __mmask8 __U, __m256i __X,
				5615	__m256i __Y)
				5616	{
				5617	return (__m256i) __builtin_ia32_psrlv8si_mask ((__v8si) __X,
				5618	(__v8si) __Y,
				5619	(__v8si) __W,
				5620	(__mmask8) __U);
				5621	}
				5622
				5623	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5624	_mm256_maskz_srlv_epi32 (__mmask8 __U, __m256i __X, __m256i __Y)
				5625	{
				5626	return (__m256i) __builtin_ia32_psrlv8si_mask ((__v8si) __X,
				5627	(__v8si) __Y,
				5628	(__v8si)
				5629	_mm256_setzero_si256 (),
				5630	(__mmask8) __U);
				5631	}
				5632
Michael Zuckerman	d176d74	2016-03-01 17:49:03 +0000	[diff] [blame]	5633
				5634
				5635	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5636	_mm_mask_srl_epi32 (__m128i __W, __mmask8 __U, __m128i __A,
				5637	__m128i __B)
				5638	{
				5639	return (__m128i) __builtin_ia32_psrld128_mask ((__v4si) __A,
				5640	(__v4si) __B,
				5641	(__v4si) __W,
				5642	(__mmask8) __U);
				5643	}
				5644
				5645	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5646	_mm_maskz_srl_epi32 (__mmask8 __U, __m128i __A, __m128i __B)
				5647	{
				5648	return (__m128i) __builtin_ia32_psrld128_mask ((__v4si) __A,
				5649	(__v4si) __B,
				5650	(__v4si)
				5651	_mm_setzero_si128 (),
				5652	(__mmask8) __U);
				5653	}
				5654
				5655	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5656	_mm256_mask_srl_epi32 (__m256i __W, __mmask8 __U, __m256i __A,
				5657	__m128i __B)
				5658	{
				5659	return (__m256i) __builtin_ia32_psrld256_mask ((__v8si) __A,
				5660	(__v4si) __B,
				5661	(__v8si) __W,
				5662	(__mmask8) __U);
				5663	}
				5664
				5665	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5666	_mm256_maskz_srl_epi32 (__mmask8 __U, __m256i __A, __m128i __B)
				5667	{
				5668	return (__m256i) __builtin_ia32_psrld256_mask ((__v8si) __A,
				5669	(__v4si) __B,
				5670	(__v8si)
				5671	_mm256_setzero_si256 (),
				5672	(__mmask8) __U);
				5673	}
				5674
				5675	#define _mm_mask_srli_epi32( __W, __U, __A, __imm) __extension__ ({ \
				5676	__builtin_ia32_psrldi128_mask ((__v4si)( __A),( __imm),\
				5677	(__v4si)( __W),\
				5678	(__mmask8)( __U));\
				5679	})
				5680
				5681	#define _mm_maskz_srli_epi32( __U, __A, __imm) __extension__ ({ \
				5682	__builtin_ia32_psrldi128_mask ((__v4si)( __A),( __imm),\
				5683	(__v4si)\
				5684	_mm_setzero_si128 (),\
				5685	(__mmask8)( __U));\
				5686	})
				5687
				5688	#define _mm256_mask_srli_epi32( __W, __U, __A, __imm) __extension__ ({ \
				5689	__builtin_ia32_psrldi256_mask ((__v8si)( __A),( __imm),\
				5690	(__v8si)( __W),\
				5691	(__mmask8)( __U));\
				5692	})
				5693
				5694	#define _mm256_maskz_srli_epi32( __U, __A, __imm) __extension__ ({ \
				5695	__builtin_ia32_psrldi256_mask ((__v8si)( __A),( __imm),\
				5696	(__v8si)\
				5697	_mm256_setzero_si256 (),\
				5698	(__mmask8)( __U));\
				5699	})
				5700
				5701	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5702	_mm_mask_srl_epi64 (__m128i __W, __mmask8 __U, __m128i __A,
				5703	__m128i __B)
				5704	{
				5705	return (__m128i) __builtin_ia32_psrlq128_mask ((__v2di) __A,
				5706	(__v2di) __B,
				5707	(__v2di) __W,
				5708	(__mmask8) __U);
				5709	}
				5710
				5711	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5712	_mm_maskz_srl_epi64 (__mmask8 __U, __m128i __A, __m128i __B)
				5713	{
				5714	return (__m128i) __builtin_ia32_psrlq128_mask ((__v2di) __A,
				5715	(__v2di) __B,
				5716	(__v2di)
				5717	_mm_setzero_di (),
				5718	(__mmask8) __U);
				5719	}
				5720
				5721	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5722	_mm256_mask_srl_epi64 (__m256i __W, __mmask8 __U, __m256i __A,
				5723	__m128i __B)
				5724	{
				5725	return (__m256i) __builtin_ia32_psrlq256_mask ((__v4di) __A,
				5726	(__v2di) __B,
				5727	(__v4di) __W,
				5728	(__mmask8) __U);
				5729	}
				5730
				5731	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5732	_mm256_maskz_srl_epi64 (__mmask8 __U, __m256i __A, __m128i __B)
				5733	{
				5734	return (__m256i) __builtin_ia32_psrlq256_mask ((__v4di) __A,
				5735	(__v2di) __B,
				5736	(__v4di)
				5737	_mm256_setzero_si256 (),
				5738	(__mmask8) __U);
				5739	}
				5740
				5741	#define _mm_mask_srli_epi64( __W, __U, __A, __imm) __extension__ ({ \
				5742	__builtin_ia32_psrlqi128_mask ((__v2di)( __A),( __imm),\
				5743	(__v2di)( __W),\
				5744	(__mmask8)( __U));\
				5745	})
				5746
				5747	#define _mm_maskz_srli_epi64( __U, __A, __imm) __extension__ ({ \
				5748	__builtin_ia32_psrlqi128_mask ((__v2di)( __A),( __imm),\
				5749	(__v2di)\
				5750	_mm_setzero_si128 (),\
				5751	(__mmask8)( __U));\
				5752	})
				5753
				5754	#define _mm256_mask_srli_epi64( __W, __U, __A, __imm) __extension__ ({ \
				5755	__builtin_ia32_psrlqi256_mask ((__v4di)( __A),( __imm),\
				5756	(__v4di)( __W),\
				5757	(__mmask8)( __U));\
				5758	})
				5759
				5760	#define _mm256_maskz_srli_epi64( __U, __A, __imm) __extension__ ({ \
				5761	__builtin_ia32_psrlqi256_mask ((__v4di)( __A),( __imm),\
				5762	(__v4di)\
				5763	_mm256_setzero_si256 (),\
				5764	(__mmask8)( __U));\
				5765	})
				5766
Michael Zuckerman	d15c95a	2016-03-02 09:05:46 +0000	[diff] [blame]	5767	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5768	_mm_mask_srav_epi32 (__m128i __W, __mmask8 __U, __m128i __X,
				5769	__m128i __Y)
				5770	{
				5771	return (__m128i) __builtin_ia32_psrav4si_mask ((__v4si) __X,
				5772	(__v4si) __Y,
				5773	(__v4si) __W,
				5774	(__mmask8) __U);
				5775	}
				5776
				5777	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5778	_mm_maskz_srav_epi32 (__mmask8 __U, __m128i __X, __m128i __Y)
				5779	{
				5780	return (__m128i) __builtin_ia32_psrav4si_mask ((__v4si) __X,
				5781	(__v4si) __Y,
				5782	(__v4si)
				5783	_mm_setzero_si128 (),
				5784	(__mmask8) __U);
				5785	}
				5786
				5787	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5788	_mm256_mask_srav_epi32 (__m256i __W, __mmask8 __U, __m256i __X,
				5789	__m256i __Y)
				5790	{
				5791	return (__m256i) __builtin_ia32_psrav8si_mask ((__v8si) __X,
				5792	(__v8si) __Y,
				5793	(__v8si) __W,
				5794	(__mmask8) __U);
				5795	}
				5796
				5797	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5798	_mm256_maskz_srav_epi32 (__mmask8 __U, __m256i __X, __m256i __Y)
				5799	{
				5800	return (__m256i) __builtin_ia32_psrav8si_mask ((__v8si) __X,
				5801	(__v8si) __Y,
				5802	(__v8si)
				5803	_mm256_setzero_si256 (),
				5804	(__mmask8) __U);
				5805	}
				5806
				5807	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5808	_mm_srav_epi64 (__m128i __X, __m128i __Y)
				5809	{
				5810	return (__m128i) __builtin_ia32_psravq128_mask ((__v2di) __X,
				5811	(__v2di) __Y,
				5812	(__v2di)
				5813	_mm_setzero_di (),
				5814	(__mmask8) -1);
				5815	}
				5816
				5817	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5818	_mm_mask_srav_epi64 (__m128i __W, __mmask8 __U, __m128i __X,
				5819	__m128i __Y)
				5820	{
				5821	return (__m128i) __builtin_ia32_psravq128_mask ((__v2di) __X,
				5822	(__v2di) __Y,
				5823	(__v2di) __W,
				5824	(__mmask8) __U);
				5825	}
				5826
				5827	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5828	_mm_maskz_srav_epi64 (__mmask8 __U, __m128i __X, __m128i __Y)
				5829	{
				5830	return (__m128i) __builtin_ia32_psravq128_mask ((__v2di) __X,
				5831	(__v2di) __Y,
				5832	(__v2di)
				5833	_mm_setzero_di (),
				5834	(__mmask8) __U);
				5835	}
				5836
				5837	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5838	_mm256_srav_epi64 (__m256i __X, __m256i __Y)
				5839	{
				5840	return (__m256i) __builtin_ia32_psravq256_mask ((__v4di) __X,
				5841	(__v4di) __Y,
				5842	(__v4di)
				5843	_mm256_setzero_si256 (),
				5844	(__mmask8) -1);
				5845	}
				5846
				5847	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5848	_mm256_mask_srav_epi64 (__m256i __W, __mmask8 __U, __m256i __X,
				5849	__m256i __Y)
				5850	{
				5851	return (__m256i) __builtin_ia32_psravq256_mask ((__v4di) __X,
				5852	(__v4di) __Y,
				5853	(__v4di) __W,
				5854	(__mmask8) __U);
				5855	}
				5856
				5857	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5858	_mm256_maskz_srav_epi64 (__mmask8 __U, __m256i __X, __m256i __Y)
				5859	{
				5860	return (__m256i) __builtin_ia32_psravq256_mask ((__v4di) __X,
				5861	(__v4di) __Y,
				5862	(__v4di)
				5863	_mm256_setzero_si256 (),
				5864	(__mmask8) __U);
				5865	}
Michael Zuckerman	ffbb67a	2016-03-03 09:26:01 +0000	[diff] [blame]	5866
				5867
				5868
				5869	static __inline__ void __DEFAULT_FN_ATTRS
				5870	_mm_mask_store_epi32 (void *__P, __mmask8 __U, __m128i __A)
				5871	{
				5872	__builtin_ia32_movdqa32store128_mask ((__v4si *) __P,
				5873	(__v4si) __A,
				5874	(__mmask8) __U);
				5875	}
				5876
				5877	static __inline__ void __DEFAULT_FN_ATTRS
				5878	_mm256_mask_store_epi32 (void *__P, __mmask8 __U, __m256i __A)
				5879	{
				5880	__builtin_ia32_movdqa32store256_mask ((__v8si *) __P,
				5881	(__v8si) __A,
				5882	(__mmask8) __U);
				5883	}
				5884
				5885	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5886	_mm_mask_mov_epi64 (__m128i __W, __mmask8 __U, __m128i __A)
				5887	{
				5888	return (__m128i) __builtin_ia32_movdqa64_128_mask ((__v2di) __A,
				5889	(__v2di) __W,
				5890	(__mmask8) __U);
				5891	}
				5892
				5893	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5894	_mm_maskz_mov_epi64 (__mmask8 __U, __m128i __A)
				5895	{
				5896	return (__m128i) __builtin_ia32_movdqa64_128_mask ((__v2di) __A,
				5897	(__v2di)
				5898	_mm_setzero_di (),
				5899	(__mmask8) __U);
				5900	}
				5901
				5902	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5903	_mm256_mask_mov_epi64 (__m256i __W, __mmask8 __U, __m256i __A)
				5904	{
				5905	return (__m256i) __builtin_ia32_movdqa64_256_mask ((__v4di) __A,
				5906	(__v4di) __W,
				5907	(__mmask8) __U);
				5908	}
				5909
				5910	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5911	_mm256_maskz_mov_epi64 (__mmask8 __U, __m256i __A)
				5912	{
				5913	return (__m256i) __builtin_ia32_movdqa64_256_mask ((__v4di) __A,
				5914	(__v4di)
				5915	_mm256_setzero_si256 (),
				5916	(__mmask8) __U);
				5917	}
				5918
				5919	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5920	_mm_mask_load_epi64 (__m128i __W, __mmask8 __U, void const *__P)
				5921	{
				5922	return (__m128i) __builtin_ia32_movdqa64load128_mask ((__v2di *) __P,
				5923	(__v2di) __W,
				5924	(__mmask8)
				5925	__U);
				5926	}
				5927
				5928	static __inline__ __m128i __DEFAULT_FN_ATTRS
				5929	_mm_maskz_load_epi64 (__mmask8 __U, void const *__P)
				5930	{
				5931	return (__m128i) __builtin_ia32_movdqa64load128_mask ((__v2di *) __P,
				5932	(__v2di)
				5933	_mm_setzero_di (),
				5934	(__mmask8)
				5935	__U);
				5936	}
				5937
				5938	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5939	_mm256_mask_load_epi64 (__m256i __W, __mmask8 __U, void const *__P)
				5940	{
				5941	return (__m256i) __builtin_ia32_movdqa64load256_mask ((__v4di *) __P,
				5942	(__v4di) __W,
				5943	(__mmask8)
				5944	__U);
				5945	}
				5946
				5947	static __inline__ __m256i __DEFAULT_FN_ATTRS
				5948	_mm256_maskz_load_epi64 (__mmask8 __U, void const *__P)
				5949	{
				5950	return (__m256i) __builtin_ia32_movdqa64load256_mask ((__v4di *) __P,
				5951	(__v4di)
				5952	_mm256_setzero_si256 (),
				5953	(__mmask8)
				5954	__U);
				5955	}
				5956
				5957	static __inline__ void __DEFAULT_FN_ATTRS
				5958	_mm_mask_store_epi64 (void *__P, __mmask8 __U, __m128i __A)
				5959	{
				5960	__builtin_ia32_movdqa64store128_mask ((__v2di *) __P,
				5961	(__v2di) __A,
				5962	(__mmask8) __U);
				5963	}
				5964
				5965	static __inline__ void __DEFAULT_FN_ATTRS
				5966	_mm256_mask_store_epi64 (void *__P, __mmask8 __U, __m256i __A)
				5967	{
				5968	__builtin_ia32_movdqa64store256_mask ((__v4di *) __P,
				5969	(__v4di) __A,
				5970	(__mmask8) __U);
				5971	}
				5972
Michael Zuckerman	0d67e4b	2016-03-03 13:43:05 +0000	[diff] [blame]	5973	static __inline__ __m128d __DEFAULT_FN_ATTRS
				5974	_mm_mask_movedup_pd (__m128d __W, __mmask8 __U, __m128d __A)
				5975	{
				5976	return (__m128d) __builtin_ia32_movddup128_mask ((__v2df) __A,
				5977	(__v2df) __W,
				5978	(__mmask8) __U);
				5979	}
				5980
				5981	static __inline__ __m128d __DEFAULT_FN_ATTRS
				5982	_mm_maskz_movedup_pd (__mmask8 __U, __m128d __A)
				5983	{
				5984	return (__m128d) __builtin_ia32_movddup128_mask ((__v2df) __A,
				5985	(__v2df)
				5986	_mm_setzero_pd (),
				5987	(__mmask8) __U);
				5988	}
				5989
				5990	static __inline__ __m256d __DEFAULT_FN_ATTRS
				5991	_mm256_mask_movedup_pd (__m256d __W, __mmask8 __U, __m256d __A)
				5992	{
				5993	return (__m256d) __builtin_ia32_movddup256_mask ((__v4df) __A,
				5994	(__v4df) __W,
				5995	(__mmask8) __U);
				5996	}
				5997
				5998	static __inline__ __m256d __DEFAULT_FN_ATTRS
				5999	_mm256_maskz_movedup_pd (__mmask8 __U, __m256d __A)
				6000	{
				6001	return (__m256d) __builtin_ia32_movddup256_mask ((__v4df) __A,
				6002	(__v4df)
				6003	_mm256_setzero_pd (),
				6004	(__mmask8) __U);
				6005	}
Michael Zuckerman	ffbb67a	2016-03-03 09:26:01 +0000	[diff] [blame]	6006
Michael Zuckerman	912be16	2016-03-07 08:29:10 +0000	[diff] [blame]	6007
				6008	#define _mm_mask_set1_epi32( __O, __M, __A) __extension__ ({ \
				6009	__builtin_ia32_pbroadcastd128_gpr_mask (__A, (__v4si)( __O),\
				6010	( __M));\
				6011	})
				6012
				6013	#define _mm_maskz_set1_epi32( __M, __A) __extension__ ({ \
				6014	__builtin_ia32_pbroadcastd128_gpr_mask (__A,\
				6015	(__v4si)\
				6016	_mm_setzero_si128 (),\
				6017	( __M));\
				6018	})
				6019
				6020	#define _mm256_mask_set1_epi32( __O, __M, __A) __extension__ ({ \
				6021	__builtin_ia32_pbroadcastd256_gpr_mask (__A, (__v8si)( __O),\
				6022	( __M));\
				6023	})
				6024
				6025	#define _mm256_maskz_set1_epi32( __M, __A) __extension__ ({ \
				6026	__builtin_ia32_pbroadcastd256_gpr_mask (__A,\
				6027	(__v8si)\
				6028	_mm256_setzero_si256 (),\
				6029	( __M));\
				6030	})
				6031
				6032	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6033	_mm_mask_set1_epi64 (__m128i __O, __mmask8 __M, long long __A)
				6034	{
				6035	return (__m128i) __builtin_ia32_pbroadcastq128_gpr_mask (__A, (__v2di) __O,
				6036	__M);
				6037	}
				6038
				6039	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6040	_mm_maskz_set1_epi64 (__mmask8 __M, long long __A)
				6041	{
				6042	return (__m128i) __builtin_ia32_pbroadcastq128_gpr_mask (__A,
				6043	(__v2di)
				6044	_mm_setzero_si128 (),
				6045	__M);
				6046	}
				6047
				6048	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6049	_mm256_mask_set1_epi64 (__m256i __O, __mmask8 __M, long long __A)
				6050	{
				6051	return (__m256i) __builtin_ia32_pbroadcastq256_gpr_mask (__A, (__v4di) __O,
				6052	__M);
				6053	}
				6054
				6055	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6056	_mm256_maskz_set1_epi64 (__mmask8 __M, long long __A)
				6057	{
				6058	return (__m256i) __builtin_ia32_pbroadcastq256_gpr_mask (__A,
				6059	(__v4di)
				6060	_mm256_setzero_si256 (),
				6061	__M);
				6062	}
Michael Zuckerman	def7875	2016-03-28 12:23:09 +0000	[diff] [blame]	6063
				6064	#define _mm_fixupimm_pd( __A, __B, __C, __imm) __extension__ ({ \
				6065	__builtin_ia32_fixupimmpd128_mask ((__v2df)( __A),\
				6066	(__v2df)( __B),\
				6067	(__v2di)( __C),\
				6068	( __imm),\
				6069	(__mmask8) -1);\
				6070	})
				6071
				6072	#define _mm_mask_fixupimm_pd( __A, __U, __B, __C, __imm) __extension__ ({ \
				6073	__builtin_ia32_fixupimmpd128_mask ((__v2df)( __A),\
				6074	(__v2df)( __B),\
				6075	(__v2di)( __C),\
				6076	( __imm),\
				6077	(__mmask8)( __U));\
				6078	})
				6079
				6080	#define _mm_maskz_fixupimm_pd( __U, __A, __B, __C, __imm) __extension__ ({ \
				6081	__builtin_ia32_fixupimmpd128_maskz ((__v2df)( __A),\
				6082	(__v2df)( __B),\
				6083	(__v2di)( __C),\
				6084	( __imm),\
				6085	(__mmask8)( __U));\
				6086	})
				6087
				6088	#define _mm256_fixupimm_pd( __A, __B, __C, __imm) __extension__ ({ \
				6089	__builtin_ia32_fixupimmpd256_mask ((__v4df)( __A),\
				6090	(__v4df)( __B),\
				6091	(__v4di)( __C),\
				6092	( __imm),\
				6093	(__mmask8) -1);\
				6094	})
				6095
				6096	#define _mm256_mask_fixupimm_pd( __A, __U, __B, __C, __imm) __extension__ ({ \
				6097	__builtin_ia32_fixupimmpd256_mask ((__v4df)( __A),\
				6098	(__v4df)( __B),\
				6099	(__v4di)( __C),\
				6100	( __imm),\
				6101	(__mmask8)( __U));\
				6102	})
				6103
				6104	#define _mm256_maskz_fixupimm_pd( __U, __A, __B, __C, __imm) __extension__ ({ \
				6105	__builtin_ia32_fixupimmpd256_maskz ((__v4df)( __A),\
				6106	(__v4df)( __B),\
				6107	(__v4di)( __C),\
				6108	( __imm),\
				6109	(__mmask8)( __U));\
				6110	})
				6111
				6112	#define _mm_fixupimm_ps( __A, __B, __C, __imm) __extension__ ({ \
				6113	__builtin_ia32_fixupimmps128_mask ((__v4sf)( __A),\
				6114	(__v4sf)( __B),\
				6115	(__v4si)( __C),\
				6116	( __imm),\
				6117	(__mmask8) -1);\
				6118	})
				6119
				6120	#define _mm_mask_fixupimm_ps( __A, __U, __B, __C, __imm) __extension__ ({ \
				6121	__builtin_ia32_fixupimmps128_mask ((__v4sf)( __A),\
				6122	(__v4sf)( __B),\
				6123	(__v4si)( __C),\
				6124	( __imm),\
				6125	(__mmask8)( __U));\
				6126	})
				6127
				6128	#define _mm_maskz_fixupimm_ps( __U, __A, __B, __C, __imm) __extension__ ({ \
				6129	__builtin_ia32_fixupimmps128_maskz ((__v4sf)( __A),\
				6130	(__v4sf)( __B),\
				6131	(__v4si)( __C),\
				6132	( __imm),\
				6133	(__mmask8)( __U));\
				6134	})
				6135
				6136	#define _mm256_fixupimm_ps( __A, __B, __C, __imm) __extension__ ({ \
				6137	__builtin_ia32_fixupimmps256_mask ((__v8sf)( __A),\
				6138	(__v8sf)( __B),\
				6139	(__v8si)( __C),\
				6140	( __imm),\
				6141	(__mmask8) -1);\
				6142	})
				6143
				6144	#define _mm256_mask_fixupimm_ps( __A, __U, __B, __C, __imm) __extension__ ({ \
				6145	__builtin_ia32_fixupimmps256_mask ((__v8sf)( __A),\
				6146	(__v8sf)( __B),\
				6147	(__v8si)( __C),\
				6148	( __imm),\
				6149	(__mmask8)( __U));\
				6150	})
				6151
				6152	#define _mm256_maskz_fixupimm_ps( __U, __A, __B, __C, __imm) __extension__ ({ \
				6153	__builtin_ia32_fixupimmps256_maskz ((__v8sf)( __A),\
				6154	(__v8sf)( __B),\
				6155	(__v8si)( __C),\
				6156	( __imm),\
				6157	(__mmask8)( __U));\
				6158	})
				6159
				6160	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6161	_mm_mask_load_pd (__m128d __W, __mmask8 __U, void const *__P)
				6162	{
				6163	return (__m128d) __builtin_ia32_loadapd128_mask ((__v2df *) __P,
				6164	(__v2df) __W,
				6165	(__mmask8) __U);
				6166	}
				6167
				6168	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6169	_mm_maskz_load_pd (__mmask8 __U, void const *__P)
				6170	{
				6171	return (__m128d) __builtin_ia32_loadapd128_mask ((__v2df *) __P,
				6172	(__v2df)
				6173	_mm_setzero_pd (),
				6174	(__mmask8) __U);
				6175	}
				6176
				6177	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6178	_mm256_mask_load_pd (__m256d __W, __mmask8 __U, void const *__P)
				6179	{
				6180	return (__m256d) __builtin_ia32_loadapd256_mask ((__v4df *) __P,
				6181	(__v4df) __W,
				6182	(__mmask8) __U);
				6183	}
				6184
				6185	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6186	_mm256_maskz_load_pd (__mmask8 __U, void const *__P)
				6187	{
				6188	return (__m256d) __builtin_ia32_loadapd256_mask ((__v4df *) __P,
				6189	(__v4df)
				6190	_mm256_setzero_pd (),
				6191	(__mmask8) __U);
				6192	}
				6193
				6194	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6195	_mm_mask_load_ps (__m128 __W, __mmask8 __U, void const *__P)
				6196	{
				6197	return (__m128) __builtin_ia32_loadaps128_mask ((__v4sf *) __P,
				6198	(__v4sf) __W,
				6199	(__mmask8) __U);
				6200	}
				6201
				6202	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6203	_mm_maskz_load_ps (__mmask8 __U, void const *__P)
				6204	{
				6205	return (__m128) __builtin_ia32_loadaps128_mask ((__v4sf *) __P,
				6206	(__v4sf)
				6207	_mm_setzero_ps (),
				6208	(__mmask8) __U);
				6209	}
				6210
				6211	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6212	_mm256_mask_load_ps (__m256 __W, __mmask8 __U, void const *__P)
				6213	{
				6214	return (__m256) __builtin_ia32_loadaps256_mask ((__v8sf *) __P,
				6215	(__v8sf) __W,
				6216	(__mmask8) __U);
				6217	}
				6218
				6219	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6220	_mm256_maskz_load_ps (__mmask8 __U, void const *__P)
				6221	{
				6222	return (__m256) __builtin_ia32_loadaps256_mask ((__v8sf *) __P,
				6223	(__v8sf)
				6224	_mm256_setzero_ps (),
				6225	(__mmask8) __U);
				6226	}
				6227
				6228	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6229	_mm_mask_loadu_epi64 (__m128i __W, __mmask8 __U, void const *__P)
				6230	{
				6231	return (__m128i) __builtin_ia32_loaddqudi128_mask ((__v2di *) __P,
				6232	(__v2di) __W,
				6233	(__mmask8) __U);
				6234	}
				6235
				6236	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6237	_mm_maskz_loadu_epi64 (__mmask8 __U, void const *__P)
				6238	{
				6239	return (__m128i) __builtin_ia32_loaddqudi128_mask ((__v2di *) __P,
				6240	(__v2di)
				6241	_mm_setzero_si128 (),
				6242	(__mmask8) __U);
				6243	}
				6244
				6245	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6246	_mm256_mask_loadu_epi64 (__m256i __W, __mmask8 __U, void const *__P)
				6247	{
				6248	return (__m256i) __builtin_ia32_loaddqudi256_mask ((__v4di *) __P,
				6249	(__v4di) __W,
				6250	(__mmask8) __U);
				6251	}
				6252
				6253	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6254	_mm256_maskz_loadu_epi64 (__mmask8 __U, void const *__P)
				6255	{
				6256	return (__m256i) __builtin_ia32_loaddqudi256_mask ((__v4di *) __P,
				6257	(__v4di)
				6258	_mm256_setzero_si256 (),
				6259	(__mmask8) __U);
				6260	}
				6261
				6262	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6263	_mm_mask_loadu_epi32 (__m128i __W, __mmask8 __U, void const *__P)
				6264	{
				6265	return (__m128i) __builtin_ia32_loaddqusi128_mask ((__v4si *) __P,
				6266	(__v4si) __W,
				6267	(__mmask8) __U);
				6268	}
				6269
				6270	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6271	_mm_maskz_loadu_epi32 (__mmask8 __U, void const *__P)
				6272	{
				6273	return (__m128i) __builtin_ia32_loaddqusi128_mask ((__v4si *) __P,
				6274	(__v4si)
				6275	_mm_setzero_si128 (),
				6276	(__mmask8) __U);
				6277	}
				6278
				6279	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6280	_mm256_mask_loadu_epi32 (__m256i __W, __mmask8 __U, void const *__P)
				6281	{
				6282	return (__m256i) __builtin_ia32_loaddqusi256_mask ((__v8si *) __P,
				6283	(__v8si) __W,
				6284	(__mmask8) __U);
				6285	}
				6286
				6287	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6288	_mm256_maskz_loadu_epi32 (__mmask8 __U, void const *__P)
				6289	{
				6290	return (__m256i) __builtin_ia32_loaddqusi256_mask ((__v8si *) __P,
				6291	(__v8si)
				6292	_mm256_setzero_si256 (),
				6293	(__mmask8) __U);
				6294	}
				6295
				6296	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6297	_mm_mask_loadu_pd (__m128d __W, __mmask8 __U, void const *__P)
				6298	{
				6299	return (__m128d) __builtin_ia32_loadupd128_mask ((__v2df *) __P,
				6300	(__v2df) __W,
				6301	(__mmask8) __U);
				6302	}
				6303
				6304	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6305	_mm_maskz_loadu_pd (__mmask8 __U, void const *__P)
				6306	{
				6307	return (__m128d) __builtin_ia32_loadupd128_mask ((__v2df *) __P,
				6308	(__v2df)
				6309	_mm_setzero_pd (),
				6310	(__mmask8) __U);
				6311	}
				6312
				6313	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6314	_mm256_mask_loadu_pd (__m256d __W, __mmask8 __U, void const *__P)
				6315	{
				6316	return (__m256d) __builtin_ia32_loadupd256_mask ((__v4df *) __P,
				6317	(__v4df) __W,
				6318	(__mmask8) __U);
				6319	}
				6320
				6321	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6322	_mm256_maskz_loadu_pd (__mmask8 __U, void const *__P)
				6323	{
				6324	return (__m256d) __builtin_ia32_loadupd256_mask ((__v4df *) __P,
				6325	(__v4df)
				6326	_mm256_setzero_pd (),
				6327	(__mmask8) __U);
				6328	}
				6329
				6330	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6331	_mm_mask_loadu_ps (__m128 __W, __mmask8 __U, void const *__P)
				6332	{
				6333	return (__m128) __builtin_ia32_loadups128_mask ((__v4sf *) __P,
				6334	(__v4sf) __W,
				6335	(__mmask8) __U);
				6336	}
				6337
				6338	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6339	_mm_maskz_loadu_ps (__mmask8 __U, void const *__P)
				6340	{
				6341	return (__m128) __builtin_ia32_loadups128_mask ((__v4sf *) __P,
				6342	(__v4sf)
				6343	_mm_setzero_ps (),
				6344	(__mmask8) __U);
				6345	}
				6346
				6347	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6348	_mm256_mask_loadu_ps (__m256 __W, __mmask8 __U, void const *__P)
				6349	{
				6350	return (__m256) __builtin_ia32_loadups256_mask ((__v8sf *) __P,
				6351	(__v8sf) __W,
				6352	(__mmask8) __U);
				6353	}
				6354
				6355	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6356	_mm256_maskz_loadu_ps (__mmask8 __U, void const *__P)
				6357	{
				6358	return (__m256) __builtin_ia32_loadups256_mask ((__v8sf *) __P,
				6359	(__v8sf)
				6360	_mm256_setzero_ps (),
				6361	(__mmask8) __U);
				6362	}
Michael Zuckerman	fa7ccc5	2016-04-10 10:51:04 +0000	[diff] [blame]	6363
				6364	static __inline__ void __DEFAULT_FN_ATTRS
				6365	_mm_mask_store_pd (void *__P, __mmask8 __U, __m128d __A)
				6366	{
				6367	__builtin_ia32_storeapd128_mask ((__v2df *) __P,
				6368	(__v2df) __A,
				6369	(__mmask8) __U);
				6370	}
				6371
				6372	static __inline__ void __DEFAULT_FN_ATTRS
				6373	_mm256_mask_store_pd (void *__P, __mmask8 __U, __m256d __A)
				6374	{
				6375	__builtin_ia32_storeapd256_mask ((__v4df *) __P,
				6376	(__v4df) __A,
				6377	(__mmask8) __U);
				6378	}
				6379
				6380	static __inline__ void __DEFAULT_FN_ATTRS
				6381	_mm_mask_store_ps (void *__P, __mmask8 __U, __m128 __A)
				6382	{
				6383	__builtin_ia32_storeaps128_mask ((__v4sf *) __P,
				6384	(__v4sf) __A,
				6385	(__mmask8) __U);
				6386	}
				6387
				6388	static __inline__ void __DEFAULT_FN_ATTRS
				6389	_mm256_mask_store_ps (void *__P, __mmask8 __U, __m256 __A)
				6390	{
				6391	__builtin_ia32_storeaps256_mask ((__v8sf *) __P,
				6392	(__v8sf) __A,
				6393	(__mmask8) __U);
				6394	}
				6395
				6396	static __inline__ void __DEFAULT_FN_ATTRS
				6397	_mm_mask_storeu_epi64 (void *__P, __mmask8 __U, __m128i __A)
				6398	{
				6399	__builtin_ia32_storedqudi128_mask ((__v2di *) __P,
				6400	(__v2di) __A,
				6401	(__mmask8) __U);
				6402	}
				6403
				6404	static __inline__ void __DEFAULT_FN_ATTRS
				6405	_mm256_mask_storeu_epi64 (void *__P, __mmask8 __U, __m256i __A)
				6406	{
				6407	__builtin_ia32_storedqudi256_mask ((__v4di *) __P,
				6408	(__v4di) __A,
				6409	(__mmask8) __U);
				6410	}
				6411
				6412	static __inline__ void __DEFAULT_FN_ATTRS
				6413	_mm_mask_storeu_epi32 (void *__P, __mmask8 __U, __m128i __A)
				6414	{
				6415	__builtin_ia32_storedqusi128_mask ((__v4si *) __P,
				6416	(__v4si) __A,
				6417	(__mmask8) __U);
				6418	}
				6419
				6420	static __inline__ void __DEFAULT_FN_ATTRS
				6421	_mm256_mask_storeu_epi32 (void *__P, __mmask8 __U, __m256i __A)
				6422	{
				6423	__builtin_ia32_storedqusi256_mask ((__v8si *) __P,
				6424	(__v8si) __A,
				6425	(__mmask8) __U);
				6426	}
				6427
				6428	static __inline__ void __DEFAULT_FN_ATTRS
				6429	_mm_mask_storeu_pd (void *__P, __mmask8 __U, __m128d __A)
				6430	{
				6431	__builtin_ia32_storeupd128_mask ((__v2df *) __P,
				6432	(__v2df) __A,
				6433	(__mmask8) __U);
				6434	}
				6435
				6436	static __inline__ void __DEFAULT_FN_ATTRS
				6437	_mm256_mask_storeu_pd (void *__P, __mmask8 __U, __m256d __A)
				6438	{
				6439	__builtin_ia32_storeupd256_mask ((__v4df *) __P,
				6440	(__v4df) __A,
				6441	(__mmask8) __U);
				6442	}
				6443
				6444	static __inline__ void __DEFAULT_FN_ATTRS
				6445	_mm_mask_storeu_ps (void *__P, __mmask8 __U, __m128 __A)
				6446	{
				6447	__builtin_ia32_storeups128_mask ((__v4sf *) __P,
				6448	(__v4sf) __A,
				6449	(__mmask8) __U);
				6450	}
				6451
				6452	static __inline__ void __DEFAULT_FN_ATTRS
				6453	_mm256_mask_storeu_ps (void *__P, __mmask8 __U, __m256 __A)
				6454	{
				6455	__builtin_ia32_storeups256_mask ((__v8sf *) __P,
				6456	(__v8sf) __A,
				6457	(__mmask8) __U);
				6458	}
				6459
Michael Zuckerman	cdd54c8	2016-04-10 12:54:23 +0000	[diff] [blame^]	6460
				6461	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6462	_mm_mask_unpackhi_pd (__m128d __W, __mmask8 __U, __m128d __A,
				6463	__m128d __B)
				6464	{
				6465	return (__m128d) __builtin_ia32_unpckhpd128_mask ((__v2df) __A,
				6466	(__v2df) __B,
				6467	(__v2df) __W,
				6468	(__mmask8) __U);
				6469	}
				6470
				6471	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6472	_mm_maskz_unpackhi_pd (__mmask8 __U, __m128d __A, __m128d __B)
				6473	{
				6474	return (__m128d) __builtin_ia32_unpckhpd128_mask ((__v2df) __A,
				6475	(__v2df) __B,
				6476	(__v2df)
				6477	_mm_setzero_pd (),
				6478	(__mmask8) __U);
				6479	}
				6480
				6481	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6482	_mm256_mask_unpackhi_pd (__m256d __W, __mmask8 __U, __m256d __A,
				6483	__m256d __B)
				6484	{
				6485	return (__m256d) __builtin_ia32_unpckhpd256_mask ((__v4df) __A,
				6486	(__v4df) __B,
				6487	(__v4df) __W,
				6488	(__mmask8) __U);
				6489	}
				6490
				6491	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6492	_mm256_maskz_unpackhi_pd (__mmask8 __U, __m256d __A, __m256d __B)
				6493	{
				6494	return (__m256d) __builtin_ia32_unpckhpd256_mask ((__v4df) __A,
				6495	(__v4df) __B,
				6496	(__v4df)
				6497	_mm256_setzero_pd (),
				6498	(__mmask8) __U);
				6499	}
				6500
				6501	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6502	_mm_mask_unpackhi_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)
				6503	{
				6504	return (__m128) __builtin_ia32_unpckhps128_mask ((__v4sf) __A,
				6505	(__v4sf) __B,
				6506	(__v4sf) __W,
				6507	(__mmask8) __U);
				6508	}
				6509
				6510	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6511	_mm_maskz_unpackhi_ps (__mmask8 __U, __m128 __A, __m128 __B)
				6512	{
				6513	return (__m128) __builtin_ia32_unpckhps128_mask ((__v4sf) __A,
				6514	(__v4sf) __B,
				6515	(__v4sf)
				6516	_mm_setzero_ps (),
				6517	(__mmask8) __U);
				6518	}
				6519
				6520	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6521	_mm256_mask_unpackhi_ps (__m256 __W, __mmask8 __U, __m256 __A,
				6522	__m256 __B)
				6523	{
				6524	return (__m256) __builtin_ia32_unpckhps256_mask ((__v8sf) __A,
				6525	(__v8sf) __B,
				6526	(__v8sf) __W,
				6527	(__mmask8) __U);
				6528	}
				6529
				6530	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6531	_mm256_maskz_unpackhi_ps (__mmask8 __U, __m256 __A, __m256 __B)
				6532	{
				6533	return (__m256) __builtin_ia32_unpckhps256_mask ((__v8sf) __A,
				6534	(__v8sf) __B,
				6535	(__v8sf)
				6536	_mm256_setzero_ps (),
				6537	(__mmask8) __U);
				6538	}
				6539
				6540	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6541	_mm_mask_unpacklo_pd (__m128d __W, __mmask8 __U, __m128d __A,
				6542	__m128d __B)
				6543	{
				6544	return (__m128d) __builtin_ia32_unpcklpd128_mask ((__v2df) __A,
				6545	(__v2df) __B,
				6546	(__v2df) __W,
				6547	(__mmask8) __U);
				6548	}
				6549
				6550	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6551	_mm_maskz_unpacklo_pd (__mmask8 __U, __m128d __A, __m128d __B)
				6552	{
				6553	return (__m128d) __builtin_ia32_unpcklpd128_mask ((__v2df) __A,
				6554	(__v2df) __B,
				6555	(__v2df)
				6556	_mm_setzero_pd (),
				6557	(__mmask8) __U);
				6558	}
				6559
				6560	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6561	_mm256_mask_unpacklo_pd (__m256d __W, __mmask8 __U, __m256d __A,
				6562	__m256d __B)
				6563	{
				6564	return (__m256d) __builtin_ia32_unpcklpd256_mask ((__v4df) __A,
				6565	(__v4df) __B,
				6566	(__v4df) __W,
				6567	(__mmask8) __U);
				6568	}
				6569
				6570	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6571	_mm256_maskz_unpacklo_pd (__mmask8 __U, __m256d __A, __m256d __B)
				6572	{
				6573	return (__m256d) __builtin_ia32_unpcklpd256_mask ((__v4df) __A,
				6574	(__v4df) __B,
				6575	(__v4df)
				6576	_mm256_setzero_pd (),
				6577	(__mmask8) __U);
				6578	}
				6579
				6580	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6581	_mm_mask_unpacklo_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)
				6582	{
				6583	return (__m128) __builtin_ia32_unpcklps128_mask ((__v4sf) __A,
				6584	(__v4sf) __B,
				6585	(__v4sf) __W,
				6586	(__mmask8) __U);
				6587	}
				6588
				6589	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6590	_mm_maskz_unpacklo_ps (__mmask8 __U, __m128 __A, __m128 __B)
				6591	{
				6592	return (__m128) __builtin_ia32_unpcklps128_mask ((__v4sf) __A,
				6593	(__v4sf) __B,
				6594	(__v4sf)
				6595	_mm_setzero_ps (),
				6596	(__mmask8) __U);
				6597	}
				6598
				6599	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6600	_mm256_mask_unpacklo_ps (__m256 __W, __mmask8 __U, __m256 __A,
				6601	__m256 __B)
				6602	{
				6603	return (__m256) __builtin_ia32_unpcklps256_mask ((__v8sf) __A,
				6604	(__v8sf) __B,
				6605	(__v8sf) __W,
				6606	(__mmask8) __U);
				6607	}
				6608
				6609	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6610	_mm256_maskz_unpacklo_ps (__mmask8 __U, __m256 __A, __m256 __B)
				6611	{
				6612	return (__m256) __builtin_ia32_unpcklps256_mask ((__v8sf) __A,
				6613	(__v8sf) __B,
				6614	(__v8sf)
				6615	_mm256_setzero_ps (),
				6616	(__mmask8) __U);
				6617	}
				6618
				6619	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6620	_mm_rcp14_pd (__m128d __A)
				6621	{
				6622	return (__m128d) __builtin_ia32_rcp14pd128_mask ((__v2df) __A,
				6623	(__v2df)
				6624	_mm_setzero_pd (),
				6625	(__mmask8) -1);
				6626	}
				6627
				6628	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6629	_mm_mask_rcp14_pd (__m128d __W, __mmask8 __U, __m128d __A)
				6630	{
				6631	return (__m128d) __builtin_ia32_rcp14pd128_mask ((__v2df) __A,
				6632	(__v2df) __W,
				6633	(__mmask8) __U);
				6634	}
				6635
				6636	static __inline__ __m128d __DEFAULT_FN_ATTRS
				6637	_mm_maskz_rcp14_pd (__mmask8 __U, __m128d __A)
				6638	{
				6639	return (__m128d) __builtin_ia32_rcp14pd128_mask ((__v2df) __A,
				6640	(__v2df)
				6641	_mm_setzero_pd (),
				6642	(__mmask8) __U);
				6643	}
				6644
				6645	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6646	_mm256_rcp14_pd (__m256d __A)
				6647	{
				6648	return (__m256d) __builtin_ia32_rcp14pd256_mask ((__v4df) __A,
				6649	(__v4df)
				6650	_mm256_setzero_pd (),
				6651	(__mmask8) -1);
				6652	}
				6653
				6654	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6655	_mm256_mask_rcp14_pd (__m256d __W, __mmask8 __U, __m256d __A)
				6656	{
				6657	return (__m256d) __builtin_ia32_rcp14pd256_mask ((__v4df) __A,
				6658	(__v4df) __W,
				6659	(__mmask8) __U);
				6660	}
				6661
				6662	static __inline__ __m256d __DEFAULT_FN_ATTRS
				6663	_mm256_maskz_rcp14_pd (__mmask8 __U, __m256d __A)
				6664	{
				6665	return (__m256d) __builtin_ia32_rcp14pd256_mask ((__v4df) __A,
				6666	(__v4df)
				6667	_mm256_setzero_pd (),
				6668	(__mmask8) __U);
				6669	}
				6670
				6671	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6672	_mm_rcp14_ps (__m128 __A)
				6673	{
				6674	return (__m128) __builtin_ia32_rcp14ps128_mask ((__v4sf) __A,
				6675	(__v4sf)
				6676	_mm_setzero_ps (),
				6677	(__mmask8) -1);
				6678	}
				6679
				6680	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6681	_mm_mask_rcp14_ps (__m128 __W, __mmask8 __U, __m128 __A)
				6682	{
				6683	return (__m128) __builtin_ia32_rcp14ps128_mask ((__v4sf) __A,
				6684	(__v4sf) __W,
				6685	(__mmask8) __U);
				6686	}
				6687
				6688	static __inline__ __m128 __DEFAULT_FN_ATTRS
				6689	_mm_maskz_rcp14_ps (__mmask8 __U, __m128 __A)
				6690	{
				6691	return (__m128) __builtin_ia32_rcp14ps128_mask ((__v4sf) __A,
				6692	(__v4sf)
				6693	_mm_setzero_ps (),
				6694	(__mmask8) __U);
				6695	}
				6696
				6697	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6698	_mm256_rcp14_ps (__m256 __A)
				6699	{
				6700	return (__m256) __builtin_ia32_rcp14ps256_mask ((__v8sf) __A,
				6701	(__v8sf)
				6702	_mm256_setzero_ps (),
				6703	(__mmask8) -1);
				6704	}
				6705
				6706	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6707	_mm256_mask_rcp14_ps (__m256 __W, __mmask8 __U, __m256 __A)
				6708	{
				6709	return (__m256) __builtin_ia32_rcp14ps256_mask ((__v8sf) __A,
				6710	(__v8sf) __W,
				6711	(__mmask8) __U);
				6712	}
				6713
				6714	static __inline__ __m256 __DEFAULT_FN_ATTRS
				6715	_mm256_maskz_rcp14_ps (__mmask8 __U, __m256 __A)
				6716	{
				6717	return (__m256) __builtin_ia32_rcp14ps256_mask ((__v8sf) __A,
				6718	(__v8sf)
				6719	_mm256_setzero_ps (),
				6720	(__mmask8) __U);
				6721	}
				6722
				6723	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6724	_mm_lzcnt_epi32 (__m128i __A)
				6725	{
				6726	return (__m128i) __builtin_ia32_vplzcntd_128_mask ((__v4si) __A,
				6727	(__v4si)
				6728	_mm_setzero_si128 (),
				6729	(__mmask8) -1);
				6730	}
				6731
				6732	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6733	_mm_mask_lzcnt_epi32 (__m128i __W, __mmask8 __U, __m128i __A)
				6734	{
				6735	return (__m128i) __builtin_ia32_vplzcntd_128_mask ((__v4si) __A,
				6736	(__v4si) __W,
				6737	(__mmask8) __U);
				6738	}
				6739
				6740	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6741	_mm_maskz_lzcnt_epi32 (__mmask8 __U, __m128i __A)
				6742	{
				6743	return (__m128i) __builtin_ia32_vplzcntd_128_mask ((__v4si) __A,
				6744	(__v4si)
				6745	_mm_setzero_si128 (),
				6746	(__mmask8) __U);
				6747	}
				6748
				6749	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6750	_mm256_lzcnt_epi32 (__m256i __A)
				6751	{
				6752	return (__m256i) __builtin_ia32_vplzcntd_256_mask ((__v8si) __A,
				6753	(__v8si)
				6754	_mm256_setzero_si256 (),
				6755	(__mmask8) -1);
				6756	}
				6757
				6758	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6759	_mm256_mask_lzcnt_epi32 (__m256i __W, __mmask8 __U, __m256i __A)
				6760	{
				6761	return (__m256i) __builtin_ia32_vplzcntd_256_mask ((__v8si) __A,
				6762	(__v8si) __W,
				6763	(__mmask8) __U);
				6764	}
				6765
				6766	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6767	_mm256_maskz_lzcnt_epi32 (__mmask8 __U, __m256i __A)
				6768	{
				6769	return (__m256i) __builtin_ia32_vplzcntd_256_mask ((__v8si) __A,
				6770	(__v8si)
				6771	_mm256_setzero_si256 (),
				6772	(__mmask8) __U);
				6773	}
				6774
				6775	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6776	_mm_lzcnt_epi64 (__m128i __A)
				6777	{
				6778	return (__m128i) __builtin_ia32_vplzcntq_128_mask ((__v2di) __A,
				6779	(__v2di)
				6780	_mm_setzero_di (),
				6781	(__mmask8) -1);
				6782	}
				6783
				6784	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6785	_mm_mask_lzcnt_epi64 (__m128i __W, __mmask8 __U, __m128i __A)
				6786	{
				6787	return (__m128i) __builtin_ia32_vplzcntq_128_mask ((__v2di) __A,
				6788	(__v2di) __W,
				6789	(__mmask8) __U);
				6790	}
				6791
				6792	static __inline__ __m128i __DEFAULT_FN_ATTRS
				6793	_mm_maskz_lzcnt_epi64 (__mmask8 __U, __m128i __A)
				6794	{
				6795	return (__m128i) __builtin_ia32_vplzcntq_128_mask ((__v2di) __A,
				6796	(__v2di)
				6797	_mm_setzero_di (),
				6798	(__mmask8) __U);
				6799	}
				6800
				6801	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6802	_mm256_lzcnt_epi64 (__m256i __A)
				6803	{
				6804	return (__m256i) __builtin_ia32_vplzcntq_256_mask ((__v4di) __A,
				6805	(__v4di)
				6806	_mm256_setzero_si256 (),
				6807	(__mmask8) -1);
				6808	}
				6809
				6810	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6811	_mm256_mask_lzcnt_epi64 (__m256i __W, __mmask8 __U, __m256i __A)
				6812	{
				6813	return (__m256i) __builtin_ia32_vplzcntq_256_mask ((__v4di) __A,
				6814	(__v4di) __W,
				6815	(__mmask8) __U);
				6816	}
				6817
				6818	static __inline__ __m256i __DEFAULT_FN_ATTRS
				6819	_mm256_maskz_lzcnt_epi64 (__mmask8 __U, __m256i __A)
				6820	{
				6821	return (__m256i) __builtin_ia32_vplzcntq_256_mask ((__v4di) __A,
				6822	(__v4di)
				6823	_mm256_setzero_si256 (),
				6824	(__mmask8) __U);
				6825	}
				6826
Michael Kuperstein	e45af54	2015-06-30 13:36:19 +0000	[diff] [blame]	6827	#undef __DEFAULT_FN_ATTRS
Eric Christopher	99af5b2	2015-10-27 06:11:03 +0000	[diff] [blame]	6828	#undef __DEFAULT_FN_ATTRS_BOTH
Eric Christopher	4d185168	2015-06-17 07:09:20 +0000	[diff] [blame]	6829
Robert Khasanov	b9f3a91	2014-10-08 17:18:13 +0000	[diff] [blame]	6830	#endif /* __AVX512VLINTRIN_H */