| Matt Arsenault | 7aad8fd | 2017-01-24 22:02:15 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s |
| 2 | ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s |
| Matt Arsenault | 9215b17 | 2014-08-03 05:27:14 +0000 | [diff] [blame] | 3 | |
| 4 | ; Make sure there isn't an extra space between the instruction name and first operands. |
| 5 | |
| Marek Olsak | fa6607d | 2015-02-11 14:26:46 +0000 | [diff] [blame] | 6 | ; GCN-LABEL: {{^}}add_f32: |
| Tom Stellard | 326d6ec | 2014-11-05 14:50:53 +0000 | [diff] [blame] | 7 | ; SI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb |
| 8 | ; SI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc |
| Marek Olsak | fa6607d | 2015-02-11 14:26:46 +0000 | [diff] [blame] | 9 | ; VI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c |
| 10 | ; VI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 |
| 11 | ; GCN: v_mov_b32_e32 [[VREGB:v[0-9]+]], [[SREGB]] |
| 12 | ; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]] |
| 13 | ; GCN: buffer_store_dword [[RESULT]], |
| Matt Arsenault | 9215b17 | 2014-08-03 05:27:14 +0000 | [diff] [blame] | 14 | define void @add_f32(float addrspace(1)* %out, float %a, float %b) { |
| 15 | %result = fadd float %a, %b |
| 16 | store float %result, float addrspace(1)* %out |
| 17 | ret void |
| 18 | } |