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gerrit-public.fairphone.software / toolchain / llvm-project / d10ce392540a9121c16916c2cf23f1843131247b / . / llvm / test / CodeGen / Mips / llvm-ir / urem.ll
blob: 1b082f5c1e34841e0011fe50bcf439f42ddb8035 [file] [log] [blame]
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]1; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]2; RUN: -check-prefix=ALL -check-prefix=GP32 \
3; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]4; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]5; RUN: -check-prefix=ALL -check-prefix=GP32 \
6; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
7; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
8; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=R2-R5 \
9; RUN: -check-prefix=R2-R6 -check-prefix=NOT-R6
10; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
11; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=R2-R5 \
12; RUN: -check-prefix=R2-R6 -check-prefix=NOT-R6
13; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
14; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=R2-R5 \
15; RUN: -check-prefix=R2-R6 -check-prefix=NOT-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]16; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]17; RUN: -check-prefix=ALL -check-prefix=GP32 \
18; RUN: -check-prefix=R6 -check-prefix=R2-R6
19
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]20; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]21; RUN: -check-prefix=ALL -check-prefix=GP64-NOT-R6 \
22; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]23; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]24; RUN: -check-prefix=ALL -check-prefix=GP64-NOT-R6 \
25; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]26; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]27; RUN: -check-prefix=ALL -check-prefix=GP64-NOT-R6 \
28; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]29; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]30; RUN: -check-prefix=ALL -check-prefix=R2-R5 -check-prefix=R2-R6 \
31; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]32; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]33; RUN: -check-prefix=ALL -check-prefix=R2-R5 -check-prefix=R2-R6 \
34; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]35; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]36; RUN: -check-prefix=ALL -check-prefix=R2-R5 -check-prefix=R2-R6 \
37; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]38; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]39; RUN: -check-prefix=ALL -check-prefix=64R6 \
40; RUN: -check-prefix=R6 -check-prefix=R2-R6
41
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]42; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]43; RUN: -check-prefix=ALL -check-prefix=MMR3 -check-prefix=MM32
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]44; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]45; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]46; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]47; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]48
49define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
50entry:
51; ALL-LABEL: urem_i1:
52
53 ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1
54 ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1
55 ; NOT-R6: divu $zero, $[[T1]], $[[T0]]
56 ; NOT-R6: teq $[[T0]], $zero, 7
57 ; NOT-R6: mfhi $[[T2:[0-9]+]]
58 ; NOT-R6: sll $[[T3:[0-9]+]], $[[T2]], 31
59 ; NOT-R6: sra $2, $[[T3]], 31
60
61 ; R6: andi $[[T0:[0-9]+]], $5, 1
62 ; R6: andi $[[T1:[0-9]+]], $4, 1
63 ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
64 ; R6: teq $[[T0]], $zero, 7
65 ; R6: sll $[[T3:[0-9]+]], $[[T2]], 31
66 ; R6: sra $2, $[[T3]], 31
67
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]68 ; MMR3: andi16 $[[T0:[0-9]+]], $5, 1
69 ; MMR3: andi16 $[[T1:[0-9]+]], $4, 1
70 ; MMR3: divu $zero, $[[T1]], $[[T0]]
71 ; MMR3: teq $[[T0]], $zero, 7
72 ; MMR3: mfhi $[[T2:[0-9]+]]
73 ; MMR3: sll $[[T3:[0-9]+]], $[[T2]], 31
74 ; MMR3: sra $2, $[[T3]], 31
75
76 ; MMR6: andi16 $[[T0:[0-9]+]], $5, 1
77 ; MMR6: andi16 $[[T1:[0-9]+]], $4, 1
78 ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
79 ; MMR6: teq $[[T0]], $zero, 7
80 ; MMR6: sll $[[T3:[0-9]+]], $[[T2]], 31
81 ; MMR6: sra $2, $[[T3]], 31
82
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]83 %r = urem i1 %a, %b
84 ret i1 %r
85}
86
87define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
88entry:
89; ALL-LABEL: urem_i8:
90
91 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255
92 ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255
93 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]]
94 ; NOT-R2-R6: teq $[[T0]], $zero, 7
95 ; NOT-R2-R6: mfhi $[[T2:[0-9]+]]
96 ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 24
97 ; NOT-R2-R6: sra $2, $[[T3]], 24
98
Daniel Sanders17793142015-02-18 16:24:50 +0000[diff] [blame]99 ; R2-R5: andi $[[T0:[0-9]+]], $5, 255
100 ; R2-R5: andi $[[T1:[0-9]+]], $4, 255
101 ; R2-R5: divu $zero, $[[T1]], $[[T0]]
102 ; R2-R5: teq $[[T0]], $zero, 7
103 ; R2-R5: mfhi $[[T2:[0-9]+]]
104 ; R2-R5: seb $2, $[[T2]]
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]105
106 ; R6: andi $[[T0:[0-9]+]], $5, 255
107 ; R6: andi $[[T1:[0-9]+]], $4, 255
108 ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
109 ; R6: teq $[[T0]], $zero, 7
110 ; R6: seb $2, $[[T2]]
111
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]112 ; MMR3: andi16 $[[T0:[0-9]+]], $5, 255
113 ; MMR3: andi16 $[[T1:[0-9]+]], $4, 255
114 ; MMR3: divu $zero, $[[T1]], $[[T0]]
115 ; MMR3: teq $[[T0]], $zero, 7
116 ; MMR3: mfhi $[[T2:[0-9]+]]
117 ; MMR3: seb $2, $[[T2]]
118
119 ; MMR6: andi16 $[[T0:[0-9]+]], $5, 255
120 ; MMR6: andi16 $[[T1:[0-9]+]], $4, 255
121 ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
122 ; MMR6: teq $[[T0]], $zero, 7
123 ; MMR6: seb $2, $[[T2]]
124
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]125 %r = urem i8 %a, %b
126 ret i8 %r
127}
128
129define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
130entry:
131; ALL-LABEL: urem_i16:
132
133 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535
134 ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 65535
135 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]]
136 ; NOT-R2-R6: teq $[[T0]], $zero, 7
137 ; NOT-R2-R6: mfhi $[[T2:[0-9]+]]
138 ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 16
139 ; NOT-R2-R6: sra $2, $[[T3]], 16
140
Daniel Sanders17793142015-02-18 16:24:50 +0000[diff] [blame]141 ; R2-R5: andi $[[T0:[0-9]+]], $5, 65535
142 ; R2-R5: andi $[[T1:[0-9]+]], $4, 65535
143 ; R2-R5: divu $zero, $[[T1]], $[[T0]]
144 ; R2-R5: teq $[[T0]], $zero, 7
145 ; R2-R5: mfhi $[[T3:[0-9]+]]
146 ; R2-R5: seh $2, $[[T2]]
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]147
148 ; R6: andi $[[T0:[0-9]+]], $5, 65535
149 ; R6: andi $[[T1:[0-9]+]], $4, 65535
150 ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
151 ; R6: teq $[[T0]], $zero, 7
152 ; R6: seh $2, $[[T2]]
153
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]154 ; MMR3: andi16 $[[T0:[0-9]+]], $5, 65535
155 ; MMR3: andi16 $[[T1:[0-9]+]], $4, 65535
156 ; MMR3: divu $zero, $[[T1]], $[[T0]]
157 ; MMR3: teq $[[T0]], $zero, 7
158 ; MMR3: mfhi $[[T2:[0-9]+]]
159 ; MMR3: seh $2, $[[T2]]
160
161 ; MMR6: andi16 $[[T0:[0-9]+]], $5, 65535
162 ; MMR6: andi16 $[[T1:[0-9]+]], $4, 65535
163 ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
164 ; MMR6: teq $[[T0]], $zero, 7
165 ; MMR6: seh $2, $[[T2]]
166
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]167 %r = urem i16 %a, %b
168 ret i16 %r
169}
170
171define signext i32 @urem_i32(i32 signext %a, i32 signext %b) {
172entry:
173; ALL-LABEL: urem_i32:
174
175 ; NOT-R6: divu $zero, $4, $5
176 ; NOT-R6: teq $5, $zero, 7
177 ; NOT-R6: mfhi $2
178
179 ; R6: modu $2, $4, $5
180 ; R6: teq $5, $zero, 7
181
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]182 ; MMR3: divu $zero, $4, $5
183 ; MMR3: teq $5, $zero, 7
184 ; MMR3: mfhi $2
185
186 ; MMR6: modu $2, $4, $5
187 ; MMR6: teq $5, $zero, 7
188
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]189 %r = urem i32 %a, %b
190 ret i32 %r
191}
192
193define signext i64 @urem_i64(i64 signext %a, i64 signext %b) {
194entry:
195; ALL-LABEL: urem_i64:
196
197 ; GP32: lw $25, %call16(__umoddi3)($gp)
198
199 ; GP64-NOT-R6: ddivu $zero, $4, $5
200 ; GP64-NOT-R6: teq $5, $zero, 7
201 ; GP64-NOT-R6: mfhi $2
202
203 ; 64R6: dmodu $2, $4, $5
204 ; 64R6: teq $5, $zero, 7
205
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]206 ; MM32: lw $25, %call16(__umoddi3)($2)
207
208 ; MM64: dmodu $2, $4, $5
209 ; MM64: teq $5, $zero, 7
210
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]211 %r = urem i64 %a, %b
212 ret i64 %r
213}
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000[diff] [blame]214
215define signext i128 @urem_i128(i128 signext %a, i128 signext %b) {
216entry:
217 ; ALL-LABEL: urem_i128:
218
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]219 ; GP32: lw $25, %call16(__umodti3)($gp)
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000[diff] [blame]220
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]221 ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame^]222 ; 64R6: ld $25, %call16(__umodti3)($gp)
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]223
224 ; MM32: lw $25, %call16(__umodti3)($2)
225
226 ; MM64: ld $25, %call16(__umodti3)($2)
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000[diff] [blame]227
228 %r = urem i128 %a, %b
229 ret i128 %r
230}