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gerrit-public.fairphone.software / toolchain / llvm-project / d2ed9c6c2c039a1a9c055ffe9bc7e1cf983f8042 / . / llvm / test / CodeGen / Mips / llvm-ir / not.ll
blob: 531a1b0447dfb11c49f65ce9750dcf39bd0f0d0c [file] [log] [blame]
Zlatko Buljand2ed9c62016-06-15 07:46:24 +0000[diff] [blame^]1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN: -check-prefix=ALL -check-prefix=GP32
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN: -check-prefix=ALL -check-prefix=GP32
5; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
6; RUN: -check-prefix=ALL -check-prefix=GP32
7; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
8; RUN: -check-prefix=ALL -check-prefix=GP32
9; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
10; RUN: -check-prefix=ALL -check-prefix=GP32
11; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
12; RUN: -check-prefix=ALL -check-prefix=GP32
13; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
14; RUN: -check-prefix=ALL -check-prefix=GP64
15; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
16; RUN: -check-prefix=ALL -check-prefix=GP64
17; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
18; RUN: -check-prefix=ALL -check-prefix=GP64
19; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
20; RUN: -check-prefix=ALL -check-prefix=GP64
21; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
22; RUN: -check-prefix=ALL -check-prefix=GP64
23; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
24; RUN: -check-prefix=ALL -check-prefix=GP64
25; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
26; RUN: -check-prefix=ALL -check-prefix=GP64
27; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
28; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
29; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
30; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
31; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
32; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MM64
33
34define signext i1 @not_i1(i1 signext %a) {
35entry:
36; ALL-LABEL: not_i1:
37
38 ; GP32: not $2, $4
39
40 ; GP64: not $2, $4
41
42 ; MM: not16 $2, $4
43
44 %r = xor i1 %a, -1
45 ret i1 %r
46}
47
48define signext i8 @not_i8(i8 signext %a) {
49entry:
50; ALL-LABEL: not_i8:
51
52 ; GP32: not $2, $4
53
54 ; GP64: not $2, $4
55
56 ; MM: not16 $2, $4
57
58 %r = xor i8 %a, -1
59 ret i8 %r
60}
61
62define signext i16 @not_i16(i16 signext %a) {
63entry:
64; ALL-LABEL: not_i16:
65
66 ; GP32: not $2, $4
67
68 ; GP64: not $2, $4
69
70 ; MM: not16 $2, $4
71
72 %r = xor i16 %a, -1
73 ret i16 %r
74}
75
76define signext i32 @not_i32(i32 signext %a) {
77entry:
78; ALL-LABEL: not_i32:
79
80 ; GP32: not $2, $4
81
82 ; GP64: not $2, $4
83
84 ; MM: not16 $2, $4
85
86 %r = xor i32 %a, -1
87 ret i32 %r
88}
89
90define signext i64 @not_i64(i64 signext %a) {
91entry:
92; ALL-LABEL: not_i64:
93
94 ; GP32: not $2, $4
95 ; GP32: not $3, $5
96
97 ; GP64: daddiu $[[T0:[0-9]+]], $zero, -1
98 ; GP64: xor $2, $4, $[[T0]]
99
100 ; MM32: not16 $2, $4
101 ; MM32: not16 $3, $5
102
103 ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1
104 ; MM64: xor $2, $4, $[[T0]]
105
106 %r = xor i64 %a, -1
107 ret i64 %r
108}
109
110define signext i128 @not_i128(i128 signext %a) {
111entry:
112; ALL-LABEL: not_i128:
113
114 ; GP32: not $2, $4
115 ; GP32: not $3, $5
116 ; GP32: not $4, $6
117 ; GP32: not $5, $7
118
119 ; GP64: daddiu $[[T0:[0-9]+]], $zero, -1
120 ; GP64: xor $2, $4, $[[T0]]
121 ; GP64: xor $3, $5, $[[T0]]
122
123 ; MM32: not16 $2, $4
124 ; MM32: not16 $3, $5
125 ; MM32: not16 $4, $6
126 ; MM32: not16 $5, $7
127
128 ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1
129 ; MM64: xor $2, $4, $[[T0]]
130 ; MM64: xor $3, $5, $[[T0]]
131
132 %r = xor i128 %a, -1
133 ret i128 %r
134}
135
136define signext i1 @nor_i1(i1 signext %a, i1 signext %b) {
137entry:
138; ALL-LABEL: nor_i1:
139
140 ; ALL: nor $2, $5, $4
141
142 %or = or i1 %b, %a
143 %r = xor i1 %or, -1
144 ret i1 %r
145}
146
147define signext i8 @nor_i8(i8 signext %a, i8 signext %b) {
148entry:
149; ALL-LABEL: nor_i8:
150
151 ; ALL: nor $2, $5, $4
152
153 %or = or i8 %b, %a
154 %r = xor i8 %or, -1
155 ret i8 %r
156}
157
158define signext i16 @nor_i16(i16 signext %a, i16 signext %b) {
159entry:
160; ALL-LABEL: nor_i16:
161
162 ; ALL: nor $2, $5, $4
163
164 %or = or i16 %b, %a
165 %r = xor i16 %or, -1
166 ret i16 %r
167}
168
169define signext i32 @nor_i32(i32 signext %a, i32 signext %b) {
170entry:
171; ALL-LABEL: nor_i32:
172
173 ; GP32: nor $2, $5, $4
174
175 ; GP64: or $[[T0:[0-9]+]], $5, $4
176 ; GP64: sll $[[T1:[0-9]+]], $[[T0]], 0
177 ; GP64: not $2, $[[T1]]
178
179 ; MM32: nor $2, $5, $4
180
181 ; MM64: or $[[T0:[0-9]+]], $5, $4
182 ; MM64: sll $[[T1:[0-9]+]], $[[T0]], 0
183 ; MM64: not16 $2, $[[T1]]
184
185 %or = or i32 %b, %a
186 %r = xor i32 %or, -1
187 ret i32 %r
188}
189
190
191define signext i64 @nor_i64(i64 signext %a, i64 signext %b) {
192entry:
193; ALL-LABEL: nor_i64:
194
195 ; GP32: nor $2, $6, $4
196 ; GP32: nor $3, $7, $5
197
198 ; GP64: nor $2, $5, $4
199
200 ; MM32: nor $2, $6, $4
201 ; MM32: nor $3, $7, $5
202
203 ; MM64: nor $2, $5, $4
204
205 %or = or i64 %b, %a
206 %r = xor i64 %or, -1
207 ret i64 %r
208}
209
210define signext i128 @nor_i128(i128 signext %a, i128 signext %b) {
211entry:
212; ALL-LABEL: nor_i128:
213
214 ; GP32: lw $[[T0:[0-9]+]], 24($sp)
215 ; GP32: lw $[[T1:[0-9]+]], 20($sp)
216 ; GP32: lw $[[T2:[0-9]+]], 16($sp)
217 ; GP32: nor $2, $[[T2]], $4
218 ; GP32: nor $3, $[[T1]], $5
219 ; GP32: nor $4, $[[T0]], $6
220 ; GP32: lw $[[T3:[0-9]+]], 28($sp)
221 ; GP32: nor $5, $[[T3]], $7
222
223 ; GP64: nor $2, $6, $4
224 ; GP64: nor $3, $7, $5
225
226 ; MM32: lw $[[T0:[0-9]+]], 20($sp)
227 ; MM32: lw $[[T1:[0-9]+]], 16($sp)
228 ; MM32: nor $2, $[[T1]], $4
229 ; MM32: nor $3, $[[T0]], $5
230 ; MM32: lw $[[T2:[0-9]+]], 24($sp)
231 ; MM32: nor $4, $[[T2]], $6
232 ; MM32: lw $[[T3:[0-9]+]], 28($sp)
233 ; MM32: nor $5, $[[T3]], $7
234
235 ; MM64: nor $2, $6, $4
236 ; MM64: nor $3, $7, $5
237
238 %or = or i128 %b, %a
239 %r = xor i128 %or, -1
240 ret i128 %r
241}