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Matt Davis712db512018-06-18 21:38:38 +00001//===--------------------- InstructionInfoView.cpp --------------*- C++ -*-===//
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +00002//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +00006//
7//===----------------------------------------------------------------------===//
8/// \file
9///
Matt Davis712db512018-06-18 21:38:38 +000010/// This file implements the InstructionInfoView API.
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000011///
12//===----------------------------------------------------------------------===//
13
Matt Davis10aa09f2018-08-24 20:24:53 +000014#include "Views/InstructionInfoView.h"
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000015
Fangrui Song5a8fd652018-10-30 15:56:08 +000016namespace llvm {
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000017namespace mca {
18
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000019void InstructionInfoView::printView(raw_ostream &OS) const {
20 std::string Buffer;
21 raw_string_ostream TempStream(Buffer);
22 const MCSchedModel &SM = STI.getSchedModel();
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000023
Andrea Di Biagioa7c3c452018-05-15 15:18:05 +000024 std::string Instruction;
25 raw_string_ostream InstrStream(Instruction);
26
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000027 TempStream << "\n\nInstruction Info:\n";
28 TempStream << "[1]: #uOps\n[2]: Latency\n[3]: RThroughput\n"
Andrea Di Biagiod2e2c052018-07-11 12:44:44 +000029 << "[4]: MayLoad\n[5]: MayStore\n[6]: HasSideEffects (U)\n\n";
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000030
Andrea Di Biagioa7c3c452018-05-15 15:18:05 +000031 TempStream << "[1] [2] [3] [4] [5] [6] Instructions:\n";
Andrea Di Biagio7be45b0f2018-10-24 15:06:27 +000032 for (const MCInst &Inst : Source) {
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000033 const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode());
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000034
Andrea Di Biagio39e5a562018-06-04 15:43:09 +000035 // Obtain the scheduling class information from the instruction.
36 unsigned SchedClassID = MCDesc.getSchedClass();
37 unsigned CPUID = SM.getProcessorID();
38
39 // Try to solve variant scheduling classes.
40 while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
41 SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &Inst, CPUID);
42
43 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000044 unsigned NumMicroOpcodes = SCDesc.NumMicroOps;
45 unsigned Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
46 Optional<double> RThroughput =
47 MCSchedModel::getReciprocalThroughput(STI, SCDesc);
48
49 TempStream << ' ' << NumMicroOpcodes << " ";
50 if (NumMicroOpcodes < 10)
51 TempStream << " ";
52 else if (NumMicroOpcodes < 100)
53 TempStream << ' ';
54 TempStream << Latency << " ";
55 if (Latency < 10)
56 TempStream << " ";
57 else if (Latency < 100)
58 TempStream << ' ';
59
60 if (RThroughput.hasValue()) {
61 double RT = RThroughput.getValue();
62 TempStream << format("%.2f", RT) << ' ';
63 if (RT < 10.0)
64 TempStream << " ";
65 else if (RT < 100.0)
66 TempStream << ' ';
67 } else {
68 TempStream << " - ";
69 }
70 TempStream << (MCDesc.mayLoad() ? " * " : " ");
71 TempStream << (MCDesc.mayStore() ? " * " : " ");
Andrea Di Biagiod2e2c052018-07-11 12:44:44 +000072 TempStream << (MCDesc.hasUnmodeledSideEffects() ? " U " : " ");
Andrea Di Biagioa7c3c452018-05-15 15:18:05 +000073
74 MCIP.printInst(&Inst, InstrStream, "", STI);
75 InstrStream.flush();
76
77 // Consume any tabs or spaces at the beginning of the string.
78 StringRef Str(Instruction);
79 Str = Str.ltrim();
80 TempStream << " " << Str << '\n';
81 Instruction = "";
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000082 }
83
84 TempStream.flush();
85 OS << Buffer;
86}
87} // namespace mca.
Fangrui Song5a8fd652018-10-30 15:56:08 +000088} // namespace llvm