| Tom Stellard | 9d7ddd5 | 2014-11-14 14:08:00 +0000 | [diff] [blame] | 1 | ============================ |
| 2 | User Guide for R600 Back-end |
| 3 | ============================ |
| 4 | |
| 5 | Introduction |
| 6 | ============ |
| 7 | |
| 8 | The R600 back-end provides ISA code generation for AMD GPUs, starting with |
| 9 | the R600 family up until the current Sea Islands (GCN Gen 2). |
| 10 | |
| 11 | |
| 12 | Assembler |
| 13 | ========= |
| 14 | |
| 15 | The assembler is currently a work in progress and not yet complete. Below |
| 16 | are the currently supported features. |
| 17 | |
| 18 | SOPP Instructions |
| 19 | ----------------- |
| 20 | |
| 21 | Unless otherwise mentioned, all SOPP instructions that with an operand |
| 22 | accept a integer operand(s) only. No verification is performed on the |
| 23 | operands, so it is up to the programmer to be familiar with the range |
| 24 | or acceptable values. |
| 25 | |
| 26 | s_waitcnt |
| 27 | ^^^^^^^^^ |
| 28 | |
| 29 | s_waitcnt accepts named arguments to specify which memory counter(s) to |
| 30 | wait for. |
| 31 | |
| 32 | .. code-block:: nasm |
| 33 | |
| 34 | // Wait for all counters to be 0 |
| 35 | s_waitcnt 0 |
| 36 | |
| 37 | // Equivalent to s_waitcnt 0. Counter names can also be delimited by |
| 38 | // '&' or ','. |
| 39 | s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0) |
| 40 | |
| 41 | // Wait for vmcnt counter to be 1. |
| 42 | s_waitcnt vmcnt(1) |
| 43 | |