Blame - llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp - toolchain/llvm-project

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Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	9
Benjamin Kramer	f57c197	2016-01-26 16:44:37 +0000	[diff] [blame]	10	#include "llvm/MC/MCDisassembler/MCDisassembler.h"
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	11	#include "MCTargetDesc/ARMAddressingModes.h"
				12	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	14	#include "llvm/MC/MCContext.h"
				15	#include "llvm/MC/MCExpr.h"
				16	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	17	#include "llvm/MC/MCInst.h"
Benjamin Kramer	48b5bbf	2011-11-11 12:39:41 +0000	[diff] [blame]	18	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	7a3973d	2012-04-03 15:48:14 +0000	[diff] [blame]	19	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	20	#include "llvm/Support/Debug.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	21	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	22	#include "llvm/Support/LEB128.h"
Evan Cheng	2bb4035	2011-08-24 18:08:43 +0000	[diff] [blame]	23	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	24	#include "llvm/Support/raw_ostream.h"
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	25	#include <vector>
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	26
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	27	using namespace llvm;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	28
Chandler Carruth	84e68b2	2014-04-22 02:41:26 +0000	[diff] [blame]	29	#define DEBUG_TYPE "arm-disassembler"
				30
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	31	typedef MCDisassembler::DecodeStatus DecodeStatus;
				32
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	33	namespace {
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	34	// Handles the condition code status of instructions in IT blocks
				35	class ITStatus
				36	{
				37	public:
				38	// Returns the condition code for instruction in IT block
				39	unsigned getITCC() {
				40	unsigned CC = ARMCC::AL;
				41	if (instrInITBlock())
				42	CC = ITStates.back();
				43	return CC;
				44	}
				45
				46	// Advances the IT block state to the next T or E
				47	void advanceITState() {
				48	ITStates.pop_back();
				49	}
				50
				51	// Returns true if the current instruction is in an IT block
				52	bool instrInITBlock() {
				53	return !ITStates.empty();
				54	}
				55
				56	// Returns true if current instruction is the last instruction in an IT block
				57	bool instrLastInITBlock() {
				58	return ITStates.size() == 1;
				59	}
				60
				61	// Called when decoding an IT instruction. Sets the IT state for the following
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	62	// instructions that for the IT block. Firstcond and Mask correspond to the
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	63	// fields in the IT instruction encoding.
				64	void setITState(char Firstcond, char Mask) {
				65	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	66	unsigned CondBit0 = Firstcond & 1;
Michael J. Spencer	df1ecbd7	2013-05-24 22:23:49 +0000	[diff] [blame]	67	unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	68	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				69	assert(NumTZ <= 3 && "Invalid IT mask!");
				70	// push condition codes onto the stack the correct order for the pops
				71	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				72	bool T = ((Mask >> Pos) & 1) == CondBit0;
				73	if (T)
				74	ITStates.push_back(CCBits);
				75	else
				76	ITStates.push_back(CCBits ^ 1);
				77	}
				78	ITStates.push_back(CCBits);
				79	}
				80
				81	private:
				82	std::vector<unsigned char> ITStates;
				83	};
Alexander Kornienko	f00654e	2015-06-23 09:49:53 +0000	[diff] [blame]	84	}
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	85
				86	namespace {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	87	/// ARM disassembler for all ARM platforms.
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	88	class ARMDisassembler : public MCDisassembler {
				89	public:
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	90	ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				91	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	92	}
				93
Alexander Kornienko	f817c1c	2015-04-11 02:11:45 +0000	[diff] [blame]	94	~ARMDisassembler() override {}
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	95
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	96	DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	97	ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	98	raw_ostream &VStream,
				99	raw_ostream &CStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	100	};
				101
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	102	/// Thumb disassembler for all Thumb platforms.
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	103	class ThumbDisassembler : public MCDisassembler {
				104	public:
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	105	ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				106	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	107	}
				108
Alexander Kornienko	f817c1c	2015-04-11 02:11:45 +0000	[diff] [blame]	109	~ThumbDisassembler() override {}
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	110
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	111	DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	112	ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	113	raw_ostream &VStream,
				114	raw_ostream &CStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	115
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	116	private:
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	117	mutable ITStatus ITBlock;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	118	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	119	void UpdateThumbVFPPredicate(MCInst&) const;
				120	};
Alexander Kornienko	f00654e	2015-06-23 09:49:53 +0000	[diff] [blame]	121	}
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	122
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	123	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	124	switch (In) {
				125	case MCDisassembler::Success:
				126	// Out stays the same.
				127	return true;
				128	case MCDisassembler::SoftFail:
				129	Out = In;
				130	return true;
				131	case MCDisassembler::Fail:
				132	Out = In;
				133	return false;
				134	}
David Blaikie	46a9f01	2012-01-20 21:51:11 +0000	[diff] [blame]	135	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	136	}
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	137
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	138
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	139	// Forward declare these because the autogenerated code will reference them.
				140	// Definitions are further down.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	141	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	142	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	143	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	144	unsigned RegNo, uint64_t Address,
				145	const void *Decoder);
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	146	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				147	unsigned RegNo, uint64_t Address,
				148	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	149	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	150	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	151	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	152	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	153	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	154	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	155	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				156	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	157	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	158	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	159	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	160	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	161	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	162	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	163	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	164	unsigned RegNo,
				165	uint64_t Address,
				166	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	167	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	168	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	169	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	170	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	171	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	172	unsigned RegNo, uint64_t Address,
				173	const void *Decoder);
Johnny Chen	74491bb	2010-08-12 01:40:54 +0000	[diff] [blame]	174
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	175	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	176	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	177	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	178	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	179	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	180	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	181	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	182	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	183	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	184	uint64_t Address, const void *Decoder);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	185
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	186	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	187	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	188	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	189	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	191	unsigned Insn,
				192	uint64_t Address,
				193	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	198	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	199	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	200	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	201	uint64_t Address, const void *Decoder);
				202
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	204	unsigned Insn,
				205	uint64_t Adddress,
				206	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	207	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	208	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	215	static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
				216	uint64_t Address, const void *Decoder);
				217	static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
				218	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	219	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	220	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	221	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	222	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	223	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	224	uint64_t Address, const void *Decoder);
Oliver Stannard	65b8538	2016-01-25 10:26:26 +0000	[diff] [blame]	225	static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
				226	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	227	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	228	uint64_t Address, const void *Decoder);
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	229	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				230	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	231	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	232	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	233	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	234	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	235	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
				236	uint64_t Address, const void *Decoder);
				237	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
				238	uint64_t Address, const void *Decoder);
				239	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
				240	uint64_t Address, const void *Decoder);
				241	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
				242	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	243	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	244	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	245	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	246	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	247	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	248	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	249	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	250	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	251	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	252	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	253	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	254	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	255	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	256	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	257	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	258	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	259	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	260	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	261	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	262	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	263	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	264	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	265	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	266	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	267	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	268	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	269	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	270	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	271	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	272	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	273	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	274	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	275	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
				276	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	277	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	278	uint64_t Address, const void *Decoder);
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	279	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
				280	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	281	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	282	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	283	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	284	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	285	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	286	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	287	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	288	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	289	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	290	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	291	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	292	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	293	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	294	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	295	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	296	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	297	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	298	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	299	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	300	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	301	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	302	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	303	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	304	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	305	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	306	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	307	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	308	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	309	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	310	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	311	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	312	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	313	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	314	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	315	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	316	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	317	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	318	uint64_t Address, const void *Decoder);
				319
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	320
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	321	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	322	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	323	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	324	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	325	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	326	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	327	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	328	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	329	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	330	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	331	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	332	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	333	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	334	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	335	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	336	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	337	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	338	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	339	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	340	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	341	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				342	uint64_t Address, const void* Decoder);
				343	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				344	uint64_t Address, const void* Decoder);
				345	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				346	uint64_t Address, const void* Decoder);
				347	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				348	uint64_t Address, const void* Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	349	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	350	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	351	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	352	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	353	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	354	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	355	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	356	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	357	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	358	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	359	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	360	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	361	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	362	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	363	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	364	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	365	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				366	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	367	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	368	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	369	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	370	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	371	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	372	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	373	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	374	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	375	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	376	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	377	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	378	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	379	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	380	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	381	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	382	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	383	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	384	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	385	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	386	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	387	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	388	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	389	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	390	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	391	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	392	uint64_t Address, const void *Decoder);
				393
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	394	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	395	uint64_t Address, const void *Decoder);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	396	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				397	uint64_t Address, const void *Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	398	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	814e69b	2010-04-13 21:21:57 +0000	[diff] [blame]	399
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	400	static MCDisassembler *createARMDisassembler(const Target &T,
				401	const MCSubtargetInfo &STI,
				402	MCContext &Ctx) {
				403	return new ARMDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	404	}
				405
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	406	static MCDisassembler *createThumbDisassembler(const Target &T,
				407	const MCSubtargetInfo &STI,
				408	MCContext &Ctx) {
				409	return new ThumbDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	410	}
				411
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	412	// Post-decoding checks
				413	static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
				414	uint64_t Address, raw_ostream &OS,
				415	raw_ostream &CS,
				416	uint32_t Insn,
				417	DecodeStatus Result)
				418	{
				419	switch (MI.getOpcode()) {
				420	case ARM::HVC: {
				421	// HVC is undefined if condition = 0xf otherwise upredictable
				422	// if condition != 0xe
				423	uint32_t Cond = (Insn >> 28) & 0xF;
				424	if (Cond == 0xF)
				425	return MCDisassembler::Fail;
				426	if (Cond != 0xE)
				427	return MCDisassembler::SoftFail;
				428	return Result;
				429	}
				430	default: return Result;
				431	}
				432	}
				433
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	434	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	435	ArrayRef<uint8_t> Bytes,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	436	uint64_t Address, raw_ostream &OS,
				437	raw_ostream &CS) const {
				438	CommentStream = &CS;
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	439
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	440	assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	441	"Asked to disassemble an ARM instruction but Subtarget is in Thumb "
				442	"mode!");
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	443
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	444	// We want to read exactly 4 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	445	if (Bytes.size() < 4) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	446	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	447	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	448	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	449
				450	// Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	451	uint32_t Insn =
				452	(Bytes[3] << 24) \| (Bytes[2] << 16) \| (Bytes[1] << 8) \| (Bytes[0] << 0);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	453
				454	// Calling the auto-generated decoder function.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	455	DecodeStatus Result =
				456	decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
				457	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	458	Size = 4;
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	459	return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	460	}
				461
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	462	// VFP and NEON instructions, similarly, are shared between ARM
				463	// and Thumb modes.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	464	Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
				465	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	466	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	467	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	468	}
				469
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	470	Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
				471	if (Result != MCDisassembler::Fail) {
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	472	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	473	return Result;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	474	}
				475
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	476	Result =
				477	decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
				478	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	479	Size = 4;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	480	// Add a fake predicate operand, because we share these instruction
				481	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	482	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				483	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	484	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	485	}
				486
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	487	Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	488	this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	489	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	490	Size = 4;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	491	// Add a fake predicate operand, because we share these instruction
				492	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	493	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				494	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	495	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	496	}
				497
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	498	Result =
				499	decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
				500	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	501	Size = 4;
				502	// Add a fake predicate operand, because we share these instruction
				503	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	504	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				505	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	506	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	507	}
				508
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	509	Result =
				510	decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
				511	if (Result != MCDisassembler::Fail) {
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	512	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	513	return Result;
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	514	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	515
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	516	Result =
				517	decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
				518	if (Result != MCDisassembler::Fail) {
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	519	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	520	return Result;
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	521	}
				522
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	523	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	524	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	525	}
				526
				527	namespace llvm {
Benjamin Kramer	0d6d098	2011-10-22 16:50:00 +0000	[diff] [blame]	528	extern const MCInstrDesc ARMInsts[];
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	529	}
				530
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	531	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				532	/// immediate Value in the MCInst. The immediate Value has had any PC
				533	/// adjustment made by the caller. If the instruction is a branch instruction
				534	/// then isBranch is true, else false. If the getOpInfo() function was set as
				535	/// part of the setupForSymbolicDisassembly() call then that function is called
				536	/// to get any symbolic information at the Address for this instruction. If
				537	/// that returns non-zero then the symbolic information it returns is used to
				538	/// create an MCExpr and that is added as an operand to the MCInst. If
				539	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				540	/// Value is done and if a symbol is found an MCExpr is created with that, else
				541	/// an MCExpr with Value is created. This function returns true if it adds an
				542	/// operand to the MCInst and false otherwise.
				543	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				544	bool isBranch, uint64_t InstSize,
				545	MCInst &MI, const void *Decoder) {
				546	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	547	// FIXME: Does it make sense for value to be negative?
				548	return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
				549	/* Offset */ 0, InstSize);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	550	}
				551
				552	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				553	/// referenced by a load instruction with the base register that is the Pc.
				554	/// These can often be values in a literal pool near the Address of the
				555	/// instruction. The Address of the instruction and its immediate Value are
				556	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	35521e2	2012-07-23 08:51:15 +0000	[diff] [blame]	557	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	558	/// the referenced address is that of a symbol. Or it will return a pointer to
				559	/// a literal 'C' string if the referenced address of the literal pool's entry
				560	/// is an address into a section with 'C' string literals.
				561	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	562	const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	563	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	564	Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	565	}
				566
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	567	// Thumb1 instructions don't have explicit S bits. Rather, they
				568	// implicitly set CPSR. Since it's not represented in the encoding, the
				569	// auto-generated decoder won't inject the CPSR operand. We need to fix
				570	// that as a post-pass.
				571	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				572	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	573	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	574	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	575	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				576	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	577	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	578	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	579	MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	580	return;
				581	}
				582	}
				583
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	584	MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	585	}
				586
				587	// Most Thumb instructions don't have explicit predicates in the
				588	// encoding, but rather get their predicates from IT context. We need
				589	// to fix up the predicate operands using this context information as a
				590	// post-pass.
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	591	MCDisassembler::DecodeStatus
				592	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	593	MCDisassembler::DecodeStatus S = Success;
				594
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	595	// A few instructions actually have predicates encoded in them. Don't
				596	// try to overwrite it if we're seeing one of those.
				597	switch (MI.getOpcode()) {
				598	case ARM::tBcc:
				599	case ARM::t2Bcc:
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	600	case ARM::tCBZ:
				601	case ARM::tCBNZ:
Owen Anderson	61e4604	2011-09-19 23:47:10 +0000	[diff] [blame]	602	case ARM::tCPS:
				603	case ARM::t2CPS3p:
				604	case ARM::t2CPS2p:
				605	case ARM::t2CPS1p:
Owen Anderson	163be01	2011-09-19 23:57:20 +0000	[diff] [blame]	606	case ARM::tMOVSr:
Owen Anderson	44f76ea	2011-10-13 17:58:39 +0000	[diff] [blame]	607	case ARM::tSETEND:
Owen Anderson	33d3953	2011-09-08 22:48:37 +0000	[diff] [blame]	608	// Some instructions (mostly conditional branches) are not
				609	// allowed in IT blocks.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	610	if (ITBlock.instrInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	611	S = SoftFail;
				612	else
				613	return Success;
				614	break;
				615	case ARM::tB:
				616	case ARM::t2B:
Owen Anderson	f902d92	2011-09-19 22:34:23 +0000	[diff] [blame]	617	case ARM::t2TBB:
				618	case ARM::t2TBH:
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	619	// Some instructions (mostly unconditional branches) can
				620	// only appears at the end of, or outside of, an IT.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	621	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	622	S = SoftFail;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	623	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	624	default:
				625	break;
				626	}
				627
				628	// If we're in an IT block, base the predicate on that. Otherwise,
				629	// assume a predicate of AL.
				630	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	631	CC = ITBlock.getITCC();
				632	if (CC == 0xF)
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	633	CC = ARMCC::AL;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	634	if (ITBlock.instrInITBlock())
				635	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	636
				637	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	638	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	639	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	640	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				641	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	642	if (OpInfo[i].isPredicate()) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	643	I = MI.insert(I, MCOperand::createImm(CC));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	644	++I;
				645	if (CC == ARMCC::AL)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	646	MI.insert(I, MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	647	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	648	MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	649	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	650	}
				651	}
				652
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	653	I = MI.insert(I, MCOperand::createImm(CC));
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	654	++I;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	655	if (CC == ARMCC::AL)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	656	MI.insert(I, MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	657	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	658	MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	659
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	660	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	661	}
				662
				663	// Thumb VFP instructions are a special case. Because we share their
				664	// encodings between ARM and Thumb modes, and they are predicable in ARM
				665	// mode, the auto-generated decoder will give them an (incorrect)
				666	// predicate operand. We need to rewrite these operands based on the IT
				667	// context as a post-pass.
				668	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				669	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	670	CC = ITBlock.getITCC();
				671	if (ITBlock.instrInITBlock())
				672	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	673
				674	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				675	MCInst::iterator I = MI.begin();
Owen Anderson	216cfaa	2011-08-24 21:35:46 +0000	[diff] [blame]	676	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				677	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	678	if (OpInfo[i].isPredicate() ) {
				679	I->setImm(CC);
				680	++I;
				681	if (CC == ARMCC::AL)
				682	I->setReg(0);
				683	else
				684	I->setReg(ARM::CPSR);
				685	return;
				686	}
				687	}
				688	}
				689
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	690	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	691	ArrayRef<uint8_t> Bytes,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	692	uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	693	raw_ostream &OS,
				694	raw_ostream &CS) const {
				695	CommentStream = &CS;
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	696
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	697	assert(STI.getFeatureBits()[ARM::ModeThumb] &&
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	698	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				699
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	700	// We want to read exactly 2 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	701	if (Bytes.size() < 2) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	702	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	703	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	704	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	705
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	706	uint16_t Insn16 = (Bytes[1] << 8) \| Bytes[0];
				707	DecodeStatus Result =
				708	decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
				709	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	710	Size = 2;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	711	Check(Result, AddThumbPredicate(MI));
				712	return Result;
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	713	}
				714
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	715	Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
				716	STI);
				717	if (Result) {
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	718	Size = 2;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	719	bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	720	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	721	AddThumb1SBit(MI, InITBlock);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	722	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	723	}
				724
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	725	Result =
				726	decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
				727	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	728	Size = 2;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	729
				730	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				731	// the Thumb predicate.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	732	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	733	Result = MCDisassembler::SoftFail;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	734
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	735	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	736
				737	// If we find an IT instruction, we need to parse its condition
				738	// code and mask operands so that we can apply them correctly
				739	// to the subsequent instructions.
				740	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	f1e3844	2011-09-14 21:06:21 +0000	[diff] [blame]	741
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	742	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	743	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	744	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	745	}
				746
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	747	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	748	}
				749
				750	// We want to read exactly 4 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	751	if (Bytes.size() < 4) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	752	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	753	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	754	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	755
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	756	uint32_t Insn32 =
				757	(Bytes[3] << 8) \| (Bytes[2] << 0) \| (Bytes[1] << 24) \| (Bytes[0] << 16);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	758	Result =
				759	decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
				760	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	761	Size = 4;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	762	bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	763	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	764	AddThumb1SBit(MI, InITBlock);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	765	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	766	}
				767
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	768	Result =
				769	decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
				770	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	771	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	772	Check(Result, AddThumbPredicate(MI));
				773	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	774	}
				775
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	776	if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	777	Result =
				778	decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
				779	if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	780	Size = 4;
				781	UpdateThumbVFPPredicate(MI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	782	return Result;
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	783	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	784	}
				785
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	786	Result =
				787	decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
				788	if (Result != MCDisassembler::Fail) {
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	789	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	790	return Result;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	791	}
				792
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	793	if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	794	Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
				795	STI);
				796	if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	797	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	798	Check(Result, AddThumbPredicate(MI));
				799	return Result;
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	800	}
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	801	}
				802
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	803	if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	804	uint32_t NEONLdStInsn = Insn32;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	805	NEONLdStInsn &= 0xF0FFFFFF;
				806	NEONLdStInsn \|= 0x04000000;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	807	Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	808	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	809	if (Result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	810	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	811	Check(Result, AddThumbPredicate(MI));
				812	return Result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	813	}
				814	}
				815
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	816	if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	817	uint32_t NEONDataInsn = Insn32;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	818	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				819	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				820	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	821	Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	822	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	823	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	824	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	825	Check(Result, AddThumbPredicate(MI));
				826	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	827	}
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	828
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	829	uint32_t NEONCryptoInsn = Insn32;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	830	NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
				831	NEONCryptoInsn \|= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				832	NEONCryptoInsn \|= 0x12000000; // Set bits 28 and 25
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	833	Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	834	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	835	if (Result != MCDisassembler::Fail) {
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	836	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	837	return Result;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	838	}
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	839
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	840	uint32_t NEONv8Insn = Insn32;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	841	NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	842	Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	843	this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	844	if (Result != MCDisassembler::Fail) {
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	845	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	846	return Result;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	847	}
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	848	}
				849
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	850	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	851	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	852	}
				853
				854
				855	extern "C" void LLVMInitializeARMDisassembler() {
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	856	TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	857	createARMDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	858	TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	859	createARMDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	860	TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	861	createThumbDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	862	TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	863	createThumbDisassembler);
				864	}
				865
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	866	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	867	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				868	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				869	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				870	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				871	};
				872
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	873	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	874	uint64_t Address, const void *Decoder) {
				875	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	876	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	877
				878	unsigned Register = GPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	879	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	880	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	881	}
				882
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	883	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	884	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	885	uint64_t Address, const void *Decoder) {
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	886	DecodeStatus S = MCDisassembler::Success;
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	887
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	888	if (RegNo == 15)
				889	S = MCDisassembler::SoftFail;
				890
				891	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				892
				893	return S;
Owen Anderson	042619f	2011-08-09 22:48:45 +0000	[diff] [blame]	894	}
				895
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	896	static DecodeStatus
				897	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				898	uint64_t Address, const void *Decoder) {
				899	DecodeStatus S = MCDisassembler::Success;
				900
				901	if (RegNo == 15)
				902	{
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	903	Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	904	return MCDisassembler::Success;
				905	}
				906
				907	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				908	return S;
				909	}
				910
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	911	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	912	uint64_t Address, const void *Decoder) {
				913	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	914	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	915	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				916	}
				917
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	918	static const uint16_t GPRPairDecoderTable[] = {
				919	ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
				920	ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
				921	};
				922
				923	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				924	uint64_t Address, const void *Decoder) {
				925	DecodeStatus S = MCDisassembler::Success;
				926
				927	if (RegNo > 13)
				928	return MCDisassembler::Fail;
				929
				930	if ((RegNo & 1) \|\| RegNo == 0xe)
				931	S = MCDisassembler::SoftFail;
				932
				933	unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	934	Inst.addOperand(MCOperand::createReg(RegisterPair));
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	935	return S;
				936	}
				937
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	938	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	939	uint64_t Address, const void *Decoder) {
				940	unsigned Register = 0;
				941	switch (RegNo) {
				942	case 0:
				943	Register = ARM::R0;
				944	break;
				945	case 1:
				946	Register = ARM::R1;
				947	break;
				948	case 2:
				949	Register = ARM::R2;
				950	break;
				951	case 3:
				952	Register = ARM::R3;
				953	break;
				954	case 9:
				955	Register = ARM::R9;
				956	break;
				957	case 12:
				958	Register = ARM::R12;
				959	break;
				960	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	961	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	962	}
				963
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	964	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	965	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	966	}
				967
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	968	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	969	uint64_t Address, const void *Decoder) {
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	970	DecodeStatus S = MCDisassembler::Success;
Artyom Skrobov	b4398107	2015-10-28 13:58:36 +0000	[diff] [blame]	971
				972	const FeatureBitset &featureBits =
				973	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				974
				975	if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) \|\| RegNo == 15)
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	976	S = MCDisassembler::SoftFail;
Artyom Skrobov	b4398107	2015-10-28 13:58:36 +0000	[diff] [blame]	977
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	978	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				979	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	980	}
				981
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	982	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	983	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				984	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				985	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				986	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				987	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				988	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				989	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				990	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				991	};
				992
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	993	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	994	uint64_t Address, const void *Decoder) {
				995	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	996	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	997
				998	unsigned Register = SPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	999	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1000	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1001	}
				1002
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1003	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1004	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1005	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1006	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1007	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1008	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1009	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1010	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1011	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1012	};
				1013
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1014	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1015	uint64_t Address, const void *Decoder) {
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	1016	const FeatureBitset &featureBits =
				1017	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				1018
				1019	bool hasD16 = featureBits[ARM::FeatureD16];
Oliver Stannard	9e89d8c	2014-11-05 12:06:39 +0000	[diff] [blame]	1020
				1021	if (RegNo > 31 \|\| (hasD16 && RegNo > 15))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1022	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1023
				1024	unsigned Register = DPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1025	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1026	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1027	}
				1028
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1029	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1030	uint64_t Address, const void *Decoder) {
				1031	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1032	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1033	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1034	}
				1035
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1036	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1037	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1038	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1039	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1040	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1041	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1042	}
				1043
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1044	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1045	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1046	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1047	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1048	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1049	};
				1050
				1051
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1052	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1053	uint64_t Address, const void *Decoder) {
Mihai Popa	dcf0922	2013-05-20 14:42:43 +0000	[diff] [blame]	1054	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1055	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1056	RegNo >>= 1;
				1057
				1058	unsigned Register = QPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1059	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1060	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1061	}
				1062
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1063	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1064	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1065	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1066	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1067	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1068	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1069	ARM::Q15
				1070	};
				1071
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1072	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1073	uint64_t Address, const void *Decoder) {
				1074	if (RegNo > 30)
				1075	return MCDisassembler::Fail;
				1076
				1077	unsigned Register = DPairDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1078	Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1079	return MCDisassembler::Success;
				1080	}
				1081
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1082	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1083	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1084	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1085	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1086	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1087	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1088	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1089	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1090	ARM::D28_D30, ARM::D29_D31
				1091	};
				1092
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1093	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1094	unsigned RegNo,
				1095	uint64_t Address,
				1096	const void *Decoder) {
				1097	if (RegNo > 29)
				1098	return MCDisassembler::Fail;
				1099
				1100	unsigned Register = DPairSpacedDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1101	Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1102	return MCDisassembler::Success;
				1103	}
				1104
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1105	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1106	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1107	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	7a2401d	2011-08-09 21:07:45 +0000	[diff] [blame]	1108	// AL predicate is not allowed on Thumb1 branches.
				1109	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1110	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1111	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1112	if (Val == ARMCC::AL) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1113	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1114	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1115	Inst.addOperand(MCOperand::createReg(ARM::CPSR));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1116	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1117	}
				1118
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1119	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1120	uint64_t Address, const void *Decoder) {
				1121	if (Val)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1122	Inst.addOperand(MCOperand::createReg(ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1123	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1124	Inst.addOperand(MCOperand::createReg(0));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1125	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1126	}
				1127
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1128	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1129	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1130	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1131
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1132	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1133	unsigned type = fieldFromInstruction(Val, 5, 2);
				1134	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1135
				1136	// Register-immediate
Artyom Skrobov	b4398107	2015-10-28 13:58:36 +0000	[diff] [blame]	1137	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1138	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1139
				1140	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1141	switch (type) {
				1142	case 0:
				1143	Shift = ARM_AM::lsl;
				1144	break;
				1145	case 1:
				1146	Shift = ARM_AM::lsr;
				1147	break;
				1148	case 2:
				1149	Shift = ARM_AM::asr;
				1150	break;
				1151	case 3:
				1152	Shift = ARM_AM::ror;
				1153	break;
				1154	}
				1155
				1156	if (Shift == ARM_AM::ror && imm == 0)
				1157	Shift = ARM_AM::rrx;
				1158
				1159	unsigned Op = Shift \| (imm << 3);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1160	Inst.addOperand(MCOperand::createImm(Op));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1161
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1162	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1163	}
				1164
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1165	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1166	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1167	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1168
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1169	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1170	unsigned type = fieldFromInstruction(Val, 5, 2);
				1171	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1172
				1173	// Register-register
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1174	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1175	return MCDisassembler::Fail;
				1176	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1177	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1178
				1179	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1180	switch (type) {
				1181	case 0:
				1182	Shift = ARM_AM::lsl;
				1183	break;
				1184	case 1:
				1185	Shift = ARM_AM::lsr;
				1186	break;
				1187	case 2:
				1188	Shift = ARM_AM::asr;
				1189	break;
				1190	case 3:
				1191	Shift = ARM_AM::ror;
				1192	break;
				1193	}
				1194
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1195	Inst.addOperand(MCOperand::createImm(Shift));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1196
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1197	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1198	}
				1199
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1200	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1201	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1202	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1203
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1204	bool NeedDisjointWriteback = false;
				1205	unsigned WritebackReg = 0;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1206	switch (Inst.getOpcode()) {
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1207	default:
				1208	break;
				1209	case ARM::LDMIA_UPD:
				1210	case ARM::LDMDB_UPD:
				1211	case ARM::LDMIB_UPD:
				1212	case ARM::LDMDA_UPD:
				1213	case ARM::t2LDMIA_UPD:
				1214	case ARM::t2LDMDB_UPD:
				1215	case ARM::t2STMIA_UPD:
				1216	case ARM::t2STMDB_UPD:
				1217	NeedDisjointWriteback = true;
				1218	WritebackReg = Inst.getOperand(0).getReg();
				1219	break;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1220	}
				1221
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	1222	// Empty register lists are not allowed.
Benjamin Kramer	8bad66e	2013-05-19 22:01:57 +0000	[diff] [blame]	1223	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1224	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1225	if (Val & (1 << i)) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1226	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1227	return MCDisassembler::Fail;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1228	// Writeback not allowed if Rn is in the target list.
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1229	if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1230	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1231	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1232	}
				1233
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1234	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1235	}
				1236
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1237	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1238	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1239	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1240
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1241	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1242	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1243
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1244	// In case of unpredictable encoding, tweak the operands.
				1245	if (regs == 0 \|\| (Vd + regs) > 32) {
				1246	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1247	regs = std::max( 1u, regs);
				1248	S = MCDisassembler::SoftFail;
				1249	}
				1250
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1251	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1252	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1253	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1254	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1255	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1256	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1257
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1258	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1259	}
				1260
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1261	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1262	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1263	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1264
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1265	unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1266	unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga	9560af8	2012-05-03 16:38:40 +0000	[diff] [blame]	1267
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1268	// In case of unpredictable encoding, tweak the operands.
				1269	if (regs == 0 \|\| regs > 16 \|\| (Vd + regs) > 32) {
				1270	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1271	regs = std::max( 1u, regs);
				1272	regs = std::min(16u, regs);
				1273	S = MCDisassembler::SoftFail;
				1274	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1275
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1276	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1277	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1278	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1279	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1280	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1281	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1282
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1283	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1284	}
				1285
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1286	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1287	uint64_t Address, const void *Decoder) {
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1288	// This operand encodes a mask of contiguous zeros between a specified MSB
				1289	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1290	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1291	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1292	// create the final mask.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1293	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1294	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1295
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1296	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	136d674	2012-11-29 23:47:11 +0000	[diff] [blame]	1297	if (lsb > msb) {
				1298	Check(S, MCDisassembler::SoftFail);
				1299	// The check above will cause the warning for the "potentially undefined
				1300	// instruction encoding" but we can't build a bad MCOperand value here
				1301	// with a lsb > msb or else printing the MCInst will cause a crash.
				1302	lsb = msb;
				1303	}
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1304
Owen Anderson	b925e93	2011-09-16 23:04:48 +0000	[diff] [blame]	1305	uint32_t msb_mask = 0xFFFFFFFF;
				1306	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1307	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1308
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1309	Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1310	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1311	}
				1312
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1313	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1314	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1315	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1316
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1317	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1318	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1319	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1320	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1321	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1322	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1323
				1324	switch (Inst.getOpcode()) {
				1325	case ARM::LDC_OFFSET:
				1326	case ARM::LDC_PRE:
				1327	case ARM::LDC_POST:
				1328	case ARM::LDC_OPTION:
				1329	case ARM::LDCL_OFFSET:
				1330	case ARM::LDCL_PRE:
				1331	case ARM::LDCL_POST:
				1332	case ARM::LDCL_OPTION:
				1333	case ARM::STC_OFFSET:
				1334	case ARM::STC_PRE:
				1335	case ARM::STC_POST:
				1336	case ARM::STC_OPTION:
				1337	case ARM::STCL_OFFSET:
				1338	case ARM::STCL_PRE:
				1339	case ARM::STCL_POST:
				1340	case ARM::STCL_OPTION:
Owen Anderson	18d17aa	2011-09-07 21:10:42 +0000	[diff] [blame]	1341	case ARM::t2LDC_OFFSET:
				1342	case ARM::t2LDC_PRE:
				1343	case ARM::t2LDC_POST:
				1344	case ARM::t2LDC_OPTION:
				1345	case ARM::t2LDCL_OFFSET:
				1346	case ARM::t2LDCL_PRE:
				1347	case ARM::t2LDCL_POST:
				1348	case ARM::t2LDCL_OPTION:
				1349	case ARM::t2STC_OFFSET:
				1350	case ARM::t2STC_PRE:
				1351	case ARM::t2STC_POST:
				1352	case ARM::t2STC_OPTION:
				1353	case ARM::t2STCL_OFFSET:
				1354	case ARM::t2STCL_PRE:
				1355	case ARM::t2STCL_POST:
				1356	case ARM::t2STCL_OPTION:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1357	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1358	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1359	break;
				1360	default:
				1361	break;
				1362	}
				1363
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	1364	const FeatureBitset &featureBits =
				1365	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				1366	if (featureBits[ARM::HasV8Ops] && (coproc != 14))
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	1367	return MCDisassembler::Fail;
				1368
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1369	Inst.addOperand(MCOperand::createImm(coproc));
				1370	Inst.addOperand(MCOperand::createImm(CRd));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1371	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1372	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1373
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1374	switch (Inst.getOpcode()) {
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1375	case ARM::t2LDC2_OFFSET:
				1376	case ARM::t2LDC2L_OFFSET:
				1377	case ARM::t2LDC2_PRE:
				1378	case ARM::t2LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1379	case ARM::t2STC2_OFFSET:
				1380	case ARM::t2STC2L_OFFSET:
				1381	case ARM::t2STC2_PRE:
				1382	case ARM::t2STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1383	case ARM::LDC2_OFFSET:
				1384	case ARM::LDC2L_OFFSET:
				1385	case ARM::LDC2_PRE:
				1386	case ARM::LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1387	case ARM::STC2_OFFSET:
				1388	case ARM::STC2L_OFFSET:
				1389	case ARM::STC2_PRE:
				1390	case ARM::STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1391	case ARM::t2LDC_OFFSET:
				1392	case ARM::t2LDCL_OFFSET:
				1393	case ARM::t2LDC_PRE:
				1394	case ARM::t2LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1395	case ARM::t2STC_OFFSET:
				1396	case ARM::t2STCL_OFFSET:
				1397	case ARM::t2STC_PRE:
				1398	case ARM::t2STCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1399	case ARM::LDC_OFFSET:
				1400	case ARM::LDCL_OFFSET:
				1401	case ARM::LDC_PRE:
				1402	case ARM::LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1403	case ARM::STC_OFFSET:
				1404	case ARM::STCL_OFFSET:
				1405	case ARM::STC_PRE:
				1406	case ARM::STCL_PRE:
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1407	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1408	Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1409	break;
				1410	case ARM::t2LDC2_POST:
				1411	case ARM::t2LDC2L_POST:
				1412	case ARM::t2STC2_POST:
				1413	case ARM::t2STC2L_POST:
				1414	case ARM::LDC2_POST:
				1415	case ARM::LDC2L_POST:
				1416	case ARM::STC2_POST:
				1417	case ARM::STC2L_POST:
				1418	case ARM::t2LDC_POST:
				1419	case ARM::t2LDCL_POST:
				1420	case ARM::t2STC_POST:
				1421	case ARM::t2STCL_POST:
				1422	case ARM::LDC_POST:
				1423	case ARM::LDCL_POST:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1424	case ARM::STC_POST:
				1425	case ARM::STCL_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1426	imm \|= U << 8;
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1427	// fall through.
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1428	default:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1429	// The 'option' variant doesn't encode 'U' in the immediate since
				1430	// the immediate is unsigned [0,255].
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1431	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1432	break;
				1433	}
				1434
				1435	switch (Inst.getOpcode()) {
				1436	case ARM::LDC_OFFSET:
				1437	case ARM::LDC_PRE:
				1438	case ARM::LDC_POST:
				1439	case ARM::LDC_OPTION:
				1440	case ARM::LDCL_OFFSET:
				1441	case ARM::LDCL_PRE:
				1442	case ARM::LDCL_POST:
				1443	case ARM::LDCL_OPTION:
				1444	case ARM::STC_OFFSET:
				1445	case ARM::STC_PRE:
				1446	case ARM::STC_POST:
				1447	case ARM::STC_OPTION:
				1448	case ARM::STCL_OFFSET:
				1449	case ARM::STCL_PRE:
				1450	case ARM::STCL_POST:
				1451	case ARM::STCL_OPTION:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1452	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1453	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1454	break;
				1455	default:
				1456	break;
				1457	}
				1458
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1459	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1460	}
				1461
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1462	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1463	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1464	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1465	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1466
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1467	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1468	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1469	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1470	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1471	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1472	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1473	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1474	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1475
				1476	// On stores, the writeback operand precedes Rt.
				1477	switch (Inst.getOpcode()) {
				1478	case ARM::STR_POST_IMM:
				1479	case ARM::STR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1480	case ARM::STRB_POST_IMM:
				1481	case ARM::STRB_POST_REG:
Jim Grosbach	e259421	2011-08-11 22:18:00 +0000	[diff] [blame]	1482	case ARM::STRT_POST_REG:
				1483	case ARM::STRT_POST_IMM:
Jim Grosbach	2a50260	2011-08-11 20:04:56 +0000	[diff] [blame]	1484	case ARM::STRBT_POST_REG:
				1485	case ARM::STRBT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1486	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1487	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1488	break;
				1489	default:
				1490	break;
				1491	}
				1492
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1493	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1494	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1495
				1496	// On loads, the writeback operand comes after Rt.
				1497	switch (Inst.getOpcode()) {
				1498	case ARM::LDR_POST_IMM:
				1499	case ARM::LDR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1500	case ARM::LDRB_POST_IMM:
				1501	case ARM::LDRB_POST_REG:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1502	case ARM::LDRBT_POST_REG:
				1503	case ARM::LDRBT_POST_IMM:
Jim Grosbach	d5d6359	2011-08-10 23:43:54 +0000	[diff] [blame]	1504	case ARM::LDRT_POST_REG:
				1505	case ARM::LDRT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1506	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1507	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1508	break;
				1509	default:
				1510	break;
				1511	}
				1512
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1513	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1514	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1515
				1516	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1517	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1518	Op = ARM_AM::sub;
				1519
				1520	bool writeback = (P == 0) \|\| (W == 1);
				1521	unsigned idx_mode = 0;
				1522	if (P && writeback)
				1523	idx_mode = ARMII::IndexModePre;
				1524	else if (!P && writeback)
				1525	idx_mode = ARMII::IndexModePost;
				1526
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1527	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1528	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	3477f2c	2011-08-11 19:00:18 +0000	[diff] [blame]	1529
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1530	if (reg) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1531	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1532	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1533	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1534	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1535	case 0:
				1536	Opc = ARM_AM::lsl;
				1537	break;
				1538	case 1:
				1539	Opc = ARM_AM::lsr;
				1540	break;
				1541	case 2:
				1542	Opc = ARM_AM::asr;
				1543	break;
				1544	case 3:
				1545	Opc = ARM_AM::ror;
				1546	break;
				1547	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1548	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1549	}
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1550	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1551	if (Opc == ARM_AM::ror && amt == 0)
				1552	Opc = ARM_AM::rrx;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1553	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1554
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1555	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1556	} else {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1557	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1558	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1559	Inst.addOperand(MCOperand::createImm(tmp));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1560	}
				1561
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1562	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1563	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1564
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1565	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1566	}
				1567
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1568	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1569	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1570	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1571
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1572	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1573	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1574	unsigned type = fieldFromInstruction(Val, 5, 2);
				1575	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1576	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1577
Owen Anderson	d151b09	2011-08-09 21:38:14 +0000	[diff] [blame]	1578	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1579	switch (type) {
				1580	case 0:
				1581	ShOp = ARM_AM::lsl;
				1582	break;
				1583	case 1:
				1584	ShOp = ARM_AM::lsr;
				1585	break;
				1586	case 2:
				1587	ShOp = ARM_AM::asr;
				1588	break;
				1589	case 3:
				1590	ShOp = ARM_AM::ror;
				1591	break;
				1592	}
				1593
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1594	if (ShOp == ARM_AM::ror && imm == 0)
				1595	ShOp = ARM_AM::rrx;
				1596
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1597	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1598	return MCDisassembler::Fail;
				1599	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1600	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1601	unsigned shift;
				1602	if (U)
				1603	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1604	else
				1605	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1606	Inst.addOperand(MCOperand::createImm(shift));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1607
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1608	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1609	}
				1610
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1611	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1612	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1613	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1614	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1615
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1616	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1617	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1618	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1619	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1620	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1621	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1622	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1623	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1624	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1625	unsigned Rt2 = Rt + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1626
				1627	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1628
				1629	// For {LD,ST}RD, Rt must be even, else undefined.
				1630	switch (Inst.getOpcode()) {
				1631	case ARM::STRD:
				1632	case ARM::STRD_PRE:
				1633	case ARM::STRD_POST:
				1634	case ARM::LDRD:
				1635	case ARM::LDRD_PRE:
				1636	case ARM::LDRD_POST:
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1637	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1638	break;
				1639	default:
				1640	break;
				1641	}
				1642	switch (Inst.getOpcode()) {
				1643	case ARM::STRD:
				1644	case ARM::STRD_PRE:
				1645	case ARM::STRD_POST:
				1646	if (P == 0 && W == 1)
				1647	S = MCDisassembler::SoftFail;
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	1648
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1649	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1650	S = MCDisassembler::SoftFail;
				1651	if (type && Rm == 15)
				1652	S = MCDisassembler::SoftFail;
				1653	if (Rt2 == 15)
				1654	S = MCDisassembler::SoftFail;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1655	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1656	S = MCDisassembler::SoftFail;
				1657	break;
				1658	case ARM::STRH:
				1659	case ARM::STRH_PRE:
				1660	case ARM::STRH_POST:
				1661	if (Rt == 15)
				1662	S = MCDisassembler::SoftFail;
				1663	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1664	S = MCDisassembler::SoftFail;
				1665	if (!type && Rm == 15)
				1666	S = MCDisassembler::SoftFail;
				1667	break;
				1668	case ARM::LDRD:
				1669	case ARM::LDRD_PRE:
				1670	case ARM::LDRD_POST:
				1671	if (type && Rn == 15){
				1672	if (Rt2 == 15)
				1673	S = MCDisassembler::SoftFail;
				1674	break;
				1675	}
				1676	if (P == 0 && W == 1)
				1677	S = MCDisassembler::SoftFail;
				1678	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1679	S = MCDisassembler::SoftFail;
				1680	if (!type && writeback && Rn == 15)
				1681	S = MCDisassembler::SoftFail;
				1682	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1683	S = MCDisassembler::SoftFail;
				1684	break;
				1685	case ARM::LDRH:
				1686	case ARM::LDRH_PRE:
				1687	case ARM::LDRH_POST:
				1688	if (type && Rn == 15){
				1689	if (Rt == 15)
				1690	S = MCDisassembler::SoftFail;
				1691	break;
				1692	}
				1693	if (Rt == 15)
				1694	S = MCDisassembler::SoftFail;
				1695	if (!type && Rm == 15)
				1696	S = MCDisassembler::SoftFail;
				1697	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1698	S = MCDisassembler::SoftFail;
				1699	break;
				1700	case ARM::LDRSH:
				1701	case ARM::LDRSH_PRE:
				1702	case ARM::LDRSH_POST:
				1703	case ARM::LDRSB:
				1704	case ARM::LDRSB_PRE:
				1705	case ARM::LDRSB_POST:
				1706	if (type && Rn == 15){
				1707	if (Rt == 15)
				1708	S = MCDisassembler::SoftFail;
				1709	break;
				1710	}
				1711	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1712	S = MCDisassembler::SoftFail;
				1713	if (!type && (Rt == 15 \|\| Rm == 15))
				1714	S = MCDisassembler::SoftFail;
				1715	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1716	S = MCDisassembler::SoftFail;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1717	break;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1718	default:
				1719	break;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1720	}
				1721
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1722	if (writeback) { // Writeback
				1723	if (P)
				1724	U \|= ARMII::IndexModePre << 9;
				1725	else
				1726	U \|= ARMII::IndexModePost << 9;
				1727
				1728	// On stores, the writeback operand precedes Rt.
				1729	switch (Inst.getOpcode()) {
				1730	case ARM::STRD:
				1731	case ARM::STRD_PRE:
				1732	case ARM::STRD_POST:
Owen Anderson	60138ea	2011-08-12 20:02:50 +0000	[diff] [blame]	1733	case ARM::STRH:
				1734	case ARM::STRH_PRE:
				1735	case ARM::STRH_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1736	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1737	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1738	break;
				1739	default:
				1740	break;
				1741	}
				1742	}
				1743
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1744	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1745	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1746	switch (Inst.getOpcode()) {
				1747	case ARM::STRD:
				1748	case ARM::STRD_PRE:
				1749	case ARM::STRD_POST:
				1750	case ARM::LDRD:
				1751	case ARM::LDRD_PRE:
				1752	case ARM::LDRD_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1753	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1754	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1755	break;
				1756	default:
				1757	break;
				1758	}
				1759
				1760	if (writeback) {
				1761	// On loads, the writeback operand comes after Rt.
				1762	switch (Inst.getOpcode()) {
				1763	case ARM::LDRD:
				1764	case ARM::LDRD_PRE:
				1765	case ARM::LDRD_POST:
Owen Anderson	2d1d7a1	2011-08-12 20:36:11 +0000	[diff] [blame]	1766	case ARM::LDRH:
				1767	case ARM::LDRH_PRE:
				1768	case ARM::LDRH_POST:
				1769	case ARM::LDRSH:
				1770	case ARM::LDRSH_PRE:
				1771	case ARM::LDRSH_POST:
				1772	case ARM::LDRSB:
				1773	case ARM::LDRSB_PRE:
				1774	case ARM::LDRSB_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1775	case ARM::LDRHTr:
				1776	case ARM::LDRSBTr:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1777	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1778	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1779	break;
				1780	default:
				1781	break;
				1782	}
				1783	}
				1784
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1785	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1786	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1787
				1788	if (type) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1789	Inst.addOperand(MCOperand::createReg(0));
				1790	Inst.addOperand(MCOperand::createImm(U \| (imm << 4) \| Rm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1791	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1792	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1793	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1794	Inst.addOperand(MCOperand::createImm(U));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1795	}
				1796
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1797	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1798	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1799
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1800	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1801	}
				1802
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1803	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1804	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1805	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1806
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1807	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1808	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1809
				1810	switch (mode) {
				1811	case 0:
				1812	mode = ARM_AM::da;
				1813	break;
				1814	case 1:
				1815	mode = ARM_AM::ia;
				1816	break;
				1817	case 2:
				1818	mode = ARM_AM::db;
				1819	break;
				1820	case 3:
				1821	mode = ARM_AM::ib;
				1822	break;
				1823	}
				1824
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1825	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1826	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1827	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1828
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1829	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1830	}
				1831
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1832	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				1833	uint64_t Address, const void *Decoder) {
				1834	DecodeStatus S = MCDisassembler::Success;
				1835
				1836	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1837	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1838	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1839	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1840
				1841	if (pred == 0xF)
				1842	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1843
				1844	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1845	return MCDisassembler::Fail;
				1846	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1847	return MCDisassembler::Fail;
				1848	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1849	return MCDisassembler::Fail;
				1850	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1851	return MCDisassembler::Fail;
				1852	return S;
				1853	}
				1854
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1855	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1856	unsigned Insn,
				1857	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1858	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1859
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1860	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1861	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1862	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1863
				1864	if (pred == 0xF) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1865	// Ambiguous with RFE and SRS
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1866	switch (Inst.getOpcode()) {
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1867	case ARM::LDMDA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1868	Inst.setOpcode(ARM::RFEDA);
				1869	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1870	case ARM::LDMDA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1871	Inst.setOpcode(ARM::RFEDA_UPD);
				1872	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1873	case ARM::LDMDB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1874	Inst.setOpcode(ARM::RFEDB);
				1875	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1876	case ARM::LDMDB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1877	Inst.setOpcode(ARM::RFEDB_UPD);
				1878	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1879	case ARM::LDMIA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1880	Inst.setOpcode(ARM::RFEIA);
				1881	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1882	case ARM::LDMIA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1883	Inst.setOpcode(ARM::RFEIA_UPD);
				1884	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1885	case ARM::LDMIB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1886	Inst.setOpcode(ARM::RFEIB);
				1887	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1888	case ARM::LDMIB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1889	Inst.setOpcode(ARM::RFEIB_UPD);
				1890	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1891	case ARM::STMDA:
				1892	Inst.setOpcode(ARM::SRSDA);
				1893	break;
				1894	case ARM::STMDA_UPD:
				1895	Inst.setOpcode(ARM::SRSDA_UPD);
				1896	break;
				1897	case ARM::STMDB:
				1898	Inst.setOpcode(ARM::SRSDB);
				1899	break;
				1900	case ARM::STMDB_UPD:
				1901	Inst.setOpcode(ARM::SRSDB_UPD);
				1902	break;
				1903	case ARM::STMIA:
				1904	Inst.setOpcode(ARM::SRSIA);
				1905	break;
				1906	case ARM::STMIA_UPD:
				1907	Inst.setOpcode(ARM::SRSIA_UPD);
				1908	break;
				1909	case ARM::STMIB:
				1910	Inst.setOpcode(ARM::SRSIB);
				1911	break;
				1912	case ARM::STMIB_UPD:
				1913	Inst.setOpcode(ARM::SRSIB_UPD);
				1914	break;
				1915	default:
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1916	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1917	}
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1918
				1919	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1920	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1921	// Check SRS encoding constraints
				1922	if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
				1923	fieldFromInstruction(Insn, 20, 1) == 0))
				1924	return MCDisassembler::Fail;
				1925
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1926	Inst.addOperand(
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1927	MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1928	return S;
				1929	}
				1930
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1931	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1932	}
				1933
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1934	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1935	return MCDisassembler::Fail;
				1936	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1937	return MCDisassembler::Fail; // Tied
				1938	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1939	return MCDisassembler::Fail;
				1940	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1941	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1942
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1943	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1944	}
				1945
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1946	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1947	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1948	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1949	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1950	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1951	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1952
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1953	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	1954
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1955	// This decoder is called from multiple location that do not check
				1956	// the full encoding is valid before they do.
				1957	if (fieldFromInstruction(Insn, 5, 1) != 0 \|\|
				1958	fieldFromInstruction(Insn, 16, 1) != 0 \|\|
				1959	fieldFromInstruction(Insn, 20, 8) != 0x10)
				1960	return MCDisassembler::Fail;
				1961
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1962	// imod == '01' --> UNPREDICTABLE
				1963	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1964	// return failure here. The '01' imod value is unprintable, so there's
				1965	// nothing useful we could do even if we returned UNPREDICTABLE.
				1966
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1967	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1968
				1969	if (imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1970	Inst.setOpcode(ARM::CPS3p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1971	Inst.addOperand(MCOperand::createImm(imod));
				1972	Inst.addOperand(MCOperand::createImm(iflags));
				1973	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1974	} else if (imod && !M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1975	Inst.setOpcode(ARM::CPS2p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1976	Inst.addOperand(MCOperand::createImm(imod));
				1977	Inst.addOperand(MCOperand::createImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1978	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1979	} else if (!imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1980	Inst.setOpcode(ARM::CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1981	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1982	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1983	} else {
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1984	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1985	Inst.setOpcode(ARM::CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1986	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1987	S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1988	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1989
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1990	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1991	}
				1992
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1993	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1994	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1995	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				1996	unsigned M = fieldFromInstruction(Insn, 8, 1);
				1997	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				1998	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1999
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2000	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2001
				2002	// imod == '01' --> UNPREDICTABLE
				2003	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				2004	// return failure here. The '01' imod value is unprintable, so there's
				2005	// nothing useful we could do even if we returned UNPREDICTABLE.
				2006
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2007	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2008
				2009	if (imod && M) {
				2010	Inst.setOpcode(ARM::t2CPS3p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2011	Inst.addOperand(MCOperand::createImm(imod));
				2012	Inst.addOperand(MCOperand::createImm(iflags));
				2013	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2014	} else if (imod && !M) {
				2015	Inst.setOpcode(ARM::t2CPS2p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2016	Inst.addOperand(MCOperand::createImm(imod));
				2017	Inst.addOperand(MCOperand::createImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2018	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2019	} else if (!imod && M) {
				2020	Inst.setOpcode(ARM::t2CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2021	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2022	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2023	} else {
Quentin Colombet	a83d5e9	2013-04-26 17:54:54 +0000	[diff] [blame]	2024	// imod == '00' && M == '0' --> this is a HINT instruction
				2025	int imm = fieldFromInstruction(Insn, 0, 8);
				2026	// HINT are defined only for immediate in [0..4]
				2027	if(imm > 4) return MCDisassembler::Fail;
				2028	Inst.setOpcode(ARM::t2HINT);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2029	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2030	}
				2031
				2032	return S;
				2033	}
				2034
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2035	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2036	uint64_t Address, const void *Decoder) {
				2037	DecodeStatus S = MCDisassembler::Success;
				2038
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2039	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2040	unsigned imm = 0;
				2041
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2042	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				2043	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				2044	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				2045	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2046
				2047	if (Inst.getOpcode() == ARM::t2MOVTi16)
				2048	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2049	return MCDisassembler::Fail;
				2050	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2051	return MCDisassembler::Fail;
				2052
				2053	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2054	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2055
				2056	return S;
				2057	}
				2058
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2059	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2060	uint64_t Address, const void *Decoder) {
				2061	DecodeStatus S = MCDisassembler::Success;
				2062
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2063	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2064	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2065	unsigned imm = 0;
				2066
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2067	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2068	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2069
				2070	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2071	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2072	return MCDisassembler::Fail;
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2073
				2074	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2075	return MCDisassembler::Fail;
				2076
				2077	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2078	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2079
				2080	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2081	return MCDisassembler::Fail;
				2082
				2083	return S;
				2084	}
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2085
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2086	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2087	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2088	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2089
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2090	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2091	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2092	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2093	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2094	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2095
				2096	if (pred == 0xF)
				2097	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2098
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2099	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2100	return MCDisassembler::Fail;
				2101	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2102	return MCDisassembler::Fail;
				2103	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2104	return MCDisassembler::Fail;
				2105	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2106	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2107
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2108	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2109	return MCDisassembler::Fail;
Owen Anderson	2f7aa73	2011-08-11 22:05:38 +0000	[diff] [blame]	2110
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2111	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2112	}
				2113
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2114	static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
				2115	uint64_t Address, const void *Decoder) {
				2116	DecodeStatus S = MCDisassembler::Success;
				2117
				2118	unsigned Pred = fieldFromInstruction(Insn, 28, 4);
				2119	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2120	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2121
				2122	if (Pred == 0xF)
				2123	return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
				2124
				2125	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2126	return MCDisassembler::Fail;
				2127	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2128	return MCDisassembler::Fail;
				2129	if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
				2130	return MCDisassembler::Fail;
				2131
				2132	return S;
				2133	}
				2134
				2135	static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
				2136	uint64_t Address, const void *Decoder) {
				2137	DecodeStatus S = MCDisassembler::Success;
				2138
				2139	unsigned Imm = fieldFromInstruction(Insn, 9, 1);
				2140
				2141	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	2142	const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
				2143
				2144	if (!FeatureBits[ARM::HasV8_1aOps] \|\|
				2145	!FeatureBits[ARM::HasV8Ops])
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2146	return MCDisassembler::Fail;
				2147
				2148	// Decoder can be called from DecodeTST, which does not check the full
				2149	// encoding is valid.
				2150	if (fieldFromInstruction(Insn, 20,12) != 0xf11 \|\|
				2151	fieldFromInstruction(Insn, 4,4) != 0)
				2152	return MCDisassembler::Fail;
				2153	if (fieldFromInstruction(Insn, 10,10) != 0 \|\|
				2154	fieldFromInstruction(Insn, 0,4) != 0)
				2155	S = MCDisassembler::SoftFail;
				2156
				2157	Inst.setOpcode(ARM::SETPAN);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2158	Inst.addOperand(MCOperand::createImm(Imm));
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2159
				2160	return S;
				2161	}
				2162
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2163	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2164	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2165	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2166
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2167	unsigned add = fieldFromInstruction(Val, 12, 1);
				2168	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2169	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2170
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2171	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2172	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2173
				2174	if (!add) imm *= -1;
				2175	if (imm == 0 && !add) imm = INT32_MIN;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2176	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2177	if (Rn == 15)
				2178	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2179
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2180	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2181	}
				2182
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2183	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2184	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2185	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2186
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2187	unsigned Rn = fieldFromInstruction(Val, 9, 4);
Oliver Stannard	65b8538	2016-01-25 10:26:26 +0000	[diff] [blame]	2188	// U == 1 to add imm, 0 to subtract it.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2189	unsigned U = fieldFromInstruction(Val, 8, 1);
				2190	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2191
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2192	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2193	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2194
				2195	if (U)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2196	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2197	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2198	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2199
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2200	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2201	}
				2202
Oliver Stannard	65b8538	2016-01-25 10:26:26 +0000	[diff] [blame]	2203	static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
				2204	uint64_t Address, const void *Decoder) {
				2205	DecodeStatus S = MCDisassembler::Success;
				2206
				2207	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2208	// U == 1 to add imm, 0 to subtract it.
				2209	unsigned U = fieldFromInstruction(Val, 8, 1);
				2210	unsigned imm = fieldFromInstruction(Val, 0, 8);
				2211
				2212	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2213	return MCDisassembler::Fail;
				2214
				2215	if (U)
				2216	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
				2217	else
				2218	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
				2219
				2220	return S;
				2221	}
				2222
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2223	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2224	uint64_t Address, const void *Decoder) {
				2225	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2226	}
				2227
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2228	static DecodeStatus
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2229	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2230	uint64_t Address, const void *Decoder) {
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2231	DecodeStatus Status = MCDisassembler::Success;
				2232
				2233	// Note the J1 and J2 values are from the encoded instruction. So here
				2234	// change them to I1 and I2 values via as documented:
				2235	// I1 = NOT(J1 EOR S);
				2236	// I2 = NOT(J2 EOR S);
				2237	// and build the imm32 with one trailing zero as documented:
				2238	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2239	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2240	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2241	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2242	unsigned I1 = !(J1 ^ S);
				2243	unsigned I2 = !(J2 ^ S);
				2244	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2245	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2246	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
Amaury de la Vieuville	bd2b610	2013-06-13 16:41:55 +0000	[diff] [blame]	2247	int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2248	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2249	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2250	Inst.addOperand(MCOperand::createImm(imm32));
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2251
				2252	return Status;
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2253	}
				2254
				2255	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2256	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2257	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2258	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2259
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2260	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2261	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2262
				2263	if (pred == 0xF) {
				2264	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2265	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2266	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2267	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2268	Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2269	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2270	}
				2271
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2272	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2273	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2274	Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2275	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2276	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2277
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2278	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2279	}
				2280
				2281
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2282	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2283	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2284	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2285
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2286	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2287	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2288
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2289	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2290	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2291	if (!align)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2292	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2293	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2294	Inst.addOperand(MCOperand::createImm(4 << align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2295
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2296	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2297	}
				2298
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2299	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2300	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2301	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2302
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2303	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2304	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2305	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2306	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2307	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2308	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2309
				2310	// First output register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2311	switch (Inst.getOpcode()) {
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2312	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2313	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2314	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2315	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2316	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2317	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2318	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2319	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2320	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2321	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2322	return MCDisassembler::Fail;
				2323	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2324	case ARM::VLD2b16:
				2325	case ARM::VLD2b32:
				2326	case ARM::VLD2b8:
				2327	case ARM::VLD2b16wb_fixed:
				2328	case ARM::VLD2b16wb_register:
				2329	case ARM::VLD2b32wb_fixed:
				2330	case ARM::VLD2b32wb_register:
				2331	case ARM::VLD2b8wb_fixed:
				2332	case ARM::VLD2b8wb_register:
				2333	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2334	return MCDisassembler::Fail;
				2335	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2336	default:
				2337	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2338	return MCDisassembler::Fail;
				2339	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2340
				2341	// Second output register
				2342	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2343	case ARM::VLD3d8:
				2344	case ARM::VLD3d16:
				2345	case ARM::VLD3d32:
				2346	case ARM::VLD3d8_UPD:
				2347	case ARM::VLD3d16_UPD:
				2348	case ARM::VLD3d32_UPD:
				2349	case ARM::VLD4d8:
				2350	case ARM::VLD4d16:
				2351	case ARM::VLD4d32:
				2352	case ARM::VLD4d8_UPD:
				2353	case ARM::VLD4d16_UPD:
				2354	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2355	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2356	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2357	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2358	case ARM::VLD3q8:
				2359	case ARM::VLD3q16:
				2360	case ARM::VLD3q32:
				2361	case ARM::VLD3q8_UPD:
				2362	case ARM::VLD3q16_UPD:
				2363	case ARM::VLD3q32_UPD:
				2364	case ARM::VLD4q8:
				2365	case ARM::VLD4q16:
				2366	case ARM::VLD4q32:
				2367	case ARM::VLD4q8_UPD:
				2368	case ARM::VLD4q16_UPD:
				2369	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2370	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2371	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2372	default:
				2373	break;
				2374	}
				2375
				2376	// Third output register
				2377	switch(Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2378	case ARM::VLD3d8:
				2379	case ARM::VLD3d16:
				2380	case ARM::VLD3d32:
				2381	case ARM::VLD3d8_UPD:
				2382	case ARM::VLD3d16_UPD:
				2383	case ARM::VLD3d32_UPD:
				2384	case ARM::VLD4d8:
				2385	case ARM::VLD4d16:
				2386	case ARM::VLD4d32:
				2387	case ARM::VLD4d8_UPD:
				2388	case ARM::VLD4d16_UPD:
				2389	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2390	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2391	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2392	break;
				2393	case ARM::VLD3q8:
				2394	case ARM::VLD3q16:
				2395	case ARM::VLD3q32:
				2396	case ARM::VLD3q8_UPD:
				2397	case ARM::VLD3q16_UPD:
				2398	case ARM::VLD3q32_UPD:
				2399	case ARM::VLD4q8:
				2400	case ARM::VLD4q16:
				2401	case ARM::VLD4q32:
				2402	case ARM::VLD4q8_UPD:
				2403	case ARM::VLD4q16_UPD:
				2404	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2405	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2406	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2407	break;
				2408	default:
				2409	break;
				2410	}
				2411
				2412	// Fourth output register
				2413	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2414	case ARM::VLD4d8:
				2415	case ARM::VLD4d16:
				2416	case ARM::VLD4d32:
				2417	case ARM::VLD4d8_UPD:
				2418	case ARM::VLD4d16_UPD:
				2419	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2420	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2421	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2422	break;
				2423	case ARM::VLD4q8:
				2424	case ARM::VLD4q16:
				2425	case ARM::VLD4q32:
				2426	case ARM::VLD4q8_UPD:
				2427	case ARM::VLD4q16_UPD:
				2428	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2429	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2430	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2431	break;
				2432	default:
				2433	break;
				2434	}
				2435
				2436	// Writeback operand
				2437	switch (Inst.getOpcode()) {
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2438	case ARM::VLD1d8wb_fixed:
				2439	case ARM::VLD1d16wb_fixed:
				2440	case ARM::VLD1d32wb_fixed:
				2441	case ARM::VLD1d64wb_fixed:
				2442	case ARM::VLD1d8wb_register:
				2443	case ARM::VLD1d16wb_register:
				2444	case ARM::VLD1d32wb_register:
				2445	case ARM::VLD1d64wb_register:
				2446	case ARM::VLD1q8wb_fixed:
				2447	case ARM::VLD1q16wb_fixed:
				2448	case ARM::VLD1q32wb_fixed:
				2449	case ARM::VLD1q64wb_fixed:
				2450	case ARM::VLD1q8wb_register:
				2451	case ARM::VLD1q16wb_register:
				2452	case ARM::VLD1q32wb_register:
				2453	case ARM::VLD1q64wb_register:
Jim Grosbach	92fd05e	2011-10-24 23:26:05 +0000	[diff] [blame]	2454	case ARM::VLD1d8Twb_fixed:
				2455	case ARM::VLD1d8Twb_register:
				2456	case ARM::VLD1d16Twb_fixed:
				2457	case ARM::VLD1d16Twb_register:
				2458	case ARM::VLD1d32Twb_fixed:
				2459	case ARM::VLD1d32Twb_register:
				2460	case ARM::VLD1d64Twb_fixed:
				2461	case ARM::VLD1d64Twb_register:
Jim Grosbach	17ec1a1	2011-10-25 00:14:01 +0000	[diff] [blame]	2462	case ARM::VLD1d8Qwb_fixed:
				2463	case ARM::VLD1d8Qwb_register:
				2464	case ARM::VLD1d16Qwb_fixed:
				2465	case ARM::VLD1d16Qwb_register:
				2466	case ARM::VLD1d32Qwb_fixed:
				2467	case ARM::VLD1d32Qwb_register:
				2468	case ARM::VLD1d64Qwb_fixed:
				2469	case ARM::VLD1d64Qwb_register:
Jim Grosbach	d146a02	2011-12-09 21:28:25 +0000	[diff] [blame]	2470	case ARM::VLD2d8wb_fixed:
				2471	case ARM::VLD2d16wb_fixed:
				2472	case ARM::VLD2d32wb_fixed:
				2473	case ARM::VLD2q8wb_fixed:
				2474	case ARM::VLD2q16wb_fixed:
				2475	case ARM::VLD2q32wb_fixed:
				2476	case ARM::VLD2d8wb_register:
				2477	case ARM::VLD2d16wb_register:
				2478	case ARM::VLD2d32wb_register:
				2479	case ARM::VLD2q8wb_register:
				2480	case ARM::VLD2q16wb_register:
				2481	case ARM::VLD2q32wb_register:
				2482	case ARM::VLD2b8wb_fixed:
				2483	case ARM::VLD2b16wb_fixed:
				2484	case ARM::VLD2b32wb_fixed:
				2485	case ARM::VLD2b8wb_register:
				2486	case ARM::VLD2b16wb_register:
				2487	case ARM::VLD2b32wb_register:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2488	Inst.addOperand(MCOperand::createImm(0));
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2489	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2490	case ARM::VLD3d8_UPD:
				2491	case ARM::VLD3d16_UPD:
				2492	case ARM::VLD3d32_UPD:
				2493	case ARM::VLD3q8_UPD:
				2494	case ARM::VLD3q16_UPD:
				2495	case ARM::VLD3q32_UPD:
				2496	case ARM::VLD4d8_UPD:
				2497	case ARM::VLD4d16_UPD:
				2498	case ARM::VLD4d32_UPD:
				2499	case ARM::VLD4q8_UPD:
				2500	case ARM::VLD4q16_UPD:
				2501	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2502	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2503	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2504	break;
				2505	default:
				2506	break;
				2507	}
				2508
				2509	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2510	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2511	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2512
				2513	// AddrMode6 Offset (register)
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2514	switch (Inst.getOpcode()) {
				2515	default:
				2516	// The below have been updated to have explicit am6offset split
				2517	// between fixed and register offset. For those instructions not
				2518	// yet updated, we need to add an additional reg0 operand for the
				2519	// fixed variant.
				2520	//
				2521	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2522	if (Rm == 0xd) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2523	Inst.addOperand(MCOperand::createReg(0));
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2524	break;
				2525	}
				2526	// Fall through to handle the register offset variant.
				2527	case ARM::VLD1d8wb_fixed:
				2528	case ARM::VLD1d16wb_fixed:
				2529	case ARM::VLD1d32wb_fixed:
				2530	case ARM::VLD1d64wb_fixed:
Owen Anderson	8a6ebd0	2011-10-27 22:53:10 +0000	[diff] [blame]	2531	case ARM::VLD1d8Twb_fixed:
				2532	case ARM::VLD1d16Twb_fixed:
				2533	case ARM::VLD1d32Twb_fixed:
				2534	case ARM::VLD1d64Twb_fixed:
Owen Anderson	40703f4	2011-10-31 17:17:32 +0000	[diff] [blame]	2535	case ARM::VLD1d8Qwb_fixed:
				2536	case ARM::VLD1d16Qwb_fixed:
				2537	case ARM::VLD1d32Qwb_fixed:
				2538	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2539	case ARM::VLD1d8wb_register:
				2540	case ARM::VLD1d16wb_register:
				2541	case ARM::VLD1d32wb_register:
				2542	case ARM::VLD1d64wb_register:
				2543	case ARM::VLD1q8wb_fixed:
				2544	case ARM::VLD1q16wb_fixed:
				2545	case ARM::VLD1q32wb_fixed:
				2546	case ARM::VLD1q64wb_fixed:
				2547	case ARM::VLD1q8wb_register:
				2548	case ARM::VLD1q16wb_register:
				2549	case ARM::VLD1q32wb_register:
				2550	case ARM::VLD1q64wb_register:
				2551	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2552	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2553	// increment and we need to add the register operand to the instruction.
				2554	if (Rm != 0xD && Rm != 0xF &&
				2555	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2556	return MCDisassembler::Fail;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2557	break;
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2558	case ARM::VLD2d8wb_fixed:
				2559	case ARM::VLD2d16wb_fixed:
				2560	case ARM::VLD2d32wb_fixed:
				2561	case ARM::VLD2b8wb_fixed:
				2562	case ARM::VLD2b16wb_fixed:
				2563	case ARM::VLD2b32wb_fixed:
				2564	case ARM::VLD2q8wb_fixed:
				2565	case ARM::VLD2q16wb_fixed:
				2566	case ARM::VLD2q32wb_fixed:
				2567	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2568	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2569
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2570	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2571	}
				2572
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2573	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
				2574	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2575	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2576	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2577	if (type == 6 && (align & 2)) return MCDisassembler::Fail;
				2578	if (type == 7 && (align & 2)) return MCDisassembler::Fail;
				2579	if (type == 10 && align == 3) return MCDisassembler::Fail;
				2580
				2581	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2582	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2583	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2584	}
				2585
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2586	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
				2587	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2588	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2589	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2590
				2591	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2592	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2593	if (type == 8 && align == 3) return MCDisassembler::Fail;
				2594	if (type == 9 && align == 3) return MCDisassembler::Fail;
				2595
				2596	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2597	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2598	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2599	}
				2600
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2601	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
				2602	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2603	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2604	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2605
				2606	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2607	if (align & 2) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2608
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2609	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2610	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2611	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2612	}
				2613
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2614	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
				2615	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2616	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2617	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2618
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2619	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2620	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2621	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2622	}
				2623
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2624	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2625	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2626	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2627
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2628	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2629	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2630	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2631	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2632	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2633	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2634
				2635	// Writeback Operand
				2636	switch (Inst.getOpcode()) {
Jim Grosbach	05df460	2011-10-31 21:50:31 +0000	[diff] [blame]	2637	case ARM::VST1d8wb_fixed:
				2638	case ARM::VST1d16wb_fixed:
				2639	case ARM::VST1d32wb_fixed:
				2640	case ARM::VST1d64wb_fixed:
				2641	case ARM::VST1d8wb_register:
				2642	case ARM::VST1d16wb_register:
				2643	case ARM::VST1d32wb_register:
				2644	case ARM::VST1d64wb_register:
				2645	case ARM::VST1q8wb_fixed:
				2646	case ARM::VST1q16wb_fixed:
				2647	case ARM::VST1q32wb_fixed:
				2648	case ARM::VST1q64wb_fixed:
				2649	case ARM::VST1q8wb_register:
				2650	case ARM::VST1q16wb_register:
				2651	case ARM::VST1q32wb_register:
				2652	case ARM::VST1q64wb_register:
Jim Grosbach	98d032f	2011-11-29 22:38:04 +0000	[diff] [blame]	2653	case ARM::VST1d8Twb_fixed:
				2654	case ARM::VST1d16Twb_fixed:
				2655	case ARM::VST1d32Twb_fixed:
				2656	case ARM::VST1d64Twb_fixed:
				2657	case ARM::VST1d8Twb_register:
				2658	case ARM::VST1d16Twb_register:
				2659	case ARM::VST1d32Twb_register:
				2660	case ARM::VST1d64Twb_register:
Jim Grosbach	5ee209c	2011-11-29 22:58:48 +0000	[diff] [blame]	2661	case ARM::VST1d8Qwb_fixed:
				2662	case ARM::VST1d16Qwb_fixed:
				2663	case ARM::VST1d32Qwb_fixed:
				2664	case ARM::VST1d64Qwb_fixed:
				2665	case ARM::VST1d8Qwb_register:
				2666	case ARM::VST1d16Qwb_register:
				2667	case ARM::VST1d32Qwb_register:
				2668	case ARM::VST1d64Qwb_register:
Jim Grosbach	88ac761	2011-12-14 21:32:11 +0000	[diff] [blame]	2669	case ARM::VST2d8wb_fixed:
				2670	case ARM::VST2d16wb_fixed:
				2671	case ARM::VST2d32wb_fixed:
				2672	case ARM::VST2d8wb_register:
				2673	case ARM::VST2d16wb_register:
				2674	case ARM::VST2d32wb_register:
				2675	case ARM::VST2q8wb_fixed:
				2676	case ARM::VST2q16wb_fixed:
				2677	case ARM::VST2q32wb_fixed:
				2678	case ARM::VST2q8wb_register:
				2679	case ARM::VST2q16wb_register:
				2680	case ARM::VST2q32wb_register:
				2681	case ARM::VST2b8wb_fixed:
				2682	case ARM::VST2b16wb_fixed:
				2683	case ARM::VST2b32wb_fixed:
				2684	case ARM::VST2b8wb_register:
				2685	case ARM::VST2b16wb_register:
				2686	case ARM::VST2b32wb_register:
Kevin Enderby	72f18bb	2012-04-11 22:40:17 +0000	[diff] [blame]	2687	if (Rm == 0xF)
				2688	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2689	Inst.addOperand(MCOperand::createImm(0));
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2690	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2691	case ARM::VST3d8_UPD:
				2692	case ARM::VST3d16_UPD:
				2693	case ARM::VST3d32_UPD:
				2694	case ARM::VST3q8_UPD:
				2695	case ARM::VST3q16_UPD:
				2696	case ARM::VST3q32_UPD:
				2697	case ARM::VST4d8_UPD:
				2698	case ARM::VST4d16_UPD:
				2699	case ARM::VST4d32_UPD:
				2700	case ARM::VST4q8_UPD:
				2701	case ARM::VST4q16_UPD:
				2702	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2703	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2704	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2705	break;
				2706	default:
				2707	break;
				2708	}
				2709
				2710	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2711	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2712	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2713
				2714	// AddrMode6 Offset (register)
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2715	switch (Inst.getOpcode()) {
				2716	default:
				2717	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2718	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2719	else if (Rm != 0xF) {
				2720	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2721	return MCDisassembler::Fail;
				2722	}
				2723	break;
				2724	case ARM::VST1d8wb_fixed:
				2725	case ARM::VST1d16wb_fixed:
				2726	case ARM::VST1d32wb_fixed:
				2727	case ARM::VST1d64wb_fixed:
				2728	case ARM::VST1q8wb_fixed:
				2729	case ARM::VST1q16wb_fixed:
				2730	case ARM::VST1q32wb_fixed:
				2731	case ARM::VST1q64wb_fixed:
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2732	case ARM::VST1d8Twb_fixed:
				2733	case ARM::VST1d16Twb_fixed:
				2734	case ARM::VST1d32Twb_fixed:
				2735	case ARM::VST1d64Twb_fixed:
				2736	case ARM::VST1d8Qwb_fixed:
				2737	case ARM::VST1d16Qwb_fixed:
				2738	case ARM::VST1d32Qwb_fixed:
				2739	case ARM::VST1d64Qwb_fixed:
				2740	case ARM::VST2d8wb_fixed:
				2741	case ARM::VST2d16wb_fixed:
				2742	case ARM::VST2d32wb_fixed:
				2743	case ARM::VST2q8wb_fixed:
				2744	case ARM::VST2q16wb_fixed:
				2745	case ARM::VST2q32wb_fixed:
				2746	case ARM::VST2b8wb_fixed:
				2747	case ARM::VST2b16wb_fixed:
				2748	case ARM::VST2b32wb_fixed:
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2749	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2750	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2751
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2752
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2753	// First input register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2754	switch (Inst.getOpcode()) {
				2755	case ARM::VST1q16:
				2756	case ARM::VST1q32:
				2757	case ARM::VST1q64:
				2758	case ARM::VST1q8:
				2759	case ARM::VST1q16wb_fixed:
				2760	case ARM::VST1q16wb_register:
				2761	case ARM::VST1q32wb_fixed:
				2762	case ARM::VST1q32wb_register:
				2763	case ARM::VST1q64wb_fixed:
				2764	case ARM::VST1q64wb_register:
				2765	case ARM::VST1q8wb_fixed:
				2766	case ARM::VST1q8wb_register:
				2767	case ARM::VST2d16:
				2768	case ARM::VST2d32:
				2769	case ARM::VST2d8:
				2770	case ARM::VST2d16wb_fixed:
				2771	case ARM::VST2d16wb_register:
				2772	case ARM::VST2d32wb_fixed:
				2773	case ARM::VST2d32wb_register:
				2774	case ARM::VST2d8wb_fixed:
				2775	case ARM::VST2d8wb_register:
				2776	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2777	return MCDisassembler::Fail;
				2778	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2779	case ARM::VST2b16:
				2780	case ARM::VST2b32:
				2781	case ARM::VST2b8:
				2782	case ARM::VST2b16wb_fixed:
				2783	case ARM::VST2b16wb_register:
				2784	case ARM::VST2b32wb_fixed:
				2785	case ARM::VST2b32wb_register:
				2786	case ARM::VST2b8wb_fixed:
				2787	case ARM::VST2b8wb_register:
				2788	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2789	return MCDisassembler::Fail;
				2790	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2791	default:
				2792	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2793	return MCDisassembler::Fail;
				2794	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2795
				2796	// Second input register
				2797	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2798	case ARM::VST3d8:
				2799	case ARM::VST3d16:
				2800	case ARM::VST3d32:
				2801	case ARM::VST3d8_UPD:
				2802	case ARM::VST3d16_UPD:
				2803	case ARM::VST3d32_UPD:
				2804	case ARM::VST4d8:
				2805	case ARM::VST4d16:
				2806	case ARM::VST4d32:
				2807	case ARM::VST4d8_UPD:
				2808	case ARM::VST4d16_UPD:
				2809	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2810	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2811	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2812	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2813	case ARM::VST3q8:
				2814	case ARM::VST3q16:
				2815	case ARM::VST3q32:
				2816	case ARM::VST3q8_UPD:
				2817	case ARM::VST3q16_UPD:
				2818	case ARM::VST3q32_UPD:
				2819	case ARM::VST4q8:
				2820	case ARM::VST4q16:
				2821	case ARM::VST4q32:
				2822	case ARM::VST4q8_UPD:
				2823	case ARM::VST4q16_UPD:
				2824	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2825	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2826	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2827	break;
				2828	default:
				2829	break;
				2830	}
				2831
				2832	// Third input register
				2833	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2834	case ARM::VST3d8:
				2835	case ARM::VST3d16:
				2836	case ARM::VST3d32:
				2837	case ARM::VST3d8_UPD:
				2838	case ARM::VST3d16_UPD:
				2839	case ARM::VST3d32_UPD:
				2840	case ARM::VST4d8:
				2841	case ARM::VST4d16:
				2842	case ARM::VST4d32:
				2843	case ARM::VST4d8_UPD:
				2844	case ARM::VST4d16_UPD:
				2845	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2846	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2847	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2848	break;
				2849	case ARM::VST3q8:
				2850	case ARM::VST3q16:
				2851	case ARM::VST3q32:
				2852	case ARM::VST3q8_UPD:
				2853	case ARM::VST3q16_UPD:
				2854	case ARM::VST3q32_UPD:
				2855	case ARM::VST4q8:
				2856	case ARM::VST4q16:
				2857	case ARM::VST4q32:
				2858	case ARM::VST4q8_UPD:
				2859	case ARM::VST4q16_UPD:
				2860	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2861	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2862	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2863	break;
				2864	default:
				2865	break;
				2866	}
				2867
				2868	// Fourth input register
				2869	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2870	case ARM::VST4d8:
				2871	case ARM::VST4d16:
				2872	case ARM::VST4d32:
				2873	case ARM::VST4d8_UPD:
				2874	case ARM::VST4d16_UPD:
				2875	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2876	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2877	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2878	break;
				2879	case ARM::VST4q8:
				2880	case ARM::VST4q16:
				2881	case ARM::VST4q32:
				2882	case ARM::VST4q8_UPD:
				2883	case ARM::VST4q16_UPD:
				2884	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2885	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2886	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2887	break;
				2888	default:
				2889	break;
				2890	}
				2891
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2892	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2893	}
				2894
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2895	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2896	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2897	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2898
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2899	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2900	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2901	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2902	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2903	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2904	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2905
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2906	if (size == 0 && align == 1)
				2907	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2908	align *= (1 << size);
				2909
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2910	switch (Inst.getOpcode()) {
				2911	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2912	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2913	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2914	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2915	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2916	return MCDisassembler::Fail;
				2917	break;
				2918	default:
				2919	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2920	return MCDisassembler::Fail;
				2921	break;
				2922	}
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2923	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2924	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2925	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2926	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2927
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2928	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2929	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2930	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2931
Jim Grosbach	a68c9a8	2011-11-30 19:35:44 +0000	[diff] [blame]	2932	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2933	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2934	// increment and we need to add the register operand to the instruction.
				2935	if (Rm != 0xD && Rm != 0xF &&
				2936	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2937	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2938
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2939	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2940	}
				2941
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2942	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2943	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2944	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2945
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2946	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2947	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2948	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2949	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2950	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2951	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2952	align = 2size;
				2953
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2954	switch (Inst.getOpcode()) {
				2955	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2956	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2957	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2958	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2959	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2960	return MCDisassembler::Fail;
				2961	break;
Jim Grosbach	ed428bc	2012-03-06 23:10:38 +0000	[diff] [blame]	2962	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2963	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2964	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2965	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2966	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2967	return MCDisassembler::Fail;
				2968	break;
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2969	default:
				2970	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2971	return MCDisassembler::Fail;
				2972	break;
				2973	}
Kevin Enderby	520eb3b	2012-03-06 18:33:12 +0000	[diff] [blame]	2974
				2975	if (Rm != 0xF)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2976	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2977
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2978	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2979	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2980	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2981
Kevin Enderby	29ae538	2012-04-17 00:49:27 +0000	[diff] [blame]	2982	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2983	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2984	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2985	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2986
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2987	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2988	}
				2989
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2990	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2991	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2992	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2993
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2994	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2995	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2996	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2997	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2998	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2999
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3000	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3001	return MCDisassembler::Fail;
				3002	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				3003	return MCDisassembler::Fail;
				3004	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				3005	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	3006	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3007	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3008	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3009	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3010
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3011	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3012	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3013	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3014
				3015	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3016	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3017	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3018	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3019	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3020	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3021
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3022	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3023	}
				3024
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3025	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3026	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3027	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3028
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3029	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3030	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3031	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3032	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3033	unsigned size = fieldFromInstruction(Insn, 6, 2);
				3034	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				3035	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3036
				3037	if (size == 0x3) {
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	3038	if (align == 0)
				3039	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3040	align = 16;
				3041	} else {
				3042	if (size == 2) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3043	align *= 8;
				3044	} else {
				3045	size = 1 << size;
				3046	align = 4size;
				3047	}
				3048	}
				3049
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3050	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3051	return MCDisassembler::Fail;
				3052	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				3053	return MCDisassembler::Fail;
				3054	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				3055	return MCDisassembler::Fail;
				3056	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				3057	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	3058	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3059	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3060	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3061	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3062
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3063	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3064	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3065	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3066
				3067	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3068	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3069	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3070	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3071	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3072	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3073
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3074	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3075	}
				3076
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3077	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3078	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3079	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3080	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3081
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3082	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3083	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3084	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				3085	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				3086	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				3087	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				3088	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				3089	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3090
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3091	if (Q) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3092	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3093	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3094	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3095	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3096	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3097	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3098
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3099	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3100
				3101	switch (Inst.getOpcode()) {
				3102	case ARM::VORRiv4i16:
				3103	case ARM::VORRiv2i32:
				3104	case ARM::VBICiv4i16:
				3105	case ARM::VBICiv2i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3106	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3107	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3108	break;
				3109	case ARM::VORRiv8i16:
				3110	case ARM::VORRiv4i32:
				3111	case ARM::VBICiv8i16:
				3112	case ARM::VBICiv4i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3113	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3114	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3115	break;
				3116	default:
				3117	break;
				3118	}
				3119
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3120	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3121	}
				3122
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3123	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3124	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3125	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3126
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3127	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3128	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3129	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3130	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3131	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3132
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3133	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3134	return MCDisassembler::Fail;
				3135	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3136	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3137	Inst.addOperand(MCOperand::createImm(8 << size));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3138
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3139	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3140	}
				3141
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3142	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3143	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3144	Inst.addOperand(MCOperand::createImm(8 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3145	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3146	}
				3147
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3148	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3149	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3150	Inst.addOperand(MCOperand::createImm(16 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3151	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3152	}
				3153
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3154	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3155	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3156	Inst.addOperand(MCOperand::createImm(32 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3157	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3158	}
				3159
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3160	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3161	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3162	Inst.addOperand(MCOperand::createImm(64 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3163	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3164	}
				3165
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3166	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3167	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3168	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3169
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3170	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3171	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3172	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3173	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3174	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3175	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3176	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3177
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3178	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3179	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3180	if (op) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3181	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3182	return MCDisassembler::Fail; // Writeback
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3183	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3184
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	3185	switch (Inst.getOpcode()) {
				3186	case ARM::VTBL2:
				3187	case ARM::VTBX2:
				3188	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3189	return MCDisassembler::Fail;
				3190	break;
				3191	default:
				3192	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3193	return MCDisassembler::Fail;
				3194	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3195
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3196	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3197	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3198
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3199	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3200	}
				3201
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3202	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3203	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3204	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3205
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3206	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3207	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3208
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3209	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3210	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3211
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3212	switch(Inst.getOpcode()) {
Owen Anderson	5658b49	2011-08-26 19:39:26 +0000	[diff] [blame]	3213	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3214	return MCDisassembler::Fail;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3215	case ARM::tADR:
Owen Anderson	240d20a	2011-08-26 21:47:57 +0000	[diff] [blame]	3216	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3217	case ARM::tADDrSPi:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3218	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3219	break;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3220	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3221
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3222	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3223	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3224	}
				3225
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3226	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3227	uint64_t Address, const void *Decoder) {
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3228	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3229	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3230	Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3231	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3232	}
				3233
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3234	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3235	uint64_t Address, const void *Decoder) {
Kevin Enderby	cabbae6	2012-05-04 22:09:52 +0000	[diff] [blame]	3236	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3237	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3238	Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3239	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3240	}
				3241
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3242	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3243	uint64_t Address, const void *Decoder) {
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3244	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3245	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3246	Inst.addOperand(MCOperand::createImm(Val << 1));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3247	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3248	}
				3249
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3250	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3251	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3252	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3253
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3254	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3255	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3256
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3257	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3258	return MCDisassembler::Fail;
				3259	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3260	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3261
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3262	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3263	}
				3264
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3265	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3266	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3267	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3268
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3269	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3270	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3271
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3272	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3273	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3274	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3275
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3276	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3277	}
				3278
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3279	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3280	uint64_t Address, const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3281	unsigned imm = Val << 2;
				3282
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3283	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3284	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3285
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3286	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3287	}
				3288
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3289	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3290	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3291	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3292	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3293
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3294	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3295	}
				3296
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3297	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3298	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3299	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3300
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3301	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3302	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3303	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3304
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3305	// Thumb stores cannot use PC as dest register.
				3306	switch (Inst.getOpcode()) {
				3307	case ARM::t2STRHs:
				3308	case ARM::t2STRBs:
				3309	case ARM::t2STRs:
				3310	if (Rn == 15)
				3311	return MCDisassembler::Fail;
				3312	default:
				3313	break;
				3314	}
				3315
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3316	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3317	return MCDisassembler::Fail;
				3318	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3319	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3320	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3321
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3322	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3323	}
				3324
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3325	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3326	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3327	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3328
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3329	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3330	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3331
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3332	const FeatureBitset &featureBits =
				3333	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3334
				3335	bool hasMP = featureBits[ARM::FeatureMP];
				3336	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3337
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3338	if (Rn == 15) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3339	switch (Inst.getOpcode()) {
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3340	case ARM::t2LDRBs:
				3341	Inst.setOpcode(ARM::t2LDRBpci);
				3342	break;
				3343	case ARM::t2LDRHs:
				3344	Inst.setOpcode(ARM::t2LDRHpci);
				3345	break;
				3346	case ARM::t2LDRSHs:
				3347	Inst.setOpcode(ARM::t2LDRSHpci);
				3348	break;
				3349	case ARM::t2LDRSBs:
				3350	Inst.setOpcode(ARM::t2LDRSBpci);
				3351	break;
				3352	case ARM::t2LDRs:
				3353	Inst.setOpcode(ARM::t2LDRpci);
				3354	break;
				3355	case ARM::t2PLDs:
				3356	Inst.setOpcode(ARM::t2PLDpci);
				3357	break;
				3358	case ARM::t2PLIs:
				3359	Inst.setOpcode(ARM::t2PLIpci);
				3360	break;
				3361	default:
				3362	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3363	}
				3364
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3365	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3366	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3367
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3368	if (Rt == 15) {
				3369	switch (Inst.getOpcode()) {
				3370	case ARM::t2LDRSHs:
				3371	return MCDisassembler::Fail;
				3372	case ARM::t2LDRHs:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3373	Inst.setOpcode(ARM::t2PLDWs);
				3374	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3375	case ARM::t2LDRSBs:
				3376	Inst.setOpcode(ARM::t2PLIs);
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3377	default:
				3378	break;
				3379	}
				3380	}
				3381
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3382	switch (Inst.getOpcode()) {
				3383	case ARM::t2PLDs:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3384	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3385	case ARM::t2PLIs:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3386	if (!hasV7Ops)
				3387	return MCDisassembler::Fail;
				3388	break;
				3389	case ARM::t2PLDWs:
				3390	if (!hasV7Ops \|\| !hasMP)
				3391	return MCDisassembler::Fail;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3392	break;
				3393	default:
				3394	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3395	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3396	}
				3397
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3398	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3399	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3400	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3401	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3402	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3403
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3404	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3405	}
				3406
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3407	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				3408	uint64_t Address, const void* Decoder) {
				3409	DecodeStatus S = MCDisassembler::Success;
				3410
				3411	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3412	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3413	unsigned U = fieldFromInstruction(Insn, 9, 1);
				3414	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3415	imm \|= (U << 8);
				3416	imm \|= (Rn << 9);
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3417	unsigned add = fieldFromInstruction(Insn, 9, 1);
				3418
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3419	const FeatureBitset &featureBits =
				3420	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3421
				3422	bool hasMP = featureBits[ARM::FeatureMP];
				3423	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3424
				3425	if (Rn == 15) {
				3426	switch (Inst.getOpcode()) {
				3427	case ARM::t2LDRi8:
				3428	Inst.setOpcode(ARM::t2LDRpci);
				3429	break;
				3430	case ARM::t2LDRBi8:
				3431	Inst.setOpcode(ARM::t2LDRBpci);
				3432	break;
				3433	case ARM::t2LDRSBi8:
				3434	Inst.setOpcode(ARM::t2LDRSBpci);
				3435	break;
				3436	case ARM::t2LDRHi8:
				3437	Inst.setOpcode(ARM::t2LDRHpci);
				3438	break;
				3439	case ARM::t2LDRSHi8:
				3440	Inst.setOpcode(ARM::t2LDRSHpci);
				3441	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3442	case ARM::t2PLDi8:
				3443	Inst.setOpcode(ARM::t2PLDpci);
				3444	break;
				3445	case ARM::t2PLIi8:
				3446	Inst.setOpcode(ARM::t2PLIpci);
				3447	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3448	default:
				3449	return MCDisassembler::Fail;
				3450	}
				3451	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3452	}
				3453
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3454	if (Rt == 15) {
				3455	switch (Inst.getOpcode()) {
				3456	case ARM::t2LDRSHi8:
				3457	return MCDisassembler::Fail;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3458	case ARM::t2LDRHi8:
				3459	if (!add)
				3460	Inst.setOpcode(ARM::t2PLDWi8);
				3461	break;
				3462	case ARM::t2LDRSBi8:
				3463	Inst.setOpcode(ARM::t2PLIi8);
				3464	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3465	default:
				3466	break;
				3467	}
				3468	}
				3469
				3470	switch (Inst.getOpcode()) {
				3471	case ARM::t2PLDi8:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3472	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3473	case ARM::t2PLIi8:
				3474	if (!hasV7Ops)
				3475	return MCDisassembler::Fail;
				3476	break;
				3477	case ARM::t2PLDWi8:
				3478	if (!hasV7Ops \|\| !hasMP)
				3479	return MCDisassembler::Fail;
				3480	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3481	default:
				3482	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3483	return MCDisassembler::Fail;
				3484	}
				3485
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3486	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3487	return MCDisassembler::Fail;
				3488	return S;
				3489	}
				3490
				3491	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				3492	uint64_t Address, const void* Decoder) {
				3493	DecodeStatus S = MCDisassembler::Success;
				3494
				3495	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3496	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3497	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3498	imm \|= (Rn << 13);
				3499
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3500	const FeatureBitset &featureBits =
				3501	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3502
				3503	bool hasMP = featureBits[ARM::FeatureMP];
				3504	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3505
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3506	if (Rn == 15) {
				3507	switch (Inst.getOpcode()) {
				3508	case ARM::t2LDRi12:
				3509	Inst.setOpcode(ARM::t2LDRpci);
				3510	break;
				3511	case ARM::t2LDRHi12:
				3512	Inst.setOpcode(ARM::t2LDRHpci);
				3513	break;
				3514	case ARM::t2LDRSHi12:
				3515	Inst.setOpcode(ARM::t2LDRSHpci);
				3516	break;
				3517	case ARM::t2LDRBi12:
				3518	Inst.setOpcode(ARM::t2LDRBpci);
				3519	break;
				3520	case ARM::t2LDRSBi12:
				3521	Inst.setOpcode(ARM::t2LDRSBpci);
				3522	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3523	case ARM::t2PLDi12:
				3524	Inst.setOpcode(ARM::t2PLDpci);
				3525	break;
				3526	case ARM::t2PLIi12:
				3527	Inst.setOpcode(ARM::t2PLIpci);
				3528	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3529	default:
				3530	return MCDisassembler::Fail;
				3531	}
				3532	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3533	}
				3534
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3535	if (Rt == 15) {
				3536	switch (Inst.getOpcode()) {
				3537	case ARM::t2LDRSHi12:
				3538	return MCDisassembler::Fail;
				3539	case ARM::t2LDRHi12:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3540	Inst.setOpcode(ARM::t2PLDWi12);
				3541	break;
				3542	case ARM::t2LDRSBi12:
				3543	Inst.setOpcode(ARM::t2PLIi12);
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3544	break;
				3545	default:
				3546	break;
				3547	}
				3548	}
				3549
				3550	switch (Inst.getOpcode()) {
				3551	case ARM::t2PLDi12:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3552	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3553	case ARM::t2PLIi12:
				3554	if (!hasV7Ops)
				3555	return MCDisassembler::Fail;
				3556	break;
				3557	case ARM::t2PLDWi12:
				3558	if (!hasV7Ops \|\| !hasMP)
				3559	return MCDisassembler::Fail;
				3560	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3561	default:
				3562	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3563	return MCDisassembler::Fail;
				3564	}
				3565
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3566	if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
				3567	return MCDisassembler::Fail;
				3568	return S;
				3569	}
				3570
				3571	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				3572	uint64_t Address, const void* Decoder) {
				3573	DecodeStatus S = MCDisassembler::Success;
				3574
				3575	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3576	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3577	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3578	imm \|= (Rn << 9);
				3579
				3580	if (Rn == 15) {
				3581	switch (Inst.getOpcode()) {
				3582	case ARM::t2LDRT:
				3583	Inst.setOpcode(ARM::t2LDRpci);
				3584	break;
				3585	case ARM::t2LDRBT:
				3586	Inst.setOpcode(ARM::t2LDRBpci);
				3587	break;
				3588	case ARM::t2LDRHT:
				3589	Inst.setOpcode(ARM::t2LDRHpci);
				3590	break;
				3591	case ARM::t2LDRSBT:
				3592	Inst.setOpcode(ARM::t2LDRSBpci);
				3593	break;
				3594	case ARM::t2LDRSHT:
				3595	Inst.setOpcode(ARM::t2LDRSHpci);
				3596	break;
				3597	default:
				3598	return MCDisassembler::Fail;
				3599	}
				3600	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3601	}
				3602
				3603	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3604	return MCDisassembler::Fail;
				3605	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3606	return MCDisassembler::Fail;
				3607	return S;
				3608	}
				3609
				3610	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				3611	uint64_t Address, const void* Decoder) {
				3612	DecodeStatus S = MCDisassembler::Success;
				3613
				3614	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3615	unsigned U = fieldFromInstruction(Insn, 23, 1);
				3616	int imm = fieldFromInstruction(Insn, 0, 12);
				3617
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3618	const FeatureBitset &featureBits =
				3619	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3620
				3621	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3622
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3623	if (Rt == 15) {
				3624	switch (Inst.getOpcode()) {
				3625	case ARM::t2LDRBpci:
				3626	case ARM::t2LDRHpci:
				3627	Inst.setOpcode(ARM::t2PLDpci);
				3628	break;
				3629	case ARM::t2LDRSBpci:
				3630	Inst.setOpcode(ARM::t2PLIpci);
				3631	break;
				3632	case ARM::t2LDRSHpci:
				3633	return MCDisassembler::Fail;
				3634	default:
				3635	break;
				3636	}
				3637	}
				3638
				3639	switch(Inst.getOpcode()) {
				3640	case ARM::t2PLDpci:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3641	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3642	case ARM::t2PLIpci:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3643	if (!hasV7Ops)
				3644	return MCDisassembler::Fail;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3645	break;
				3646	default:
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3647	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3648	return MCDisassembler::Fail;
				3649	}
				3650
				3651	if (!U) {
				3652	// Special case for #-0.
				3653	if (imm == 0)
				3654	imm = INT32_MIN;
				3655	else
				3656	imm = -imm;
				3657	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3658	Inst.addOperand(MCOperand::createImm(imm));
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3659
				3660	return S;
				3661	}
				3662
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3663	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3664	uint64_t Address, const void *Decoder) {
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3665	if (Val == 0)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3666	Inst.addOperand(MCOperand::createImm(INT32_MIN));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3667	else {
				3668	int imm = Val & 0xFF;
				3669
				3670	if (!(Val & 0x100)) imm *= -1;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3671	Inst.addOperand(MCOperand::createImm(imm * 4));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3672	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3673
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3674	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3675	}
				3676
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3677	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3678	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3679	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3680
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3681	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3682	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3683
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3684	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3685	return MCDisassembler::Fail;
				3686	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3687	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3688
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3689	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3690	}
				3691
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3692	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3693	uint64_t Address, const void *Decoder) {
				3694	DecodeStatus S = MCDisassembler::Success;
				3695
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3696	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3697	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3698
				3699	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3700	return MCDisassembler::Fail;
				3701
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3702	Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3703
				3704	return S;
				3705	}
				3706
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3707	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3708	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3709	int imm = Val & 0xFF;
Owen Anderson	fe82365	2011-09-16 21:08:33 +0000	[diff] [blame]	3710	if (Val == 0)
				3711	imm = INT32_MIN;
				3712	else if (!(Val & 0x100))
				3713	imm *= -1;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3714	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3715
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3716	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3717	}
				3718
				3719
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3720	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3721	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3722	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3723
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3724	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3725	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3726
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3727	// Thumb stores cannot use PC as dest register.
				3728	switch (Inst.getOpcode()) {
				3729	case ARM::t2STRT:
				3730	case ARM::t2STRBT:
				3731	case ARM::t2STRHT:
				3732	case ARM::t2STRi8:
				3733	case ARM::t2STRHi8:
				3734	case ARM::t2STRBi8:
				3735	if (Rn == 15)
				3736	return MCDisassembler::Fail;
				3737	break;
				3738	default:
				3739	break;
				3740	}
				3741
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3742	// Some instructions always use an additive offset.
				3743	switch (Inst.getOpcode()) {
				3744	case ARM::t2LDRT:
				3745	case ARM::t2LDRBT:
				3746	case ARM::t2LDRHT:
				3747	case ARM::t2LDRSBT:
				3748	case ARM::t2LDRSHT:
Owen Anderson	ddfcec9	2011-09-19 18:07:10 +0000	[diff] [blame]	3749	case ARM::t2STRT:
				3750	case ARM::t2STRBT:
				3751	case ARM::t2STRHT:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3752	imm \|= 0x100;
				3753	break;
				3754	default:
				3755	break;
				3756	}
				3757
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3758	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3759	return MCDisassembler::Fail;
				3760	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3761	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3762
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3763	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3764	}
				3765
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3766	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3767	uint64_t Address, const void *Decoder) {
				3768	DecodeStatus S = MCDisassembler::Success;
				3769
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3770	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3771	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3772	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3773	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3774	addr \|= Rn << 9;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3775	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3776
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3777	if (Rn == 15) {
				3778	switch (Inst.getOpcode()) {
				3779	case ARM::t2LDR_PRE:
				3780	case ARM::t2LDR_POST:
				3781	Inst.setOpcode(ARM::t2LDRpci);
				3782	break;
				3783	case ARM::t2LDRB_PRE:
				3784	case ARM::t2LDRB_POST:
				3785	Inst.setOpcode(ARM::t2LDRBpci);
				3786	break;
				3787	case ARM::t2LDRH_PRE:
				3788	case ARM::t2LDRH_POST:
				3789	Inst.setOpcode(ARM::t2LDRHpci);
				3790	break;
				3791	case ARM::t2LDRSB_PRE:
				3792	case ARM::t2LDRSB_POST:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3793	if (Rt == 15)
				3794	Inst.setOpcode(ARM::t2PLIpci);
				3795	else
				3796	Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3797	break;
				3798	case ARM::t2LDRSH_PRE:
				3799	case ARM::t2LDRSH_POST:
				3800	Inst.setOpcode(ARM::t2LDRSHpci);
				3801	break;
				3802	default:
				3803	return MCDisassembler::Fail;
				3804	}
				3805	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3806	}
				3807
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3808	if (!load) {
				3809	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3810	return MCDisassembler::Fail;
				3811	}
				3812
Joe Abbey	f686be4	2013-03-26 13:58:53 +0000	[diff] [blame]	3813	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3814	return MCDisassembler::Fail;
				3815
				3816	if (load) {
				3817	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3818	return MCDisassembler::Fail;
				3819	}
				3820
				3821	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3822	return MCDisassembler::Fail;
				3823
				3824	return S;
				3825	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3826
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3827	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3828	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3829	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3830
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3831	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3832	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3833
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3834	// Thumb stores cannot use PC as dest register.
				3835	switch (Inst.getOpcode()) {
				3836	case ARM::t2STRi12:
				3837	case ARM::t2STRBi12:
				3838	case ARM::t2STRHi12:
				3839	if (Rn == 15)
				3840	return MCDisassembler::Fail;
				3841	default:
				3842	break;
				3843	}
				3844
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3845	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3846	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3847	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3848
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3849	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3850	}
				3851
				3852
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3853	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3854	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3855	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3856
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3857	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3858	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3859	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3860
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3861	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3862	}
				3863
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3864	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3865	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3866	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3867
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3868	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3869	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3870	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3871
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3872	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3873	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3874	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3875	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3876	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3877	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3878	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3879
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3880	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3881	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3882	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3883	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3884	}
				3885
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3886	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3887	}
				3888
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3889	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3890	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3891	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3892	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3893
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3894	Inst.addOperand(MCOperand::createImm(imod));
				3895	Inst.addOperand(MCOperand::createImm(flags));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3896
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3897	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3898	}
				3899
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3900	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3901	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3902	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3903	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3904	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3905
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	3906	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3907	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3908	Inst.addOperand(MCOperand::createImm(add));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3909
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3910	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3911	}
				3912
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3913	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3914	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3915	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3916	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3917	// the encoded instruction. So here change to I1 and I2 values via:
				3918	// I1 = NOT(J1 EOR S);
				3919	// I2 = NOT(J2 EOR S);
				3920	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3921	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3922	unsigned S = (Val >> 23) & 1;
				3923	unsigned J1 = (Val >> 22) & 1;
				3924	unsigned J2 = (Val >> 21) & 1;
				3925	unsigned I1 = !(J1 ^ S);
				3926	unsigned I2 = !(J2 ^ S);
				3927	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3928	int imm32 = SignExtend32<25>(tmp << 1);
				3929
Jim Grosbach	79ebc51	2011-10-20 17:28:20 +0000	[diff] [blame]	3930	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3931	(Address & ~2u) + imm32 + 4,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3932	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3933	Inst.addOperand(MCOperand::createImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3934	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3935	}
				3936
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3937	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3938	uint64_t Address, const void *Decoder) {
				3939	if (Val == 0xA \|\| Val == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3940	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3941
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3942	const FeatureBitset &featureBits =
				3943	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3944
				3945	if (featureBits[ARM::HasV8Ops] && !(Val == 14 \|\| Val == 15))
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	3946	return MCDisassembler::Fail;
				3947
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3948	Inst.addOperand(MCOperand::createImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3949	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3950	}
				3951
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3952	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3953	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3954	uint64_t Address, const void *Decoder) {
				3955	DecodeStatus S = MCDisassembler::Success;
				3956
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3957	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3958	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3959
				3960	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3961	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3962	return MCDisassembler::Fail;
				3963	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3964	return MCDisassembler::Fail;
				3965	return S;
				3966	}
				3967
				3968	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3969	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3970	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3971	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3972
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3973	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3974	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3975	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3976	switch (opc) {
				3977	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3978	return MCDisassembler::Fail;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3979	case 0xf3bf8f4:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3980	Inst.setOpcode(ARM::t2DSB);
				3981	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3982	case 0xf3bf8f5:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3983	Inst.setOpcode(ARM::t2DMB);
				3984	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3985	case 0xf3bf8f6:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3986	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	cd5612d	2011-09-07 17:55:19 +0000	[diff] [blame]	3987	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3988	}
				3989
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3990	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3991	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3992	}
				3993
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3994	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3995	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3996	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3997	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3998	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3999
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4000	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				4001	return MCDisassembler::Fail;
				4002	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4003	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4004
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4005	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4006	}
				4007
				4008	// Decode a shifted immediate operand. These basically consist
				4009	// of an 8-bit value, and a 4-bit directive that specifies either
				4010	// a splat operation or a rotation.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4011	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4012	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4013	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4014	if (ctrl == 0) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4015	unsigned byte = fieldFromInstruction(Val, 8, 2);
				4016	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4017	switch (byte) {
				4018	case 0:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4019	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4020	break;
				4021	case 1:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4022	Inst.addOperand(MCOperand::createImm((imm << 16) \| imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4023	break;
				4024	case 2:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4025	Inst.addOperand(MCOperand::createImm((imm << 24) \| (imm << 8)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4026	break;
				4027	case 3:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4028	Inst.addOperand(MCOperand::createImm((imm << 24) \| (imm << 16) \|
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4029	(imm << 8) \| imm));
				4030	break;
				4031	}
				4032	} else {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4033	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				4034	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4035	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4036	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4037	}
				4038
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4039	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4040	}
				4041
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4042	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4043	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4044	uint64_t Address, const void *Decoder){
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	4045	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	4046	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4047	Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4048	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4049	}
				4050
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4051	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	4052	uint64_t Address, const void *Decoder){
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4053	// Val is passed in as S:J1:J2:imm10:imm11
				4054	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				4055	// the encoded instruction. So here change to I1 and I2 values via:
				4056	// I1 = NOT(J1 EOR S);
				4057	// I2 = NOT(J2 EOR S);
				4058	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	4059	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4060	unsigned S = (Val >> 23) & 1;
				4061	unsigned J1 = (Val >> 22) & 1;
				4062	unsigned J2 = (Val >> 21) & 1;
				4063	unsigned I1 = !(J1 ^ S);
				4064	unsigned I2 = !(J2 ^ S);
				4065	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				4066	int imm32 = SignExtend32<25>(tmp << 1);
				4067
				4068	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	4069	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4070	Inst.addOperand(MCOperand::createImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4071	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4072	}
				4073
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4074	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4075	uint64_t Address, const void *Decoder) {
Jiangning Liu	288e1af	2012-08-02 08:21:27 +0000	[diff] [blame]	4076	if (Val & ~0xf)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4077	return MCDisassembler::Fail;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4078
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4079	Inst.addOperand(MCOperand::createImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4080	return MCDisassembler::Success;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4081	}
				4082
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	4083	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
				4084	uint64_t Address, const void *Decoder) {
				4085	if (Val & ~0xf)
				4086	return MCDisassembler::Fail;
				4087
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4088	Inst.addOperand(MCOperand::createImm(Val));
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	4089	return MCDisassembler::Success;
				4090	}
				4091
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4092	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4093	uint64_t Address, const void *Decoder) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4094	DecodeStatus S = MCDisassembler::Success;
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	4095	const FeatureBitset &FeatureBits =
				4096	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				4097
				4098	if (FeatureBits[ARM::FeatureMClass]) {
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4099	unsigned ValLow = Val & 0xff;
				4100
				4101	// Validate the SYSm value first.
				4102	switch (ValLow) {
				4103	case 0: // apsr
				4104	case 1: // iapsr
				4105	case 2: // eapsr
				4106	case 3: // xpsr
				4107	case 5: // ipsr
				4108	case 6: // epsr
				4109	case 7: // iepsr
				4110	case 8: // msp
				4111	case 9: // psp
				4112	case 16: // primask
				4113	case 20: // control
				4114	break;
				4115	case 17: // basepri
				4116	case 18: // basepri_max
				4117	case 19: // faultmask
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	4118	if (!(FeatureBits[ARM::HasV7Ops]))
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4119	// Values basepri, basepri_max and faultmask are only valid for v7m.
				4120	return MCDisassembler::Fail;
				4121	break;
Bradley Smith	f277c8a	2016-01-25 11:25:36 +0000	[diff] [blame]	4122	case 0x8a: // msplim_ns
				4123	case 0x8b: // psplim_ns
				4124	case 0x91: // basepri_ns
				4125	case 0x92: // basepri_max_ns
				4126	case 0x93: // faultmask_ns
				4127	if (!(FeatureBits[ARM::HasV8MMainlineOps]))
				4128	return MCDisassembler::Fail;
				4129	// fall through
				4130	case 10: // msplim
				4131	case 11: // psplim
				4132	case 0x88: // msp_ns
				4133	case 0x89: // psp_ns
				4134	case 0x90: // primask_ns
				4135	case 0x94: // control_ns
				4136	case 0x98: // sp_ns
				4137	if (!(FeatureBits[ARM::Feature8MSecExt]))
				4138	return MCDisassembler::Fail;
				4139	break;
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4140	default:
				4141	return MCDisassembler::Fail;
				4142	}
				4143
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4144	if (Inst.getOpcode() == ARM::t2MSR_M) {
				4145	unsigned Mask = fieldFromInstruction(Val, 10, 2);
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	4146	if (!(FeatureBits[ARM::HasV7Ops])) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4147	// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
				4148	// unpredictable.
				4149	if (Mask != 2)
				4150	S = MCDisassembler::SoftFail;
				4151	}
				4152	else {
				4153	// The ARMv7-M architecture stores an additional 2-bit mask value in
				4154	// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
				4155	// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
				4156	// the NZCVQ bits should be moved by the instruction. Bit mask{0}
				4157	// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
				4158	// only if the processor includes the DSP extension.
				4159	if (Mask == 0 \|\| (Mask != 2 && ValLow > 3) \|\|
Artyom Skrobov	cf29644	2015-09-24 17:31:16 +0000	[diff] [blame]	4160	(!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4161	S = MCDisassembler::SoftFail;
				4162	}
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4163	}
				4164	} else {
				4165	// A/R class
				4166	if (Val == 0)
				4167	return MCDisassembler::Fail;
				4168	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4169	Inst.addOperand(MCOperand::createImm(Val));
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4170	return S;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4171	}
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4172
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4173	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
				4174	uint64_t Address, const void *Decoder) {
				4175
				4176	unsigned R = fieldFromInstruction(Val, 5, 1);
				4177	unsigned SysM = fieldFromInstruction(Val, 0, 5);
				4178
				4179	// The table of encodings for these banked registers comes from B9.2.3 of the
				4180	// ARM ARM. There are patterns, but nothing regular enough to make this logic
				4181	// neater. So by fiat, these values are UNPREDICTABLE:
				4182	if (!R) {
				4183	if (SysM == 0x7 \|\| SysM == 0xf \|\| SysM == 0x18 \|\| SysM == 0x19 \|\|
				4184	SysM == 0x1a \|\| SysM == 0x1b)
				4185	return MCDisassembler::SoftFail;
				4186	} else {
				4187	if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
				4188	SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
				4189	return MCDisassembler::SoftFail;
				4190	}
				4191
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4192	Inst.addOperand(MCOperand::createImm(Val));
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4193	return MCDisassembler::Success;
				4194	}
				4195
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4196	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4197	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4198	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4199
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4200	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4201	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4202	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4203
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4204	if (Rn == 0xF)
				4205	S = MCDisassembler::SoftFail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4206
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4207	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4208	return MCDisassembler::Fail;
				4209	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4210	return MCDisassembler::Fail;
				4211	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4212	return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4213
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4214	return S;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4215	}
				4216
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4217	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4218	uint64_t Address, const void *Decoder){
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4219	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4220
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4221	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4222	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				4223	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4224	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4225
Tim Northover	27ff504	2013-04-19 15:44:32 +0000	[diff] [blame]	4226	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4227	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4228
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4229	if (Rn == 0xF \|\| Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1)
				4230	S = MCDisassembler::SoftFail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4231
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4232	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4233	return MCDisassembler::Fail;
				4234	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4235	return MCDisassembler::Fail;
				4236	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4237	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4238
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4239	return S;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4240	}
				4241
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4242	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4243	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4244	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4245
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4246	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4247	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4248	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4249	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4250	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4251	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4252
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4253	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4254
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4255	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4256	return MCDisassembler::Fail;
				4257	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4258	return MCDisassembler::Fail;
				4259	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4260	return MCDisassembler::Fail;
				4261	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4262	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4263
				4264	return S;
				4265	}
				4266
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4267	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4268	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4269	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4270
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4271	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4272	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4273	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4274	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4275	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4276	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4277	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4278
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4279	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				4280	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4281
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4282	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4283	return MCDisassembler::Fail;
				4284	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4285	return MCDisassembler::Fail;
				4286	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4287	return MCDisassembler::Fail;
				4288	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4289	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4290
				4291	return S;
				4292	}
				4293
				4294
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4295	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4296	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4297	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4298
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4299	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4300	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4301	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4302	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4303	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4304	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4305
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4306	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4307
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4308	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4309	return MCDisassembler::Fail;
				4310	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4311	return MCDisassembler::Fail;
				4312	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4313	return MCDisassembler::Fail;
				4314	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4315	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4316
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4317	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4318	}
				4319
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4320	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4321	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4322	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4323
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4324	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4325	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4326	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4327	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4328	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4329	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4330
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4331	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4332
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4333	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4334	return MCDisassembler::Fail;
				4335	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4336	return MCDisassembler::Fail;
				4337	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4338	return MCDisassembler::Fail;
				4339	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4340	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4341
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4342	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4343	}
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4344
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4345	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4346	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4347	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4348
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4349	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4350	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4351	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4352	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4353	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4354
				4355	unsigned align = 0;
				4356	unsigned index = 0;
				4357	switch (size) {
				4358	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4359	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4360	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4361	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4362	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4363	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4364	break;
				4365	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4366	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4367	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4368	index = fieldFromInstruction(Insn, 6, 2);
				4369	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4370	align = 2;
				4371	break;
				4372	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4373	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4374	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4375	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4376
				4377	switch (fieldFromInstruction(Insn, 4, 2)) {
				4378	case 0 :
				4379	align = 0; break;
				4380	case 3:
				4381	align = 4; break;
				4382	default:
				4383	return MCDisassembler::Fail;
				4384	}
				4385	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4386	}
				4387
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4388	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4389	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4390	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4391	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4392	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4393	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4394	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4395	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4396	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4397	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4398	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4399	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4400	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4401	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4402	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4403	}
				4404
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4405	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4406	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4407	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4408
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4409	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4410	}
				4411
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4412	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4413	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4414	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4415
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4416	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4417	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4418	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4419	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4420	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4421
				4422	unsigned align = 0;
				4423	unsigned index = 0;
				4424	switch (size) {
				4425	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4426	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4427	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4428	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4429	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4430	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4431	break;
				4432	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4433	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4434	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4435	index = fieldFromInstruction(Insn, 6, 2);
				4436	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4437	align = 2;
				4438	break;
				4439	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4440	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4441	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4442	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4443
				4444	switch (fieldFromInstruction(Insn, 4, 2)) {
				4445	case 0:
				4446	align = 0; break;
				4447	case 3:
				4448	align = 4; break;
				4449	default:
				4450	return MCDisassembler::Fail;
				4451	}
				4452	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4453	}
				4454
				4455	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4456	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4457	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4458	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4459	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4460	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4461	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4462	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4463	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4464	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4465	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4466	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4467	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4468	}
				4469
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4470	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4471	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4472	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4473
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4474	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4475	}
				4476
				4477
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4478	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4479	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4480	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4481
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4482	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4483	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4484	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4485	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4486	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4487
				4488	unsigned align = 0;
				4489	unsigned index = 0;
				4490	unsigned inc = 1;
				4491	switch (size) {
				4492	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4493	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4494	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4495	index = fieldFromInstruction(Insn, 5, 3);
				4496	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4497	align = 2;
				4498	break;
				4499	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4500	index = fieldFromInstruction(Insn, 6, 2);
				4501	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4502	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4503	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4504	inc = 2;
				4505	break;
				4506	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4507	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4508	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4509	index = fieldFromInstruction(Insn, 7, 1);
				4510	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4511	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4512	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4513	inc = 2;
				4514	break;
				4515	}
				4516
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4517	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4518	return MCDisassembler::Fail;
				4519	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4520	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4521	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4522	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4523	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4524	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4525	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4526	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4527	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4528	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4529	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4530	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4531	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4532	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4533	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4534	}
				4535
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4536	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4537	return MCDisassembler::Fail;
				4538	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4539	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4540	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4541
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4542	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4543	}
				4544
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4545	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4546	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4547	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4548
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4549	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4550	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4551	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4552	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4553	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4554
				4555	unsigned align = 0;
				4556	unsigned index = 0;
				4557	unsigned inc = 1;
				4558	switch (size) {
				4559	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4560	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4561	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4562	index = fieldFromInstruction(Insn, 5, 3);
				4563	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4564	align = 2;
				4565	break;
				4566	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4567	index = fieldFromInstruction(Insn, 6, 2);
				4568	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4569	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4570	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4571	inc = 2;
				4572	break;
				4573	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4574	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4575	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4576	index = fieldFromInstruction(Insn, 7, 1);
				4577	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4578	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4579	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4580	inc = 2;
				4581	break;
				4582	}
				4583
				4584	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4585	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4586	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4587	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4588	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4589	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4590	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4591	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4592	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4593	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4594	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4595	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4596	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4597	}
				4598
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4599	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4600	return MCDisassembler::Fail;
				4601	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4602	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4603	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4604
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4605	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4606	}
				4607
				4608
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4609	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4610	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4611	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4612
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4613	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4614	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4615	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4616	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4617	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4618
				4619	unsigned align = 0;
				4620	unsigned index = 0;
				4621	unsigned inc = 1;
				4622	switch (size) {
				4623	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4624	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4625	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4626	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4627	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4628	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4629	break;
				4630	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4631	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4632	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4633	index = fieldFromInstruction(Insn, 6, 2);
				4634	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4635	inc = 2;
				4636	break;
				4637	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4638	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4639	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4640	index = fieldFromInstruction(Insn, 7, 1);
				4641	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4642	inc = 2;
				4643	break;
				4644	}
				4645
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4646	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4647	return MCDisassembler::Fail;
				4648	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4649	return MCDisassembler::Fail;
				4650	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4651	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4652
				4653	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4654	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4655	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4656	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4657	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4658	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4659	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4660	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4661	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4662	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4663	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4664	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4665	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4666	}
				4667
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4668	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4669	return MCDisassembler::Fail;
				4670	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4671	return MCDisassembler::Fail;
				4672	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4673	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4674	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4675
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4676	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4677	}
				4678
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4679	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4680	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4681	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4682
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4683	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4684	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4685	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4686	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4687	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4688
				4689	unsigned align = 0;
				4690	unsigned index = 0;
				4691	unsigned inc = 1;
				4692	switch (size) {
				4693	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4694	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4695	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4696	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4697	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4698	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4699	break;
				4700	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4701	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4702	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4703	index = fieldFromInstruction(Insn, 6, 2);
				4704	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4705	inc = 2;
				4706	break;
				4707	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4708	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4709	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4710	index = fieldFromInstruction(Insn, 7, 1);
				4711	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4712	inc = 2;
				4713	break;
				4714	}
				4715
				4716	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4717	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4718	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4719	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4720	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4721	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4722	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4723	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4724	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4725	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4726	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4727	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4728	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4729	}
				4730
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4731	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4732	return MCDisassembler::Fail;
				4733	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4734	return MCDisassembler::Fail;
				4735	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4736	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4737	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4738
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4739	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4740	}
				4741
				4742
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4743	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4744	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4745	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4746
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4747	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4748	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4749	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4750	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4751	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4752
				4753	unsigned align = 0;
				4754	unsigned index = 0;
				4755	unsigned inc = 1;
				4756	switch (size) {
				4757	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4758	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4759	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4760	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4761	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4762	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4763	break;
				4764	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4765	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4766	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4767	index = fieldFromInstruction(Insn, 6, 2);
				4768	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4769	inc = 2;
				4770	break;
				4771	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4772	switch (fieldFromInstruction(Insn, 4, 2)) {
				4773	case 0:
				4774	align = 0; break;
				4775	case 3:
				4776	return MCDisassembler::Fail;
				4777	default:
				4778	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4779	}
				4780
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4781	index = fieldFromInstruction(Insn, 7, 1);
				4782	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4783	inc = 2;
				4784	break;
				4785	}
				4786
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4787	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4788	return MCDisassembler::Fail;
				4789	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4790	return MCDisassembler::Fail;
				4791	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4792	return MCDisassembler::Fail;
				4793	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4794	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4795
				4796	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4797	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4798	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4799	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4800	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4801	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4802	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4803	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4804	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4805	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4806	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4807	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4808	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4809	}
				4810
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4811	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4812	return MCDisassembler::Fail;
				4813	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4814	return MCDisassembler::Fail;
				4815	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4816	return MCDisassembler::Fail;
				4817	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4818	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4819	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4820
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4821	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4822	}
				4823
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4824	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4825	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4826	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4827
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4828	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4829	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4830	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4831	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4832	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4833
				4834	unsigned align = 0;
				4835	unsigned index = 0;
				4836	unsigned inc = 1;
				4837	switch (size) {
				4838	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4839	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4840	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4841	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4842	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4843	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4844	break;
				4845	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4846	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4847	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4848	index = fieldFromInstruction(Insn, 6, 2);
				4849	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4850	inc = 2;
				4851	break;
				4852	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4853	switch (fieldFromInstruction(Insn, 4, 2)) {
				4854	case 0:
				4855	align = 0; break;
				4856	case 3:
				4857	return MCDisassembler::Fail;
				4858	default:
				4859	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4860	}
				4861
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4862	index = fieldFromInstruction(Insn, 7, 1);
				4863	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4864	inc = 2;
				4865	break;
				4866	}
				4867
				4868	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4869	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4870	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4871	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4872	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4873	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4874	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4875	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4876	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4877	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4878	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4879	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4880	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4881	}
				4882
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4883	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4884	return MCDisassembler::Fail;
				4885	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4886	return MCDisassembler::Fail;
				4887	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4888	return MCDisassembler::Fail;
				4889	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4890	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4891	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4892
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4893	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4894	}
				4895
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4896	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4897	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4898	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4899	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4900	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4901	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4902	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4903	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4904
				4905	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4906	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4907
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4908	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4909	return MCDisassembler::Fail;
				4910	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4911	return MCDisassembler::Fail;
				4912	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4913	return MCDisassembler::Fail;
				4914	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4915	return MCDisassembler::Fail;
				4916	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4917	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4918
				4919	return S;
				4920	}
				4921
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4922	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4923	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4924	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4925	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4926	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4927	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4928	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4929	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4930
				4931	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4932	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4933
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4934	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4935	return MCDisassembler::Fail;
				4936	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4937	return MCDisassembler::Fail;
				4938	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4939	return MCDisassembler::Fail;
				4940	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4941	return MCDisassembler::Fail;
				4942	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4943	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4944
				4945	return S;
				4946	}
Owen Anderson	eb1367b	2011-08-22 23:44:04 +0000	[diff] [blame]	4947
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4948	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4949	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4950	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4951	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4952	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4953
				4954	if (pred == 0xF) {
				4955	pred = 0xE;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4956	S = MCDisassembler::SoftFail;
Owen Anderson	5230041	2011-08-24 17:21:43 +0000	[diff] [blame]	4957	}
				4958
Amaury de la Vieuville	2f0ac8d	2013-06-24 09:11:45 +0000	[diff] [blame]	4959	if (mask == 0x0)
				4960	return MCDisassembler::Fail;
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4961
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4962	Inst.addOperand(MCOperand::createImm(pred));
				4963	Inst.addOperand(MCOperand::createImm(mask));
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4964	return S;
				4965	}
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4966
				4967	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4968	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4969	uint64_t Address, const void *Decoder) {
				4970	DecodeStatus S = MCDisassembler::Success;
				4971
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4972	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4973	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4974	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4975	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4976	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4977	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4978	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4979	bool writeback = (W == 1) \| (P == 0);
				4980
				4981	addr \|= (U << 8) \| (Rn << 9);
				4982
				4983	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4984	Check(S, MCDisassembler::SoftFail);
				4985	if (Rt == Rt2)
				4986	Check(S, MCDisassembler::SoftFail);
				4987
				4988	// Rt
				4989	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4990	return MCDisassembler::Fail;
				4991	// Rt2
				4992	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4993	return MCDisassembler::Fail;
				4994	// Writeback operand
				4995	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4996	return MCDisassembler::Fail;
				4997	// addr
				4998	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4999	return MCDisassembler::Fail;
				5000
				5001	return S;
				5002	}
				5003
				5004	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5005	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	5006	uint64_t Address, const void *Decoder) {
				5007	DecodeStatus S = MCDisassembler::Success;
				5008
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5009	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				5010	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				5011	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				5012	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				5013	unsigned W = fieldFromInstruction(Insn, 21, 1);
				5014	unsigned U = fieldFromInstruction(Insn, 23, 1);
				5015	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	5016	bool writeback = (W == 1) \| (P == 0);
				5017
				5018	addr \|= (U << 8) \| (Rn << 9);
				5019
				5020	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				5021	Check(S, MCDisassembler::SoftFail);
				5022
				5023	// Writeback operand
				5024	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				5025	return MCDisassembler::Fail;
				5026	// Rt
				5027	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				5028	return MCDisassembler::Fail;
				5029	// Rt2
				5030	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				5031	return MCDisassembler::Fail;
				5032	// addr
				5033	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				5034	return MCDisassembler::Fail;
				5035
				5036	return S;
				5037	}
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5038
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5039	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5040	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5041	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				5042	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5043	if (sign1 != sign2) return MCDisassembler::Fail;
				5044
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5045	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				5046	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				5047	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5048	Val \|= sign1 << 12;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5049	Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5050
				5051	return MCDisassembler::Success;
				5052	}
				5053
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5054	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	5055	uint64_t Address,
				5056	const void *Decoder) {
				5057	DecodeStatus S = MCDisassembler::Success;
				5058
				5059	// Shift of "asr #32" is not allowed in Thumb2 mode.
Bradley Smith	3131e85	2015-01-19 16:37:17 +0000	[diff] [blame]	5060	if (Val == 0x20) S = MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5061	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	5062	return S;
				5063	}
				5064
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5065	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5066	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5067	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				5068	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				5069	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				5070	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5071
				5072	if (pred == 0xF)
				5073	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				5074
				5075	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	ca45af9	2012-04-18 14:18:57 +0000	[diff] [blame]	5076
				5077	if (Rt == Rn \|\| Rn == Rt2)
				5078	S = MCDisassembler::SoftFail;
				5079
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5080	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5081	return MCDisassembler::Fail;
				5082	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5083	return MCDisassembler::Fail;
				5084	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5085	return MCDisassembler::Fail;
				5086	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				5087	return MCDisassembler::Fail;
				5088
				5089	return S;
				5090	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5091
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5092	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5093	uint64_t Address, const void *Decoder) {
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5094	const FeatureBitset &featureBits =
				5095	((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
				5096	bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
				5097
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5098	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5099	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5100	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5101	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5102	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				5103	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5104	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5105
				5106	DecodeStatus S = MCDisassembler::Success;
				5107
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5108	// If the top 3 bits of imm are clear, this is a VMOV (immediate)
				5109	if (!(imm & 0x38)) {
				5110	if (cmode == 0xF) {
				5111	if (op == 1) return MCDisassembler::Fail;
				5112	Inst.setOpcode(ARM::VMOVv2f32);
				5113	}
				5114	if (hasFullFP16) {
				5115	if (cmode == 0xE) {
				5116	if (op == 1) {
				5117	Inst.setOpcode(ARM::VMOVv1i64);
				5118	} else {
				5119	Inst.setOpcode(ARM::VMOVv8i8);
				5120	}
				5121	}
				5122	if (cmode == 0xD) {
				5123	if (op == 1) {
				5124	Inst.setOpcode(ARM::VMVNv2i32);
				5125	} else {
				5126	Inst.setOpcode(ARM::VMOVv2i32);
				5127	}
				5128	}
				5129	if (cmode == 0xC) {
				5130	if (op == 1) {
				5131	Inst.setOpcode(ARM::VMVNv2i32);
				5132	} else {
				5133	Inst.setOpcode(ARM::VMOVv2i32);
				5134	}
				5135	}
				5136	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5137	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5138	}
				5139
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5140	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5141
				5142	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				5143	return MCDisassembler::Fail;
				5144	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				5145	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5146	Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5147
				5148	return S;
				5149	}
				5150
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5151	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5152	uint64_t Address, const void *Decoder) {
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5153	const FeatureBitset &featureBits =
				5154	((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
				5155	bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
				5156
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5157	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5158	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5159	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5160	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5161	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				5162	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5163	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5164
				5165	DecodeStatus S = MCDisassembler::Success;
				5166
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5167	// If the top 3 bits of imm are clear, this is a VMOV (immediate)
				5168	if (!(imm & 0x38)) {
				5169	if (cmode == 0xF) {
				5170	if (op == 1) return MCDisassembler::Fail;
				5171	Inst.setOpcode(ARM::VMOVv4f32);
				5172	}
				5173	if (hasFullFP16) {
				5174	if (cmode == 0xE) {
				5175	if (op == 1) {
				5176	Inst.setOpcode(ARM::VMOVv2i64);
				5177	} else {
				5178	Inst.setOpcode(ARM::VMOVv16i8);
				5179	}
				5180	}
				5181	if (cmode == 0xD) {
				5182	if (op == 1) {
				5183	Inst.setOpcode(ARM::VMVNv4i32);
				5184	} else {
				5185	Inst.setOpcode(ARM::VMOVv4i32);
				5186	}
				5187	}
				5188	if (cmode == 0xC) {
				5189	if (op == 1) {
				5190	Inst.setOpcode(ARM::VMVNv4i32);
				5191	} else {
				5192	Inst.setOpcode(ARM::VMOVv4i32);
				5193	}
				5194	}
				5195	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5196	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5197	}
				5198
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5199	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5200
				5201	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				5202	return MCDisassembler::Fail;
				5203	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				5204	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5205	Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5206
				5207	return S;
				5208	}
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5209
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5210	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5211	uint64_t Address, const void *Decoder) {
				5212	DecodeStatus S = MCDisassembler::Success;
				5213
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5214	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				5215	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5216	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				5217	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				5218	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	5219
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5220	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5221	S = MCDisassembler::SoftFail;
				5222
				5223	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5224	return MCDisassembler::Fail;
				5225	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5226	return MCDisassembler::Fail;
				5227	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				5228	return MCDisassembler::Fail;
				5229	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				5230	return MCDisassembler::Fail;
				5231	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				5232	return MCDisassembler::Fail;
				5233
				5234	return S;
				5235	}
				5236
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5237	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				5238	uint64_t Address, const void *Decoder) {
				5239
				5240	DecodeStatus S = MCDisassembler::Success;
				5241
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5242	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				5243	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				5244	unsigned cop = fieldFromInstruction(Val, 8, 4);
				5245	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5246	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5247
				5248	if ((cop & ~0x1) == 0xa)
				5249	return MCDisassembler::Fail;
				5250
				5251	if (Rt == Rt2)
				5252	S = MCDisassembler::SoftFail;
				5253
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5254	Inst.addOperand(MCOperand::createImm(cop));
				5255	Inst.addOperand(MCOperand::createImm(opc1));
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5256	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5257	return MCDisassembler::Fail;
				5258	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5259	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5260	Inst.addOperand(MCOperand::createImm(CRm));
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5261
				5262	return S;
				5263	}
				5264