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gerrit-public.fairphone.software / toolchain / llvm-project / d97c100dc456b7e1222ab2e0ddf233a09bbf627c / . / llvm / test / CodeGen / Generic / MachineBranchProb.ll
blob: ae3c8da21471f5b0cc0333094f2402e33a371757 [file] [log] [blame]
Manman Rencf104462012-08-24 18:14:27 +0000[diff] [blame]1; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
2
Weiming Zhaodf8b0d62015-10-29 22:34:59 +0000[diff] [blame]3; ARM & AArch64 run an extra SimplifyCFG which disrupts this test.
Colin LeMahieu68d155b2015-10-17 01:58:51 +0000[diff] [blame]4; Hexagon crashes (PR23377)
Weiming Zhaodf8b0d62015-10-29 22:34:59 +0000[diff] [blame]5; XFAIL: arm,aarch64,hexagon
Tim Northover3ef452e2014-05-30 10:56:12 +0000[diff] [blame]6
Manman Rencf104462012-08-24 18:14:27 +0000[diff] [blame]7; Make sure we have the correct weight attached to each successor.
8define i32 @test2(i32 %x) nounwind uwtable readnone ssp {
Hans Wennborg4b828d32015-04-30 00:57:37 +0000[diff] [blame]9; CHECK-LABEL: Machine code for function test2:
Manman Rencf104462012-08-24 18:14:27 +0000[diff] [blame]10entry:
11 %conv = sext i32 %x to i64
12 switch i64 %conv, label %return [
13 i64 0, label %sw.bb
14 i64 1, label %sw.bb
15 i64 4, label %sw.bb
16 i64 5, label %sw.bb1
17 ], !prof !0
18; CHECK: BB#0: derived from LLVM BB %entry
Cong Houd97c1002015-12-01 05:29:22 +0000[diff] [blame^]19; CHECK: Successors according to CFG: BB#2({{[0-9a-fx/= ]+}}75.29%) BB#4({{[0-9a-fx/= ]+}}24.71%)
Manman Rencf104462012-08-24 18:14:27 +0000[diff] [blame]20; CHECK: BB#4: derived from LLVM BB %entry
Cong Houd97c1002015-12-01 05:29:22 +0000[diff] [blame^]21; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}47.62%) BB#5({{[0-9a-fx/= ]+}}52.38%)
Manman Rencf104462012-08-24 18:14:27 +0000[diff] [blame]22; CHECK: BB#5: derived from LLVM BB %entry
Cong Houd97c1002015-12-01 05:29:22 +0000[diff] [blame^]23; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}36.36%) BB#3({{[0-9a-fx/= ]+}}63.64%)
Manman Rencf104462012-08-24 18:14:27 +0000[diff] [blame]24
25sw.bb:
26 br label %return
27
28sw.bb1:
29 br label %return
30
31return:
32 %retval.0 = phi i32 [ 5, %sw.bb1 ], [ 1, %sw.bb ], [ 0, %entry ]
33 ret i32 %retval.0
34}
35
Duncan P. N. Exon Smithbe7ea192014-12-15 19:07:53 +0000[diff] [blame]36!0 = !{!"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64}
Hans Wennborg4b828d32015-04-30 00:57:37 +0000[diff] [blame]37
38
39declare void @g(i32)
40define void @left_leaning_weight_balanced_tree(i32 %x) {
41entry:
42 switch i32 %x, label %return [
43 i32 0, label %bb0
44 i32 10, label %bb1
45 i32 20, label %bb2
46 i32 30, label %bb3
47 i32 40, label %bb4
48 i32 50, label %bb5
49 ], !prof !1
50bb0: tail call void @g(i32 0) br label %return
51bb1: tail call void @g(i32 1) br label %return
52bb2: tail call void @g(i32 2) br label %return
53bb3: tail call void @g(i32 3) br label %return
54bb4: tail call void @g(i32 4) br label %return
55bb5: tail call void @g(i32 5) br label %return
56return: ret void
57
58; Check that we set branch weights on the pivot cmp instruction correctly.
59; Cases {0,10,20,30} go on the left with weight 13; cases {40,50} go on the
60; right with weight 20.
61;
62; CHECK-LABEL: Machine code for function left_leaning_weight_balanced_tree:
63; CHECK: BB#0: derived from LLVM BB %entry
64; CHECK-NOT: Successors
Cong Houd97c1002015-12-01 05:29:22 +0000[diff] [blame^]65; CHECK: Successors according to CFG: BB#8({{[0-9a-fx/= ]+}}39.71%) BB#9({{[0-9a-fx/= ]+}}60.29%)
Hans Wennborg4b828d32015-04-30 00:57:37 +0000[diff] [blame]66}
67
68!1 = !{!"branch_weights",
69 ; Default:
70 i32 1,
71 ; Case 0, 10, 20:
72 i32 10, i32 1, i32 1,
73 ; Case 30, 40, 50:
74 i32 1, i32 10, i32 10}