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gerrit-public.fairphone.software / toolchain / llvm-project / 191ba00b83bf4d79209145f78c1c08b0f7ca41e0 / . / llvm / lib / Target / X86 / Disassembler / X86DisassemblerDecoderCommon.h
blob: 86a90ee49d36d14c1a23e859c194f5f3cfaeadfa [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1/*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===*
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]2 *
3 * The LLVM Compiler Infrastructure
4 *
5 * This file is distributed under the University of Illinois Open Source
6 * License. See LICENSE.TXT for details.
7 *
8 *===----------------------------------------------------------------------===*
9 *
10 * This file is part of the X86 Disassembler.
11 * It contains common definitions used by both the disassembler and the table
12 * generator.
13 * Documentation for the disassembler can be found in X86Disassembler.h.
14 *
15 *===----------------------------------------------------------------------===*/
16
17/*
18 * This header file provides those definitions that need to be shared between
19 * the decoder and the table generator in a C-friendly manner.
20 */
21
22#ifndef X86DISASSEMBLERDECODERCOMMON_H
23#define X86DISASSEMBLERDECODERCOMMON_H
24
Michael J. Spencer447762d2010-11-29 18:16:10 +0000[diff] [blame]25#include "llvm/Support/DataTypes.h"
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]26
27#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
28#define CONTEXTS_SYM x86DisassemblerContexts
29#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
30#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
31#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
32#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
Joerg Sonnenbergerfc4789d2011-04-04 16:58:13 +0000[diff] [blame]33#define THREEBYTEA6_SYM x86DisassemblerThreeByteA6Opcodes
34#define THREEBYTEA7_SYM x86DisassemblerThreeByteA7Opcodes
Craig Topper9e3e38a2013-10-03 05:17:48 +0000[diff] [blame]35#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
36#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
37#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]38
39#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
40#define CONTEXTS_STR "x86DisassemblerContexts"
41#define ONEBYTE_STR "x86DisassemblerOneByteOpcodes"
42#define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes"
43#define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes"
44#define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes"
Joerg Sonnenbergerfc4789d2011-04-04 16:58:13 +0000[diff] [blame]45#define THREEBYTEA6_STR "x86DisassemblerThreeByteA6Opcodes"
46#define THREEBYTEA7_STR "x86DisassemblerThreeByteA7Opcodes"
Craig Topper9e3e38a2013-10-03 05:17:48 +0000[diff] [blame]47#define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes"
48#define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes"
49#define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes"
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]50
51/*
52 * Attributes of an instruction that must be known before the opcode can be
53 * processed correctly. Most of these indicate the presence of particular
54 * prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
55 */
56#define ATTRIBUTE_BITS \
57 ENUM_ENTRY(ATTR_NONE, 0x00) \
58 ENUM_ENTRY(ATTR_64BIT, 0x01) \
59 ENUM_ENTRY(ATTR_XS, 0x02) \
60 ENUM_ENTRY(ATTR_XD, 0x04) \
61 ENUM_ENTRY(ATTR_REXW, 0x08) \
Sean Callananc3fd5232011-03-15 01:23:15 +0000[diff] [blame]62 ENUM_ENTRY(ATTR_OPSIZE, 0x10) \
Craig Topper6491c802012-02-27 01:54:29 +0000[diff] [blame]63 ENUM_ENTRY(ATTR_ADSIZE, 0x20) \
64 ENUM_ENTRY(ATTR_VEX, 0x40) \
65 ENUM_ENTRY(ATTR_VEXL, 0x80)
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]66
67#define ENUM_ENTRY(n, v) n = v,
68enum attributeBits {
69 ATTRIBUTE_BITS
70 ATTR_max
71};
72#undef ENUM_ENTRY
73
74/*
75 * Combinations of the above attributes that are relevant to instruction
76 * decode. Although other combinations are possible, they can be reduced to
77 * these without affecting the ultimately decoded instruction.
78 */
79
80/* Class name Rank Rationale for rank assignment */
81#define INSTRUCTION_CONTEXTS \
82 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
83 ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \
84 "64-bit mode but no more") \
85 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
86 "operands change width") \
Craig Topper6491c802012-02-27 01:54:29 +0000[diff] [blame]87 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
88 "operands change width") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]89 ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \
90 "but not the operands") \
91 ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \
92 "but not the operands") \
Craig Topper88cb33e2011-10-01 19:54:56 +0000[diff] [blame]93 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
94 "operands change width") \
Craig Toppera6978522011-10-11 04:34:23 +0000[diff] [blame]95 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
96 "operands change width") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]97 ENUM_ENTRY(IC_64BIT_REXW, 4, "requires a REX.W prefix, so operands "\
98 "change width; overrides IC_OPSIZE") \
99 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \
Craig Topper6491c802012-02-27 01:54:29 +0000[diff] [blame]100 ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]101 ENUM_ENTRY(IC_64BIT_XD, 5, "XD instructions are SSE; REX.W is " \
102 "secondary") \
103 ENUM_ENTRY(IC_64BIT_XS, 5, "Just as meaningful as IC_64BIT_XD") \
Craig Topper88cb33e2011-10-01 19:54:56 +0000[diff] [blame]104 ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \
Craig Toppera6978522011-10-11 04:34:23 +0000[diff] [blame]105 ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]106 ENUM_ENTRY(IC_64BIT_REXW_XS, 6, "OPSIZE could mean a different " \
107 "opcode") \
108 ENUM_ENTRY(IC_64BIT_REXW_XD, 6, "Just as meaningful as " \
109 "IC_64BIT_REXW_XS") \
110 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 7, "The Dynamic Duo! Prefer over all " \
111 "else because this changes most " \
Sean Callananc3fd5232011-03-15 01:23:15 +0000[diff] [blame]112 "operands' meaning") \
113 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
114 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
115 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
116 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
117 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
118 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
119 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
120 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
121 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
122 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
Craig Topperf18c8962011-10-04 06:30:42 +0000[diff] [blame]123 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
Craig Topperf01f1b52011-11-06 23:04:08 +0000[diff] [blame]124 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
Craig Toppered59dd32013-09-30 02:46:36 +0000[diff] [blame]125 ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \
126 ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \
127 ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \
128 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000[diff] [blame]129 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
130 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
131 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
132 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
133 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
134 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
135 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \
136 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
137 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \
138 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\
139 ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\
140 ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \
141 ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \
142 ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \
143 ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \
144 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \
145 ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \
146 ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\
147 ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\
148 ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \
149 ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \
150 ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \
151 ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \
152 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \
153 ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \
154 ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \
155 ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \
156 ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \
157 ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \
158 ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \
159 ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \
160 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \
161 ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \
162 ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\
163 ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\
164 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \
165 ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \
166 ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \
167 ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \
168 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \
169 ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \
170 ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\
171 ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\
172 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \
173 ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \
174 ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \
175 ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \
176 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \
177 ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \
178 ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \
179 ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \
180 ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \
181 ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \
182 ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \
183 ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \
184 ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \
185 ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \
186 ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\
187 ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\
188 ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \
189 ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \
190 ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \
191 ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \
192 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \
193 ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \
194 ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\
195 ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\
196 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \
197 ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \
198 ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \
199 ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \
200 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \
201 ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
202 ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
203 ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
204 ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \
205 ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
206 ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
207 ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
208 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \
209 ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
210 ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\
211 ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\
212 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \
213 ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
214 ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \
215 ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \
216 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, W and OpSize") \
217 ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
218 ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
219 ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
220 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \
221 ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
222 ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
223 ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
224 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and OpSize")
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]225
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]226#define ENUM_ENTRY(n, r, d) n,
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]227typedef enum {
228 INSTRUCTION_CONTEXTS
229 IC_max
230} InstructionContext;
231#undef ENUM_ENTRY
232
233/*
234 * Opcode types, which determine which decode table to use, both in the Intel
235 * manual and also for the decoder.
236 */
237typedef enum {
238 ONEBYTE = 0,
239 TWOBYTE = 1,
240 THREEBYTE_38 = 2,
Joerg Sonnenbergerfc4789d2011-04-04 16:58:13 +0000[diff] [blame]241 THREEBYTE_3A = 3,
242 THREEBYTE_A6 = 4,
Craig Topper9e3e38a2013-10-03 05:17:48 +0000[diff] [blame]243 THREEBYTE_A7 = 5,
244 XOP8_MAP = 6,
245 XOP9_MAP = 7,
246 XOPA_MAP = 8
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]247} OpcodeType;
248
249/*
250 * The following structs are used for the hierarchical decode table. After
251 * determining the instruction's class (i.e., which IC_* constant applies to
252 * it), the decoder reads the opcode. Some instructions require specific
253 * values of the ModR/M byte, so the ModR/M byte indexes into the final table.
254 *
255 * If a ModR/M byte is not required, "required" is left unset, and the values
256 * for each instructionID are identical.
257 */
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]258
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]259typedef uint16_t InstrUID;
260
261/*
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]262 * ModRMDecisionType - describes the type of ModR/M decision, allowing the
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]263 * consumer to determine the number of entries in it.
264 *
265 * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
266 * instruction is the same.
267 * MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
268 * corresponds to one instruction; otherwise, it corresponds to
269 * a different instruction.
Craig Topper963305b2012-09-13 05:45:42 +0000[diff] [blame]270 * MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
271 * divided by 8 is used to select instruction; otherwise, each
272 * value of the ModR/M byte could correspond to a different
273 * instruction.
Craig Toppera0cd9702012-02-09 08:58:07 +0000[diff] [blame]274 * MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
275 corresponds to instructions that use reg field as opcode
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]276 * MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
277 * to a different instruction.
278 */
279
280#define MODRMTYPES \
281 ENUM_ENTRY(MODRM_ONEENTRY) \
282 ENUM_ENTRY(MODRM_SPLITRM) \
Craig Topper963305b2012-09-13 05:45:42 +0000[diff] [blame]283 ENUM_ENTRY(MODRM_SPLITMISC) \
Craig Toppera0cd9702012-02-09 08:58:07 +0000[diff] [blame]284 ENUM_ENTRY(MODRM_SPLITREG) \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]285 ENUM_ENTRY(MODRM_FULL)
286
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]287#define ENUM_ENTRY(n) n,
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]288typedef enum {
289 MODRMTYPES
290 MODRM_max
291} ModRMDecisionType;
292#undef ENUM_ENTRY
293
294/*
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]295 * ModRMDecision - Specifies whether a ModR/M byte is needed and (if so) which
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]296 * instruction each possible value of the ModR/M byte corresponds to. Once
297 * this information is known, we have narrowed down to a single instruction.
298 */
299struct ModRMDecision {
300 uint8_t modrm_type;
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]301
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]302 /* The macro below must be defined wherever this file is included. */
303 INSTRUCTION_IDS
304};
305
306/*
307 * OpcodeDecision - Specifies which set of ModR/M->instruction tables to look at
308 * given a particular opcode.
309 */
310struct OpcodeDecision {
311 struct ModRMDecision modRMDecisions[256];
312};
313
314/*
315 * ContextDecision - Specifies which opcode->instruction tables to look at given
316 * a particular context (set of attributes). Since there are many possible
317 * contexts, the decoder first uses CONTEXTS_SYM to determine which context
318 * applies given a specific set of attributes. Hence there are only IC_max
319 * entries in this table, rather than 2^(ATTR_max).
320 */
321struct ContextDecision {
322 struct OpcodeDecision opcodeDecisions[IC_max];
323};
324
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]325/*
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]326 * Physical encodings of instruction operands.
327 */
328
329#define ENCODINGS \
330 ENUM_ENTRY(ENCODING_NONE, "") \
331 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
332 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
Sean Callananc3fd5232011-03-15 01:23:15 +0000[diff] [blame]333 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000[diff] [blame]334 ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]335 ENUM_ENTRY(ENCODING_CB, "1-byte code offset (possible new CS value)") \
336 ENUM_ENTRY(ENCODING_CW, "2-byte") \
337 ENUM_ENTRY(ENCODING_CD, "4-byte") \
338 ENUM_ENTRY(ENCODING_CP, "6-byte") \
339 ENUM_ENTRY(ENCODING_CO, "8-byte") \
340 ENUM_ENTRY(ENCODING_CT, "10-byte") \
341 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \
342 ENUM_ENTRY(ENCODING_IW, "2-byte") \
343 ENUM_ENTRY(ENCODING_ID, "4-byte") \
344 ENUM_ENTRY(ENCODING_IO, "8-byte") \
345 ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \
346 "the opcode byte") \
347 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
348 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
349 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
350 ENUM_ENTRY(ENCODING_I, "Position on floating-point stack added to the " \
351 "opcode byte") \
352 \
353 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
354 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
355 ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
356 "opcode byte") \
357 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
358 "in type")
359
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]360#define ENUM_ENTRY(n, d) n,
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]361 typedef enum {
362 ENCODINGS
363 ENCODING_max
364 } OperandEncoding;
365#undef ENUM_ENTRY
366
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]367/*
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]368 * Semantic interpretations of instruction operands.
369 */
370
371#define TYPES \
372 ENUM_ENTRY(TYPE_NONE, "") \
373 ENUM_ENTRY(TYPE_REL8, "1-byte immediate address") \
374 ENUM_ENTRY(TYPE_REL16, "2-byte") \
375 ENUM_ENTRY(TYPE_REL32, "4-byte") \
376 ENUM_ENTRY(TYPE_REL64, "8-byte") \
377 ENUM_ENTRY(TYPE_PTR1616, "2+2-byte segment+offset address") \
378 ENUM_ENTRY(TYPE_PTR1632, "2+4-byte") \
379 ENUM_ENTRY(TYPE_PTR1664, "2+8-byte") \
380 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
381 ENUM_ENTRY(TYPE_R16, "2-byte") \
382 ENUM_ENTRY(TYPE_R32, "4-byte") \
383 ENUM_ENTRY(TYPE_R64, "8-byte") \
384 ENUM_ENTRY(TYPE_IMM8, "1-byte immediate operand") \
385 ENUM_ENTRY(TYPE_IMM16, "2-byte") \
386 ENUM_ENTRY(TYPE_IMM32, "4-byte") \
387 ENUM_ENTRY(TYPE_IMM64, "8-byte") \
Sean Callanan1efe6612010-04-07 21:42:19 +0000[diff] [blame]388 ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \
Craig Topper7629d632012-04-03 05:20:24 +0000[diff] [blame]389 ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]390 ENUM_ENTRY(TYPE_RM8, "1-byte register or memory operand") \
391 ENUM_ENTRY(TYPE_RM16, "2-byte") \
392 ENUM_ENTRY(TYPE_RM32, "4-byte") \
393 ENUM_ENTRY(TYPE_RM64, "8-byte") \
394 ENUM_ENTRY(TYPE_M, "Memory operand") \
395 ENUM_ENTRY(TYPE_M8, "1-byte") \
396 ENUM_ENTRY(TYPE_M16, "2-byte") \
397 ENUM_ENTRY(TYPE_M32, "4-byte") \
398 ENUM_ENTRY(TYPE_M64, "8-byte") \
Sean Callanan36eab802009-12-22 21:12:55 +0000[diff] [blame]399 ENUM_ENTRY(TYPE_LEA, "Effective address") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]400 ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \
Chris Lattnerf60062f2010-09-29 02:57:56 +0000[diff] [blame]401 ENUM_ENTRY(TYPE_M256, "256-byte (AVX)") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]402 ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \
403 ENUM_ENTRY(TYPE_M1632, "2+4-byte") \
404 ENUM_ENTRY(TYPE_M1664, "2+8-byte") \
405 ENUM_ENTRY(TYPE_M16_32, "2+4-byte two-part memory operand (LIDT, LGDT)") \
406 ENUM_ENTRY(TYPE_M16_16, "2+2-byte (BOUND)") \
407 ENUM_ENTRY(TYPE_M32_32, "4+4-byte (BOUND)") \
408 ENUM_ENTRY(TYPE_M16_64, "2+8-byte (LIDT, LGDT)") \
409 ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \
410 "base)") \
411 ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \
412 ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \
413 ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \
414 ENUM_ENTRY(TYPE_SREG, "Byte with single bit set: 0 = ES, 1 = CS, " \
415 "2 = SS, 3 = DS, 4 = FS, 5 = GS") \
416 ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \
417 ENUM_ENTRY(TYPE_M64FP, "64-bit") \
418 ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \
419 ENUM_ENTRY(TYPE_M16INT, "2-byte memory integer operand for use in " \
420 "floating-point instructions") \
421 ENUM_ENTRY(TYPE_M32INT, "4-byte") \
422 ENUM_ENTRY(TYPE_M64INT, "8-byte") \
423 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
424 ENUM_ENTRY(TYPE_MM, "MMX register operand") \
425 ENUM_ENTRY(TYPE_MM32, "4-byte MMX register or memory operand") \
426 ENUM_ENTRY(TYPE_MM64, "8-byte") \
427 ENUM_ENTRY(TYPE_XMM, "XMM register operand") \
428 ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \
429 ENUM_ENTRY(TYPE_XMM64, "8-byte") \
430 ENUM_ENTRY(TYPE_XMM128, "16-byte") \
Sean Callananc3fd5232011-03-15 01:23:15 +0000[diff] [blame]431 ENUM_ENTRY(TYPE_XMM256, "32-byte") \
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000[diff] [blame]432 ENUM_ENTRY(TYPE_XMM512, "64-byte") \
433 ENUM_ENTRY(TYPE_VK8, "8-bit") \
434 ENUM_ENTRY(TYPE_VK16, "16-bit") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]435 ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \
436 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
437 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
Sean Callanane7e1cf92010-05-06 20:59:00 +0000[diff] [blame]438 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]439 \
440 ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \
441 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
442 ENUM_ENTRY(TYPE_IMMv, "Immediate operand of operand size") \
443 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
444 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
445 ENUM_ENTRY(TYPE_DUP1, "operand 1") \
446 ENUM_ENTRY(TYPE_DUP2, "operand 2") \
447 ENUM_ENTRY(TYPE_DUP3, "operand 3") \
448 ENUM_ENTRY(TYPE_DUP4, "operand 4") \
449 ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state")
450
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]451#define ENUM_ENTRY(n, d) n,
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]452typedef enum {
453 TYPES
454 TYPE_max
455} OperandType;
456#undef ENUM_ENTRY
457
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]458/*
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]459 * OperandSpecifier - The specification for how to extract and interpret one
460 * operand.
461 */
462struct OperandSpecifier {
Craig Topper6dedbae2012-03-04 02:16:41 +0000[diff] [blame]463 uint8_t encoding;
464 uint8_t type;
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]465};
466
467/*
468 * Indicates where the opcode modifier (if any) is to be found. Extended
469 * opcodes with AddRegFrm have the opcode modifier in the ModR/M byte.
470 */
471
472#define MODIFIER_TYPES \
473 ENUM_ENTRY(MODIFIER_NONE) \
474 ENUM_ENTRY(MODIFIER_OPCODE) \
475 ENUM_ENTRY(MODIFIER_MODRM)
476
477#define ENUM_ENTRY(n) n,
478typedef enum {
479 MODIFIER_TYPES
480 MODIFIER_max
481} ModifierType;
482#undef ENUM_ENTRY
483
484#define X86_MAX_OPERANDS 5
485
486/*
487 * The specification for how to extract and interpret a full instruction and
488 * its operands.
489 */
490struct InstructionSpecifier {
Craig Topper6dedbae2012-03-04 02:16:41 +0000[diff] [blame]491 uint8_t modifierType;
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]492 uint8_t modifierBase;
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]493
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]494 /* The macro below must be defined wherever this file is included. */
495 INSTRUCTION_SPECIFIER_FIELDS
496};
497
498/*
499 * Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
500 * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
501 * respectively.
502 */
503typedef enum {
504 MODE_16BIT,
505 MODE_32BIT,
506 MODE_64BIT
507} DisassemblerMode;
508
509#endif