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gerrit-public.fairphone.software / toolchain / llvm-project / dacddb0bab810aeb970271214a1879c98eef1b95 / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 6ce5c38dd2aa3daae7449d7fe87ea9b0774e8e11 [file] [log] [blame]
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1// Bitcasts between 512-bit vector types. Return the original type since
2// no instruction is needed for the conversion
3let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
17
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
48
49// Bitcasts between 256-bit vector types. Return the original type since
50// no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
81}
82
83//
84// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
85//
86
87let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
91}
92
93def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
97
98//===----------------------------------------------------------------------===//
99// AVX-512 - VECTOR INSERT
100//
101// -- 32x8 form --
102let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
107let mayLoad = 1 in
108def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
112}
113
114// -- 64x4 fp form --
115let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
120let mayLoad = 1 in
121def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
125}
126// -- 32x4 integer form --
127let neverHasSideEffects = 1 in {
128def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
132let mayLoad = 1 in
133def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
137
138}
139
140let neverHasSideEffects = 1 in {
141// -- 64x4 form --
142def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
146let mayLoad = 1 in
147def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
151}
152
153def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
165
166def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179
180def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
192
193def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206
207// vinsertps - insert f32 to XMM
208def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
212 EVEX_4V;
213def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
219
220//===----------------------------------------------------------------------===//
221// AVX-512 VECTOR EXTRACT
222//---
223let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
224// -- 32x4 form --
225def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
233
234// -- 64x4 form --
235def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
239let mayStore = 1 in
240def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
244}
245
246let neverHasSideEffects = 1 in {
247// -- 32x4 form --
248def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
256
257// -- 64x4 form --
258def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
262let mayStore = 1 in
263def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
267}
268
269def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
272
273def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
276
277def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
280
281def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
284
285
286def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
289
290def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
293
294def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
297
298def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
301
302// A 256-bit subvector extract from the first 512-bit vector position
303// is a subregister copy that needs no instruction.
304def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
312
313// zmm -> xmm
314def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
322
323
324// A 128-bit subvector insert to the first 512-bit vector position
325// is a subregister copy that needs no instruction.
326def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
329 sub_ymm)>;
330def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
333 sub_ymm)>;
334def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
337 sub_ymm)>;
338def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
341 sub_ymm)>;
342
343def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
351
352// vextractps - extract 32 bits from XMM
353def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
357 EVEX;
358
359def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
363 addr:$dst)]>, EVEX;
364
365//===---------------------------------------------------------------------===//
366// AVX-512 BROADCAST
367//---
368multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
373 []>, EVEX;
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
376}
377let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
379 VR128X, f32mem>,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
381}
382
383let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
385 VR128X, f64mem>,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
387}
388
389def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
393
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]394def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
398
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]399multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
409}
410
411defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
413 VEX_W;
414
415def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
417
418def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
420
421def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
424 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]425def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
426 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]427
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]428def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
429 (VPBROADCASTDrZrr GR32:$src)>;
430def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
431 (VPBROADCASTQrZrr GR64:$src)>;
432
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]433multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
434 X86MemOperand x86memop, PatFrag ld_frag,
435 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
436 RegisterClass KRC> {
437 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
438 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
439 [(set DstRC:$dst,
440 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
441 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
442 VR128X:$src),
443 !strconcat(OpcodeStr,
444 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
445 [(set DstRC:$dst,
446 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
447 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]448 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]449 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
450 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
451 [(set DstRC:$dst,
452 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
453 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
454 x86memop:$src),
455 !strconcat(OpcodeStr,
456 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
457 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
458 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]459 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]460}
461
462defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
463 loadi32, VR512, v16i32, v4i32, VK16WM>,
464 EVEX_V512, EVEX_CD8<32, CD8VT1>;
465defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
466 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
467 EVEX_CD8<64, CD8VT1>;
468
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]469def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
470 (VPBROADCASTDZrr VR128X:$src)>;
471def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
472 (VPBROADCASTQZrr VR128X:$src)>;
473
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]474def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
475 (VBROADCASTSSZrr VR128X:$src)>;
476def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
477 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]478
479def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
480 (VBROADCASTSSZrr VR128X:$src)>;
481def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
482 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]483
484// Provide fallback in case the load node that is used in the patterns above
485// is used by additional users, which prevents the pattern selection.
486def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
487 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
488def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
489 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
490
491
492let Predicates = [HasAVX512] in {
493def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
494 (EXTRACT_SUBREG
495 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
496 addr:$src)), sub_ymm)>;
497}
498//===----------------------------------------------------------------------===//
499// AVX-512 BROADCAST MASK TO VECTOR REGISTER
500//---
501
502multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
503 RegisterClass DstRC, RegisterClass KRC,
504 ValueType OpVT, ValueType SrcVT> {
505def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
506 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
507 []>, EVEX;
508}
509
510defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
511 VK16, v16i32, v16i1>, EVEX_V512;
512defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
513 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
514
515//===----------------------------------------------------------------------===//
516// AVX-512 - VPERM
517//
518// -- immediate form --
519multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
520 SDNode OpNode, PatFrag mem_frag,
521 X86MemOperand x86memop, ValueType OpVT> {
522 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
523 (ins RC:$src1, i8imm:$src2),
524 !strconcat(OpcodeStr,
525 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
526 [(set RC:$dst,
527 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
528 EVEX;
529 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
530 (ins x86memop:$src1, i8imm:$src2),
531 !strconcat(OpcodeStr,
532 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
533 [(set RC:$dst,
534 (OpVT (OpNode (mem_frag addr:$src1),
535 (i8 imm:$src2))))]>, EVEX;
536}
537
538defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
539 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
540let ExeDomain = SSEPackedDouble in
541defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
542 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
543
544// -- VPERM - register form --
545multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
546 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
547
548 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
549 (ins RC:$src1, RC:$src2),
550 !strconcat(OpcodeStr,
551 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
552 [(set RC:$dst,
553 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
554
555 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
556 (ins RC:$src1, x86memop:$src2),
557 !strconcat(OpcodeStr,
558 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
559 [(set RC:$dst,
560 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
561 EVEX_4V;
562}
563
564defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
565 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
566defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
567 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
568let ExeDomain = SSEPackedSingle in
569defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
570 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
571let ExeDomain = SSEPackedDouble in
572defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
573 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
574
575// -- VPERM2I - 3 source operands form --
576multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
577 PatFrag mem_frag, X86MemOperand x86memop,
578 ValueType OpVT> {
579let Constraints = "$src1 = $dst" in {
580 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
581 (ins RC:$src1, RC:$src2, RC:$src3),
582 !strconcat(OpcodeStr,
583 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
584 [(set RC:$dst,
585 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
586 EVEX_4V;
587
588 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
589 (ins RC:$src1, RC:$src2, x86memop:$src3),
590 !strconcat(OpcodeStr,
591 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
592 [(set RC:$dst,
593 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
594 (mem_frag addr:$src3))))]>, EVEX_4V;
595 }
596}
597defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
598 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
599defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
600 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
601defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
602 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
603defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
604 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
605
606//===----------------------------------------------------------------------===//
607// AVX-512 - BLEND using mask
608//
609multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
610 RegisterClass KRC, RegisterClass RC,
611 X86MemOperand x86memop, PatFrag mem_frag,
612 SDNode OpNode, ValueType vt> {
613 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
614 (ins KRC:$mask, RC:$src1, RC:$src2),
615 !strconcat(OpcodeStr,
616 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
617 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
618 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
619
620 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
621 (ins KRC:$mask, RC:$src1, x86memop:$src2),
622 !strconcat(OpcodeStr,
623 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
624 []>,
625 EVEX_4V, EVEX_K;
626}
627
628let ExeDomain = SSEPackedSingle in
629defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
630 memopv16f32, vselect, v16f32>,
631 EVEX_CD8<32, CD8VF>, EVEX_V512;
632let ExeDomain = SSEPackedDouble in
633defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
634 memopv8f64, vselect, v8f64>,
635 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
636
637defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
638 memopv8i64, vselect, v16i32>,
639 EVEX_CD8<32, CD8VF>, EVEX_V512;
640
641defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
642 memopv8i64, vselect, v8i64>, VEX_W,
643 EVEX_CD8<64, CD8VF>, EVEX_V512;
644
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]645let Predicates = [HasAVX512] in {
646def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
647 (v8f32 VR256X:$src2))),
648 (EXTRACT_SUBREG
649 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
650 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
651 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
652
653def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
654 (v8i32 VR256X:$src2))),
655 (EXTRACT_SUBREG
656 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
657 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
658 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
659}
660
661multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
662 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
663 SDNode OpNode, ValueType vt> {
664 def rr : AVX512BI<opc, MRMSrcReg,
665 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
666 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
667 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
668 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
669 def rm : AVX512BI<opc, MRMSrcMem,
670 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
671 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
672 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
673 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
674}
675
676defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
677 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
678defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
679 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
680
681defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
682 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
683defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
684 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
685
686def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
687 (COPY_TO_REGCLASS (VPCMPGTDZrr
688 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
689 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
690
691def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
692 (COPY_TO_REGCLASS (VPCMPEQDZrr
693 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
694 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
695
696multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
697 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
698 SDNode OpNode, ValueType vt, Operand CC, string asm,
699 string asm_alt> {
700 def rri : AVX512AIi8<opc, MRMSrcReg,
701 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
702 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
703 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
704 def rmi : AVX512AIi8<opc, MRMSrcMem,
705 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
706 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
707 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
708 // Accept explicit immediate argument form instead of comparison code.
709 let neverHasSideEffects = 1 in {
710 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
711 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
712 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
713 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
714 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
715 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
716 }
717}
718
719defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
720 X86cmpm, v16i32, AVXCC,
721 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
722 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
723 EVEX_V512, EVEX_CD8<32, CD8VF>;
724defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
725 X86cmpmu, v16i32, AVXCC,
726 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
727 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
728 EVEX_V512, EVEX_CD8<32, CD8VF>;
729
730defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
731 X86cmpm, v8i64, AVXCC,
732 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
733 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
734 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
735defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
736 X86cmpmu, v8i64, AVXCC,
737 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
738 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
739 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
740
741// avx512_cmp_packed - sse 1 & 2 compare packed instructions
742multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
743 X86MemOperand x86memop, Operand CC,
744 SDNode OpNode, ValueType vt, string asm,
745 string asm_alt, Domain d> {
746 def rri : AVX512PIi8<0xC2, MRMSrcReg,
747 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
748 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
749 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
750 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
751 [(set KRC:$dst,
752 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
753
754 // Accept explicit immediate argument form instead of comparison code.
755 let neverHasSideEffects = 1 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]756 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]757 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]758 asm_alt, [], d>;
759 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]760 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]761 asm_alt, [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]762 }
763}
764
765defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
766 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
767 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]768 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]769defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
770 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
771 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]772 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]773 EVEX_CD8<64, CD8VF>;
774
775def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
776 (COPY_TO_REGCLASS (VCMPPSZrri
777 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
778 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
779 imm:$cc), VK8)>;
780def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
781 (COPY_TO_REGCLASS (VPCMPDZrri
782 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
783 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
784 imm:$cc), VK8)>;
785def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
786 (COPY_TO_REGCLASS (VPCMPUDZrri
787 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
788 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
789 imm:$cc), VK8)>;
790
791// Mask register copy, including
792// - copy between mask registers
793// - load/store mask registers
794// - copy from GPR to mask register and vice versa
795//
796multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
797 string OpcodeStr, RegisterClass KRC,
798 ValueType vt, X86MemOperand x86memop> {
799 let neverHasSideEffects = 1 in {
800 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
801 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
802 let mayLoad = 1 in
803 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
804 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
805 [(set KRC:$dst, (vt (load addr:$src)))]>;
806 let mayStore = 1 in
807 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
808 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
809 }
810}
811
812multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
813 string OpcodeStr,
814 RegisterClass KRC, RegisterClass GRC> {
815 let neverHasSideEffects = 1 in {
816 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
817 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
818 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
819 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
820 }
821}
822
823let Predicates = [HasAVX512] in {
824 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
825 VEX, TB;
826 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
827 VEX, TB;
828}
829
830let Predicates = [HasAVX512] in {
831 // GR16 from/to 16-bit mask
832 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
833 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
834 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
835 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
836
837 // Store kreg in memory
838 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
839 (KMOVWmk addr:$dst, VK16:$src)>;
840
841 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
842 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
843}
844// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
845let Predicates = [HasAVX512] in {
846 // GR from/to 8-bit mask without native support
847 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
848 (COPY_TO_REGCLASS
849 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
850 VK8)>;
851 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
852 (EXTRACT_SUBREG
853 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
854 sub_8bit)>;
855}
856
857// Mask unary operation
858// - KNOT
859multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
860 RegisterClass KRC, SDPatternOperator OpNode> {
861 let Predicates = [HasAVX512] in
862 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
863 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
864 [(set KRC:$dst, (OpNode KRC:$src))]>;
865}
866
867multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
868 SDPatternOperator OpNode> {
869 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
870 VEX, TB;
871}
872
873defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
874
875def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
876def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
877 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
878
879// With AVX-512, 8-bit mask is promoted to 16-bit mask.
880def : Pat<(not VK8:$src),
881 (COPY_TO_REGCLASS
882 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
883
884// Mask binary operation
885// - KADD, KAND, KANDN, KOR, KXNOR, KXOR
886multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
887 RegisterClass KRC, SDPatternOperator OpNode> {
888 let Predicates = [HasAVX512] in
889 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
890 !strconcat(OpcodeStr,
891 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
892 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
893}
894
895multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
896 SDPatternOperator OpNode> {
897 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
898 VEX_4V, VEX_L, TB;
899}
900
901def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
902def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
903
904let isCommutable = 1 in {
905 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
906 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
907 let isCommutable = 0 in
908 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
909 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
910 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
911 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
912}
913
914multiclass avx512_mask_binop_int<string IntName, string InstName> {
915 let Predicates = [HasAVX512] in
916 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
917 VK16:$src1, VK16:$src2),
918 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
919}
920
921defm : avx512_mask_binop_int<"kadd", "KADD">;
922defm : avx512_mask_binop_int<"kand", "KAND">;
923defm : avx512_mask_binop_int<"kandn", "KANDN">;
924defm : avx512_mask_binop_int<"kor", "KOR">;
925defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
926defm : avx512_mask_binop_int<"kxor", "KXOR">;
927// With AVX-512, 8-bit mask is promoted to 16-bit mask.
928multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
929 let Predicates = [HasAVX512] in
930 def : Pat<(OpNode VK8:$src1, VK8:$src2),
931 (COPY_TO_REGCLASS
932 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
933 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
934}
935
936defm : avx512_binop_pat<and, KANDWrr>;
937defm : avx512_binop_pat<andn, KANDNWrr>;
938defm : avx512_binop_pat<or, KORWrr>;
939defm : avx512_binop_pat<xnor, KXNORWrr>;
940defm : avx512_binop_pat<xor, KXORWrr>;
941
942// Mask unpacking
943multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
944 RegisterClass KRC1, RegisterClass KRC2> {
945 let Predicates = [HasAVX512] in
946 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
947 !strconcat(OpcodeStr,
948 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
949}
950
951multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
952 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
953 VEX_4V, VEX_L, OpSize, TB;
954}
955
956defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
957
958multiclass avx512_mask_unpck_int<string IntName, string InstName> {
959 let Predicates = [HasAVX512] in
960 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
961 VK8:$src1, VK8:$src2),
962 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
963}
964
965defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
966// Mask bit testing
967multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
968 SDNode OpNode> {
969 let Predicates = [HasAVX512], Defs = [EFLAGS] in
970 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
971 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
972 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
973}
974
975multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
976 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
977 VEX, TB;
978}
979
980defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
981defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
982
983// Mask shift
984multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
985 SDNode OpNode> {
986 let Predicates = [HasAVX512] in
987 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
988 !strconcat(OpcodeStr,
989 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
990 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
991}
992
993multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
994 SDNode OpNode> {
995 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
996 VEX, OpSize, TA, VEX_W;
997}
998
999defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
1000defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
1001
1002// Mask setting all 0s or 1s
1003multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1004 let Predicates = [HasAVX512] in
1005 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1006 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1007 [(set KRC:$dst, (VT Val))]>;
1008}
1009
1010multiclass avx512_mask_setop_w<PatFrag Val> {
1011 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1012 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1013}
1014
1015defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1016defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1017
1018// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1019let Predicates = [HasAVX512] in {
1020 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1021 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1022}
1023def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1024 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1025
1026def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1027 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1028
1029def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1030 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1031
1032//===----------------------------------------------------------------------===//
1033// AVX-512 - Aligned and unaligned load and store
1034//
1035
1036multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1037 X86MemOperand x86memop, PatFrag ld_frag,
1038 string asm, Domain d> {
1039let neverHasSideEffects = 1 in
1040 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1041 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1042 EVEX;
1043let canFoldAsLoad = 1 in
1044 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1045 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1046 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1047let Constraints = "$src1 = $dst" in {
1048 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1049 (ins RC:$src1, KRC:$mask, RC:$src2),
1050 !strconcat(asm,
1051 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1052 EVEX, EVEX_K;
1053 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1054 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1055 !strconcat(asm,
1056 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1057 [], d>, EVEX, EVEX_K;
1058}
1059}
1060
1061defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1062 "vmovaps", SSEPackedSingle>,
1063 EVEX_V512, EVEX_CD8<32, CD8VF>;
1064defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1065 "vmovapd", SSEPackedDouble>,
1066 OpSize, EVEX_V512, VEX_W,
1067 EVEX_CD8<64, CD8VF>;
1068defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1069 "vmovups", SSEPackedSingle>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1070 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1071defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1072 "vmovupd", SSEPackedDouble>,
1073 OpSize, EVEX_V512, VEX_W,
1074 EVEX_CD8<64, CD8VF>;
1075def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1076 "vmovaps\t{$src, $dst|$dst, $src}",
1077 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1078 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1079def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1080 "vmovapd\t{$src, $dst|$dst, $src}",
1081 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1082 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1083 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1084def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1085 "vmovups\t{$src, $dst|$dst, $src}",
1086 [(store (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1087 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1088def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1089 "vmovupd\t{$src, $dst|$dst, $src}",
1090 [(store (v8f64 VR512:$src), addr:$dst)],
1091 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1092 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1093
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1094let neverHasSideEffects = 1 in {
1095 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1096 (ins VR512:$src),
1097 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1098 EVEX, EVEX_V512;
1099 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1100 (ins VR512:$src),
1101 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1102 EVEX, EVEX_V512, VEX_W;
1103let mayStore = 1 in {
1104 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1105 (ins i512mem:$dst, VR512:$src),
1106 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1107 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1108 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1109 (ins i512mem:$dst, VR512:$src),
1110 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1111 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1112}
1113let mayLoad = 1 in {
1114def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1115 (ins i512mem:$src),
1116 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1117 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1118def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1119 (ins i512mem:$src),
1120 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1121 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1122}
1123}
1124
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1125// 512-bit aligned load/store
1126def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1127def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1128
1129def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1130 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1131def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1132 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1133
1134multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1135 RegisterClass RC, RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1136 PatFrag ld_frag, X86MemOperand x86memop> {
1137let neverHasSideEffects = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1138 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1139 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1140let canFoldAsLoad = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1141 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1142 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1143 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1144let mayStore = 1 in
1145 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1146 (ins x86memop:$dst, VR512:$src),
1147 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1148let Constraints = "$src1 = $dst" in {
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1149 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1150 (ins RC:$src1, KRC:$mask, RC:$src2),
1151 !strconcat(asm,
1152 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1153 EVEX, EVEX_K;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1154 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1155 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1156 !strconcat(asm,
1157 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1158 []>, EVEX, EVEX_K;
1159}
1160}
1161
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1162defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1163 memopv16i32, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1164 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1165defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1166 memopv8i64, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1167 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1168
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1169// 512-bit unaligned load/store
1170def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1171def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1172
1173def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1174 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1175def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1176 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1177
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1178let AddedComplexity = 20 in {
1179def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1180 (v16f32 VR512:$src2))),
1181 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1182def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1183 (v8f64 VR512:$src2))),
1184 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1185def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1186 (v16i32 VR512:$src2))),
1187 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1188def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1189 (v8i64 VR512:$src2))),
1190 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1191}
1192// Move Int Doubleword to Packed Double Int
1193//
1194def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1195 "vmovd{z}\t{$src, $dst|$dst, $src}",
1196 [(set VR128X:$dst,
1197 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1198 EVEX, VEX_LIG;
1199def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1200 "vmovd{z}\t{$src, $dst|$dst, $src}",
1201 [(set VR128X:$dst,
1202 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1203 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1204def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1205 "vmovq{z}\t{$src, $dst|$dst, $src}",
1206 [(set VR128X:$dst,
1207 (v2i64 (scalar_to_vector GR64:$src)))],
1208 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1209let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1210def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1211 "vmovq{z}\t{$src, $dst|$dst, $src}",
1212 [(set FR64:$dst, (bitconvert GR64:$src))],
1213 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1214def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1215 "vmovq{z}\t{$src, $dst|$dst, $src}",
1216 [(set GR64:$dst, (bitconvert FR64:$src))],
1217 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1218}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1219def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1220 "vmovq{z}\t{$src, $dst|$dst, $src}",
1221 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1222 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1223 EVEX_CD8<64, CD8VT1>;
1224
1225// Move Int Doubleword to Single Scalar
1226//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1227let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1228def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1229 "vmovd{z}\t{$src, $dst|$dst, $src}",
1230 [(set FR32X:$dst, (bitconvert GR32:$src))],
1231 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1232
1233def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1234 "vmovd{z}\t{$src, $dst|$dst, $src}",
1235 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1236 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1237}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1238
1239// Move Packed Doubleword Int to Packed Double Int
1240//
1241def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1242 "vmovd{z}\t{$src, $dst|$dst, $src}",
1243 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1244 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1245 EVEX, VEX_LIG;
1246def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1247 (ins i32mem:$dst, VR128X:$src),
1248 "vmovd{z}\t{$src, $dst|$dst, $src}",
1249 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1250 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1251 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1252
1253// Move Packed Doubleword Int first element to Doubleword Int
1254//
1255def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1256 "vmovq{z}\t{$src, $dst|$dst, $src}",
1257 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1258 (iPTR 0)))],
1259 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1260 Requires<[HasAVX512, In64BitMode]>;
1261
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1262def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1263 (ins i64mem:$dst, VR128X:$src),
1264 "vmovq{z}\t{$src, $dst|$dst, $src}",
1265 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1266 addr:$dst)], IIC_SSE_MOVDQ>,
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1267 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1268 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1269
1270// Move Scalar Single to Double Int
1271//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1272let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1273def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1274 (ins FR32X:$src),
1275 "vmovd{z}\t{$src, $dst|$dst, $src}",
1276 [(set GR32:$dst, (bitconvert FR32X:$src))],
1277 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1278def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1279 (ins i32mem:$dst, FR32X:$src),
1280 "vmovd{z}\t{$src, $dst|$dst, $src}",
1281 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1282 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1283}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1284
1285// Move Quadword Int to Packed Quadword Int
1286//
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1287def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1288 (ins i64mem:$src),
1289 "vmovq{z}\t{$src, $dst|$dst, $src}",
1290 [(set VR128X:$dst,
1291 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1292 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1293
1294//===----------------------------------------------------------------------===//
1295// AVX-512 MOVSS, MOVSD
1296//===----------------------------------------------------------------------===//
1297
1298multiclass avx512_move_scalar <string asm, RegisterClass RC,
1299 SDNode OpNode, ValueType vt,
1300 X86MemOperand x86memop, PatFrag mem_pat> {
1301 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1302 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1303 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1304 (scalar_to_vector RC:$src2))))],
1305 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1306 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1307 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1308 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1309 EVEX, VEX_LIG;
1310 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1311 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1312 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1313 EVEX, VEX_LIG;
1314}
1315
1316let ExeDomain = SSEPackedSingle in
1317defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1318 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1319
1320let ExeDomain = SSEPackedDouble in
1321defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1322 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1323
1324
1325// For the disassembler
1326let isCodeGenOnly = 1 in {
1327 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1328 (ins VR128X:$src1, FR32X:$src2),
1329 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1330 IIC_SSE_MOV_S_RR>,
1331 XS, EVEX_4V, VEX_LIG;
1332 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1333 (ins VR128X:$src1, FR64X:$src2),
1334 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1335 IIC_SSE_MOV_S_RR>,
1336 XD, EVEX_4V, VEX_LIG, VEX_W;
1337}
1338
1339let Predicates = [HasAVX512] in {
1340 let AddedComplexity = 15 in {
1341 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1342 // MOVS{S,D} to the lower bits.
1343 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1344 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1345 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1346 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1347 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1348 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1349 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1350 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1351
1352 // Move low f32 and clear high bits.
1353 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1354 (SUBREG_TO_REG (i32 0),
1355 (VMOVSSZrr (v4f32 (V_SET0)),
1356 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1357 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1358 (SUBREG_TO_REG (i32 0),
1359 (VMOVSSZrr (v4i32 (V_SET0)),
1360 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1361 }
1362
1363 let AddedComplexity = 20 in {
1364 // MOVSSrm zeros the high parts of the register; represent this
1365 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1366 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1367 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1368 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1369 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1370 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1371 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1372
1373 // MOVSDrm zeros the high parts of the register; represent this
1374 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1375 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1376 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1377 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1378 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1379 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1380 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1381 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1382 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1383 def : Pat<(v2f64 (X86vzload addr:$src)),
1384 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1385
1386 // Represent the same patterns above but in the form they appear for
1387 // 256-bit types
1388 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1389 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1390 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1391 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1392 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1393 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1394 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1395 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1396 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1397 }
1398 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1399 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1400 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1401 FR32X:$src)), sub_xmm)>;
1402 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1403 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1404 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1405 FR64X:$src)), sub_xmm)>;
1406 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1407 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1408 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1409
1410 // Move low f64 and clear high bits.
1411 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1412 (SUBREG_TO_REG (i32 0),
1413 (VMOVSDZrr (v2f64 (V_SET0)),
1414 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1415
1416 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1417 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1418 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1419
1420 // Extract and store.
1421 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1422 addr:$dst),
1423 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1424 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1425 addr:$dst),
1426 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1427
1428 // Shuffle with VMOVSS
1429 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1430 (VMOVSSZrr (v4i32 VR128X:$src1),
1431 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1432 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1433 (VMOVSSZrr (v4f32 VR128X:$src1),
1434 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1435
1436 // 256-bit variants
1437 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1438 (SUBREG_TO_REG (i32 0),
1439 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1440 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1441 sub_xmm)>;
1442 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1443 (SUBREG_TO_REG (i32 0),
1444 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1445 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1446 sub_xmm)>;
1447
1448 // Shuffle with VMOVSD
1449 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1450 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1451 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1452 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1453 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1454 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1455 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1456 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1457
1458 // 256-bit variants
1459 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1460 (SUBREG_TO_REG (i32 0),
1461 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1462 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1463 sub_xmm)>;
1464 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1465 (SUBREG_TO_REG (i32 0),
1466 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1467 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1468 sub_xmm)>;
1469
1470 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1471 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1472 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1473 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1474 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1475 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1476 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1477 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1478}
1479
1480let AddedComplexity = 15 in
1481def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1482 (ins VR128X:$src),
1483 "vmovq{z}\t{$src, $dst|$dst, $src}",
1484 [(set VR128X:$dst, (v2i64 (X86vzmovl
1485 (v2i64 VR128X:$src))))],
1486 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1487
1488let AddedComplexity = 20 in
1489def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1490 (ins i128mem:$src),
1491 "vmovq{z}\t{$src, $dst|$dst, $src}",
1492 [(set VR128X:$dst, (v2i64 (X86vzmovl
1493 (loadv2i64 addr:$src))))],
1494 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1495 EVEX_CD8<8, CD8VT8>;
1496
1497let Predicates = [HasAVX512] in {
1498 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1499 let AddedComplexity = 20 in {
1500 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1501 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1502 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1503 (VMOV64toPQIZrr GR64:$src)>;
1504 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1505 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1506
1507 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1508 (VMOVDI2PDIZrm addr:$src)>;
1509 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1510 (VMOVDI2PDIZrm addr:$src)>;
1511 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1512 (VMOVZPQILo2PQIZrm addr:$src)>;
1513 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1514 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1515 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1516
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1517 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1518 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1519 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1520 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1521 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1522 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1523 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1524}
1525
1526def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1527 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1528
1529def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1530 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1531
1532def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1533 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1534
1535def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1536 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1537
1538//===----------------------------------------------------------------------===//
1539// AVX-512 - Integer arithmetic
1540//
1541multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1542 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1543 X86MemOperand x86memop, PatFrag scalar_mfrag,
1544 X86MemOperand x86scalar_mop, string BrdcstStr,
1545 OpndItins itins, bit IsCommutable = 0> {
1546 let isCommutable = IsCommutable in
1547 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1548 (ins RC:$src1, RC:$src2),
1549 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1550 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1551 itins.rr>, EVEX_4V;
1552 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1553 (ins RC:$src1, x86memop:$src2),
1554 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1555 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1556 itins.rm>, EVEX_4V;
1557 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1558 (ins RC:$src1, x86scalar_mop:$src2),
1559 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1560 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1561 [(set RC:$dst, (OpNode RC:$src1,
1562 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1563 itins.rm>, EVEX_4V, EVEX_B;
1564}
1565multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1566 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1567 PatFrag memop_frag, X86MemOperand x86memop,
1568 OpndItins itins,
1569 bit IsCommutable = 0> {
1570 let isCommutable = IsCommutable in
1571 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1572 (ins RC:$src1, RC:$src2),
1573 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1574 []>, EVEX_4V, VEX_W;
1575 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1576 (ins RC:$src1, x86memop:$src2),
1577 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1578 []>, EVEX_4V, VEX_W;
1579}
1580
1581defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1582 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1583 EVEX_V512, EVEX_CD8<32, CD8VF>;
1584
1585defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1586 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1587 EVEX_V512, EVEX_CD8<32, CD8VF>;
1588
1589defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1590 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1591 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1592
1593defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1594 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1595 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1596
1597defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1598 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1599 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1600
1601defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1602 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1603 EVEX_V512, EVEX_CD8<64, CD8VF>;
1604
1605defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1606 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1607 EVEX_CD8<64, CD8VF>;
1608
1609def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1610 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1611
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]1612defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1613 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1614 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1615defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1616 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1617 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1618
1619defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1620 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1621 EVEX_V512, EVEX_CD8<32, CD8VF>;
1622defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1623 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1624 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1625
1626defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1627 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1628 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1629defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1630 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1631 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1632
1633defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1634 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1635 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1636defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1637 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1638 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1639
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1640//===----------------------------------------------------------------------===//
1641// AVX-512 - Unpack Instructions
1642//===----------------------------------------------------------------------===//
1643
1644multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1645 PatFrag mem_frag, RegisterClass RC,
1646 X86MemOperand x86memop, string asm,
1647 Domain d> {
1648 def rr : AVX512PI<opc, MRMSrcReg,
1649 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1650 asm, [(set RC:$dst,
1651 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1652 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1653 def rm : AVX512PI<opc, MRMSrcMem,
1654 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1655 asm, [(set RC:$dst,
1656 (vt (OpNode RC:$src1,
1657 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1658 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1659}
1660
1661defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1662 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1663 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1664defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1665 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1666 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1667defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1668 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1669 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1670defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1671 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1672 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1673
1674multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1675 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1676 X86MemOperand x86memop> {
1677 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1678 (ins RC:$src1, RC:$src2),
1679 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1680 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1681 IIC_SSE_UNPCK>, EVEX_4V;
1682 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1683 (ins RC:$src1, x86memop:$src2),
1684 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1685 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1686 (bitconvert (memop_frag addr:$src2)))))],
1687 IIC_SSE_UNPCK>, EVEX_4V;
1688}
1689defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1690 VR512, memopv16i32, i512mem>, EVEX_V512,
1691 EVEX_CD8<32, CD8VF>;
1692defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1693 VR512, memopv8i64, i512mem>, EVEX_V512,
1694 VEX_W, EVEX_CD8<64, CD8VF>;
1695defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1696 VR512, memopv16i32, i512mem>, EVEX_V512,
1697 EVEX_CD8<32, CD8VF>;
1698defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1699 VR512, memopv8i64, i512mem>, EVEX_V512,
1700 VEX_W, EVEX_CD8<64, CD8VF>;
1701//===----------------------------------------------------------------------===//
1702// AVX-512 - PSHUFD
1703//
1704
1705multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1706 SDNode OpNode, PatFrag mem_frag,
1707 X86MemOperand x86memop, ValueType OpVT> {
1708 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1709 (ins RC:$src1, i8imm:$src2),
1710 !strconcat(OpcodeStr,
1711 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1712 [(set RC:$dst,
1713 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1714 EVEX;
1715 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1716 (ins x86memop:$src1, i8imm:$src2),
1717 !strconcat(OpcodeStr,
1718 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1719 [(set RC:$dst,
1720 (OpVT (OpNode (mem_frag addr:$src1),
1721 (i8 imm:$src2))))]>, EVEX;
1722}
1723
1724defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1725 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1726
1727let ExeDomain = SSEPackedSingle in
1728defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1729 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1730 EVEX_CD8<32, CD8VF>;
1731let ExeDomain = SSEPackedDouble in
1732defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1733 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1734 VEX_W, EVEX_CD8<32, CD8VF>;
1735
1736def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1737 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1738def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1739 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1740
1741//===----------------------------------------------------------------------===//
1742// AVX-512 Logical Instructions
1743//===----------------------------------------------------------------------===//
1744
1745defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1746 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1747 EVEX_V512, EVEX_CD8<32, CD8VF>;
1748defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1749 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1750 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1751defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1752 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1753 EVEX_V512, EVEX_CD8<32, CD8VF>;
1754defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1755 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1756 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1757defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1758 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1759 EVEX_V512, EVEX_CD8<32, CD8VF>;
1760defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1761 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1762 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1763defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1764 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1765 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1766defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1767 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1768 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1769
1770//===----------------------------------------------------------------------===//
1771// AVX-512 FP arithmetic
1772//===----------------------------------------------------------------------===//
1773
1774multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1775 SizeItins itins> {
1776 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1777 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1778 EVEX_CD8<32, CD8VT1>;
1779 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1780 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1781 EVEX_CD8<64, CD8VT1>;
1782}
1783
1784let isCommutable = 1 in {
1785defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1786defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1787defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1788defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1789}
1790let isCommutable = 0 in {
1791defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1792defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1793}
1794
1795multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1796 RegisterClass RC, ValueType vt,
1797 X86MemOperand x86memop, PatFrag mem_frag,
1798 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1799 string BrdcstStr,
1800 Domain d, OpndItins itins, bit commutable> {
1801 let isCommutable = commutable in
1802 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1803 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1804 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1805 EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1806 let mayLoad = 1 in {
1807 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1808 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1809 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1810 itins.rm, d>, EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1811 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1812 (ins RC:$src1, x86scalar_mop:$src2),
1813 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1814 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1815 [(set RC:$dst, (OpNode RC:$src1,
1816 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1817 itins.rm, d>, EVEX_4V, EVEX_B, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1818 }
1819}
1820
1821defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1822 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1823 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1824
1825defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1826 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1827 SSE_ALU_ITINS_P.d, 1>,
1828 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1829
1830defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1831 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1832 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1833defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1834 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1835 SSE_ALU_ITINS_P.d, 1>,
1836 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1837
1838defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1839 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1840 SSE_ALU_ITINS_P.s, 1>,
1841 EVEX_V512, EVEX_CD8<32, CD8VF>;
1842defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1843 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1844 SSE_ALU_ITINS_P.s, 1>,
1845 EVEX_V512, EVEX_CD8<32, CD8VF>;
1846
1847defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1848 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1849 SSE_ALU_ITINS_P.d, 1>,
1850 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1851defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1852 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1853 SSE_ALU_ITINS_P.d, 1>,
1854 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1855
1856defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1857 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1858 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1859defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1860 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1861 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1862
1863defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1864 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1865 SSE_ALU_ITINS_P.d, 0>,
1866 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1867defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1868 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1869 SSE_ALU_ITINS_P.d, 0>,
1870 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1871
1872//===----------------------------------------------------------------------===//
1873// AVX-512 VPTESTM instructions
1874//===----------------------------------------------------------------------===//
1875
1876multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1877 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1878 SDNode OpNode, ValueType vt> {
1879 def rr : AVX5128I<opc, MRMSrcReg,
1880 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1881 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1882 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1883 def rm : AVX5128I<opc, MRMSrcMem,
1884 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1885 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1886 [(set KRC:$dst, (OpNode (vt RC:$src1),
1887 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1888}
1889
1890defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1891 memopv16i32, X86testm, v16i32>, EVEX_V512,
1892 EVEX_CD8<32, CD8VF>;
1893defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1894 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1895 EVEX_CD8<64, CD8VF>;
1896
1897//===----------------------------------------------------------------------===//
1898// AVX-512 Shift instructions
1899//===----------------------------------------------------------------------===//
1900multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1901 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1902 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1903 RegisterClass KRC> {
1904 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1905 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1906 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1907 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1908 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1909 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1910 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1911 !strconcat(OpcodeStr,
1912 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1913 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1914 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1915 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1916 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1917 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1918 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1919 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1920 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1921 !strconcat(OpcodeStr,
1922 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1923 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1924}
1925
1926multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1927 RegisterClass RC, ValueType vt, ValueType SrcVT,
1928 PatFrag bc_frag, RegisterClass KRC> {
1929 // src2 is always 128-bit
1930 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1931 (ins RC:$src1, VR128X:$src2),
1932 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1933 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1934 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1935 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1936 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1937 !strconcat(OpcodeStr,
1938 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1939 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1940 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1941 (ins RC:$src1, i128mem:$src2),
1942 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1943 [(set RC:$dst, (vt (OpNode RC:$src1,
1944 (bc_frag (memopv2i64 addr:$src2)))))],
1945 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1946 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1947 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1948 !strconcat(OpcodeStr,
1949 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1950 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1951}
1952
1953defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1954 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1955 EVEX_V512, EVEX_CD8<32, CD8VF>;
1956defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1957 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1958 EVEX_CD8<32, CD8VQ>;
1959
1960defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1961 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1962 EVEX_CD8<64, CD8VF>, VEX_W;
1963defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1964 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1965 EVEX_CD8<64, CD8VQ>, VEX_W;
1966
1967defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1968 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1969 EVEX_CD8<32, CD8VF>;
1970defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1971 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1972 EVEX_CD8<32, CD8VQ>;
1973
1974defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1975 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1976 EVEX_CD8<64, CD8VF>, VEX_W;
1977defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1978 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1979 EVEX_CD8<64, CD8VQ>, VEX_W;
1980
1981defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1982 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1983 EVEX_V512, EVEX_CD8<32, CD8VF>;
1984defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1985 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1986 EVEX_CD8<32, CD8VQ>;
1987
1988defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1989 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1990 EVEX_CD8<64, CD8VF>, VEX_W;
1991defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1992 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1993 EVEX_CD8<64, CD8VQ>, VEX_W;
1994
1995//===-------------------------------------------------------------------===//
1996// Variable Bit Shifts
1997//===-------------------------------------------------------------------===//
1998multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1999 RegisterClass RC, ValueType vt,
2000 X86MemOperand x86memop, PatFrag mem_frag> {
2001 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2002 (ins RC:$src1, RC:$src2),
2003 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2004 [(set RC:$dst,
2005 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2006 EVEX_4V;
2007 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2008 (ins RC:$src1, x86memop:$src2),
2009 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2010 [(set RC:$dst,
2011 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2012 EVEX_4V;
2013}
2014
2015defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2016 i512mem, memopv16i32>, EVEX_V512,
2017 EVEX_CD8<32, CD8VF>;
2018defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2019 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2020 EVEX_CD8<64, CD8VF>;
2021defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2022 i512mem, memopv16i32>, EVEX_V512,
2023 EVEX_CD8<32, CD8VF>;
2024defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2025 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2026 EVEX_CD8<64, CD8VF>;
2027defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2028 i512mem, memopv16i32>, EVEX_V512,
2029 EVEX_CD8<32, CD8VF>;
2030defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2031 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2032 EVEX_CD8<64, CD8VF>;
2033
2034//===----------------------------------------------------------------------===//
2035// AVX-512 - MOVDDUP
2036//===----------------------------------------------------------------------===//
2037
2038multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2039 X86MemOperand x86memop, PatFrag memop_frag> {
2040def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2041 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2042 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2043def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2044 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2045 [(set RC:$dst,
2046 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2047}
2048
2049defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2050 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2051def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2052 (VMOVDDUPZrm addr:$src)>;
2053
2054def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2055 (ins VR128X:$src1, VR128X:$src2),
2056 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2057 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2058 IIC_SSE_MOV_LH>, EVEX_4V;
2059def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2060 (ins VR128X:$src1, VR128X:$src2),
2061 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2062 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2063 IIC_SSE_MOV_LH>, EVEX_4V;
2064
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2065let Predicates = [HasAVX512] in {
2066 // MOVLHPS patterns
2067 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2068 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2069 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2070 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2071
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2072 // MOVHLPS patterns
2073 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2074 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2075}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2076
2077//===----------------------------------------------------------------------===//
2078// FMA - Fused Multiply Operations
2079//
2080let Constraints = "$src1 = $dst" in {
2081multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2082 RegisterClass RC, X86MemOperand x86memop,
2083 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2084 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2085 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2086 (ins RC:$src1, RC:$src2, RC:$src3),
2087 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2088 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2089
2090 let mayLoad = 1 in
2091 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2092 (ins RC:$src1, RC:$src2, x86memop:$src3),
2093 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2094 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2095 (mem_frag addr:$src3))))]>;
2096 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2097 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2098 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2099 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2100 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2101 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2102}
2103} // Constraints = "$src1 = $dst"
2104
2105let ExeDomain = SSEPackedSingle in {
2106 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2107 memopv16f32, f32mem, loadf32, "{1to16}",
2108 X86Fmadd, v16f32>, EVEX_V512,
2109 EVEX_CD8<32, CD8VF>;
2110 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2111 memopv16f32, f32mem, loadf32, "{1to16}",
2112 X86Fmsub, v16f32>, EVEX_V512,
2113 EVEX_CD8<32, CD8VF>;
2114 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2115 memopv16f32, f32mem, loadf32, "{1to16}",
2116 X86Fmaddsub, v16f32>,
2117 EVEX_V512, EVEX_CD8<32, CD8VF>;
2118 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2119 memopv16f32, f32mem, loadf32, "{1to16}",
2120 X86Fmsubadd, v16f32>,
2121 EVEX_V512, EVEX_CD8<32, CD8VF>;
2122 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2123 memopv16f32, f32mem, loadf32, "{1to16}",
2124 X86Fnmadd, v16f32>, EVEX_V512,
2125 EVEX_CD8<32, CD8VF>;
2126 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2127 memopv16f32, f32mem, loadf32, "{1to16}",
2128 X86Fnmsub, v16f32>, EVEX_V512,
2129 EVEX_CD8<32, CD8VF>;
2130}
2131let ExeDomain = SSEPackedDouble in {
2132 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2133 memopv8f64, f64mem, loadf64, "{1to8}",
2134 X86Fmadd, v8f64>, EVEX_V512,
2135 VEX_W, EVEX_CD8<64, CD8VF>;
2136 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2137 memopv8f64, f64mem, loadf64, "{1to8}",
2138 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2139 EVEX_CD8<64, CD8VF>;
2140 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2141 memopv8f64, f64mem, loadf64, "{1to8}",
2142 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2143 EVEX_CD8<64, CD8VF>;
2144 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2145 memopv8f64, f64mem, loadf64, "{1to8}",
2146 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2147 EVEX_CD8<64, CD8VF>;
2148 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2149 memopv8f64, f64mem, loadf64, "{1to8}",
2150 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2151 EVEX_CD8<64, CD8VF>;
2152 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2153 memopv8f64, f64mem, loadf64, "{1to8}",
2154 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2155 EVEX_CD8<64, CD8VF>;
2156}
2157
2158let Constraints = "$src1 = $dst" in {
2159multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2160 RegisterClass RC, X86MemOperand x86memop,
2161 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2162 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2163 let mayLoad = 1 in
2164 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2165 (ins RC:$src1, RC:$src3, x86memop:$src2),
2166 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2167 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2168 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2169 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2170 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2171 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2172 [(set RC:$dst, (OpNode RC:$src1,
2173 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2174}
2175} // Constraints = "$src1 = $dst"
2176
2177
2178let ExeDomain = SSEPackedSingle in {
2179 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2180 memopv16f32, f32mem, loadf32, "{1to16}",
2181 X86Fmadd, v16f32>, EVEX_V512,
2182 EVEX_CD8<32, CD8VF>;
2183 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2184 memopv16f32, f32mem, loadf32, "{1to16}",
2185 X86Fmsub, v16f32>, EVEX_V512,
2186 EVEX_CD8<32, CD8VF>;
2187 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2188 memopv16f32, f32mem, loadf32, "{1to16}",
2189 X86Fmaddsub, v16f32>,
2190 EVEX_V512, EVEX_CD8<32, CD8VF>;
2191 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2192 memopv16f32, f32mem, loadf32, "{1to16}",
2193 X86Fmsubadd, v16f32>,
2194 EVEX_V512, EVEX_CD8<32, CD8VF>;
2195 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2196 memopv16f32, f32mem, loadf32, "{1to16}",
2197 X86Fnmadd, v16f32>, EVEX_V512,
2198 EVEX_CD8<32, CD8VF>;
2199 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2200 memopv16f32, f32mem, loadf32, "{1to16}",
2201 X86Fnmsub, v16f32>, EVEX_V512,
2202 EVEX_CD8<32, CD8VF>;
2203}
2204let ExeDomain = SSEPackedDouble in {
2205 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2206 memopv8f64, f64mem, loadf64, "{1to8}",
2207 X86Fmadd, v8f64>, EVEX_V512,
2208 VEX_W, EVEX_CD8<64, CD8VF>;
2209 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2210 memopv8f64, f64mem, loadf64, "{1to8}",
2211 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2212 EVEX_CD8<64, CD8VF>;
2213 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2214 memopv8f64, f64mem, loadf64, "{1to8}",
2215 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2216 EVEX_CD8<64, CD8VF>;
2217 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2218 memopv8f64, f64mem, loadf64, "{1to8}",
2219 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2220 EVEX_CD8<64, CD8VF>;
2221 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2222 memopv8f64, f64mem, loadf64, "{1to8}",
2223 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2224 EVEX_CD8<64, CD8VF>;
2225 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2226 memopv8f64, f64mem, loadf64, "{1to8}",
2227 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2228 EVEX_CD8<64, CD8VF>;
2229}
2230
2231// Scalar FMA
2232let Constraints = "$src1 = $dst" in {
2233multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2234 RegisterClass RC, ValueType OpVT,
2235 X86MemOperand x86memop, Operand memop,
2236 PatFrag mem_frag> {
2237 let isCommutable = 1 in
2238 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2239 (ins RC:$src1, RC:$src2, RC:$src3),
2240 !strconcat(OpcodeStr,
2241 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2242 [(set RC:$dst,
2243 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2244 let mayLoad = 1 in
2245 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2246 (ins RC:$src1, RC:$src2, f128mem:$src3),
2247 !strconcat(OpcodeStr,
2248 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2249 [(set RC:$dst,
2250 (OpVT (OpNode RC:$src2, RC:$src1,
2251 (mem_frag addr:$src3))))]>;
2252}
2253
2254} // Constraints = "$src1 = $dst"
2255
2256defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2257 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2258defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2259 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2260defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2261 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2262defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2263 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2264defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2265 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2266defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2267 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2268defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2269 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2270defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2271 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2272
2273//===----------------------------------------------------------------------===//
2274// AVX-512 Scalar convert from sign integer to float/double
2275//===----------------------------------------------------------------------===//
2276
2277multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2278 X86MemOperand x86memop, string asm> {
2279let neverHasSideEffects = 1 in {
2280 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2281 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2282 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2283 let mayLoad = 1 in
2284 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2285 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2286 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2287 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2288} // neverHasSideEffects = 1
2289}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2290let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2291defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2292 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2293defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2294 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2295defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2296 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2297defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2298 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2299
2300def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2301 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2302def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2303 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2304def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2305 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2306def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2307 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2308
2309def : Pat<(f32 (sint_to_fp GR32:$src)),
2310 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2311def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2312 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2313def : Pat<(f64 (sint_to_fp GR32:$src)),
2314 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2315def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2316 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2317
2318defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}{z}">,
2319 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2320defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}{z}">,
2321 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2322defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}{z}">,
2323 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2324defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}{z}">,
2325 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2326
2327def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2328 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2329def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2330 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2331def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2332 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2333def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2334 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2335
2336def : Pat<(f32 (uint_to_fp GR32:$src)),
2337 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2338def : Pat<(f32 (uint_to_fp GR64:$src)),
2339 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2340def : Pat<(f64 (uint_to_fp GR32:$src)),
2341 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2342def : Pat<(f64 (uint_to_fp GR64:$src)),
2343 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2344}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2345
2346//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2347// AVX-512 Scalar convert from float/double to integer
2348//===----------------------------------------------------------------------===//
2349multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2350 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2351 string asm> {
2352let neverHasSideEffects = 1 in {
2353 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2354 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2355 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
2356 let mayLoad = 1 in
2357 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2358 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
2359} // neverHasSideEffects = 1
2360}
2361let Predicates = [HasAVX512] in {
2362// Convert float/double to signed/unsigned int 32/64
2363defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2364 ssmem, sse_load_f32, "cvtss2si{z}">,
2365 XS, EVEX_CD8<32, CD8VT1>;
2366defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2367 ssmem, sse_load_f32, "cvtss2si{z}">,
2368 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2369defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2370 ssmem, sse_load_f32, "cvtss2usi{z}">,
2371 XS, EVEX_CD8<32, CD8VT1>;
2372defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2373 int_x86_avx512_cvtss2usi64, ssmem,
2374 sse_load_f32, "cvtss2usi{z}">, XS, VEX_W,
2375 EVEX_CD8<32, CD8VT1>;
2376defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2377 sdmem, sse_load_f64, "cvtsd2si{z}">,
2378 XD, EVEX_CD8<64, CD8VT1>;
2379defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2380 sdmem, sse_load_f64, "cvtsd2si{z}">,
2381 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2382defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2383 sdmem, sse_load_f64, "cvtsd2usi{z}">,
2384 XD, EVEX_CD8<64, CD8VT1>;
2385defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2386 int_x86_avx512_cvtsd2usi64, sdmem,
2387 sse_load_f64, "cvtsd2usi{z}">, XD, VEX_W,
2388 EVEX_CD8<64, CD8VT1>;
2389
2390defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2391 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}{z}",
2392 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2393defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2394 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}{z}",
2395 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2396defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2397 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}{z}",
2398 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2399defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2400 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}{z}",
2401 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2402
2403defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2404 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}{z}",
2405 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2406defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2407 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}{z}",
2408 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2409defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2410 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}{z}",
2411 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2412defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2413 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}{z}",
2414 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2415
2416// Convert float/double to signed/unsigned int 32/64 with truncation
2417defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2418 ssmem, sse_load_f32, "cvttss2si{z}">,
2419 XS, EVEX_CD8<32, CD8VT1>;
2420defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2421 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2422 "cvttss2si{z}">, XS, VEX_W,
2423 EVEX_CD8<32, CD8VT1>;
2424defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2425 sdmem, sse_load_f64, "cvttsd2si{z}">, XD,
2426 EVEX_CD8<64, CD8VT1>;
2427defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2428 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2429 "cvttsd2si{z}">, XD, VEX_W,
2430 EVEX_CD8<64, CD8VT1>;
2431defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2432 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2433 "cvttss2si{z}">, XS, EVEX_CD8<32, CD8VT1>;
2434defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2435 int_x86_avx512_cvttss2usi64, ssmem,
2436 sse_load_f32, "cvttss2usi{z}">, XS, VEX_W,
2437 EVEX_CD8<32, CD8VT1>;
2438defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2439 int_x86_avx512_cvttsd2usi,
2440 sdmem, sse_load_f64, "cvttsd2usi{z}">, XD,
2441 EVEX_CD8<64, CD8VT1>;
2442defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2443 int_x86_avx512_cvttsd2usi64, sdmem,
2444 sse_load_f64, "cvttsd2usi{z}">, XD, VEX_W,
2445 EVEX_CD8<64, CD8VT1>;
2446}
2447
2448multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2449 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2450 string asm> {
2451 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2452 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2453 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2454 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2455 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2456 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2457}
2458
2459defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2460 loadf32, "cvttss2si{z}">, XS,
2461 EVEX_CD8<32, CD8VT1>;
2462defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2463 loadf32, "cvttss2usi{z}">, XS,
2464 EVEX_CD8<32, CD8VT1>;
2465defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2466 loadf32, "cvttss2si{z}">, XS, VEX_W,
2467 EVEX_CD8<32, CD8VT1>;
2468defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2469 loadf32, "cvttss2usi{z}">, XS, VEX_W,
2470 EVEX_CD8<32, CD8VT1>;
2471defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2472 loadf64, "cvttsd2si{z}">, XD,
2473 EVEX_CD8<64, CD8VT1>;
2474defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2475 loadf64, "cvttsd2usi{z}">, XD,
2476 EVEX_CD8<64, CD8VT1>;
2477defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2478 loadf64, "cvttsd2si{z}">, XD, VEX_W,
2479 EVEX_CD8<64, CD8VT1>;
2480defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2481 loadf64, "cvttsd2usi{z}">, XD, VEX_W,
2482 EVEX_CD8<64, CD8VT1>;
2483//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2484// AVX-512 Convert form float to double and back
2485//===----------------------------------------------------------------------===//
2486let neverHasSideEffects = 1 in {
2487def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2488 (ins FR32X:$src1, FR32X:$src2),
2489 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2490 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2491let mayLoad = 1 in
2492def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2493 (ins FR32X:$src1, f32mem:$src2),
2494 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2495 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2496 EVEX_CD8<32, CD8VT1>;
2497
2498// Convert scalar double to scalar single
2499def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2500 (ins FR64X:$src1, FR64X:$src2),
2501 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2502 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2503let mayLoad = 1 in
2504def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2505 (ins FR64X:$src1, f64mem:$src2),
2506 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2507 []>, EVEX_4V, VEX_LIG, VEX_W,
2508 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2509}
2510
2511def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2512 Requires<[HasAVX512]>;
2513def : Pat<(fextend (loadf32 addr:$src)),
2514 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2515
2516def : Pat<(extloadf32 addr:$src),
2517 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2518 Requires<[HasAVX512, OptForSize]>;
2519
2520def : Pat<(extloadf32 addr:$src),
2521 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2522 Requires<[HasAVX512, OptForSpeed]>;
2523
2524def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2525 Requires<[HasAVX512]>;
2526
2527multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2528 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2529 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2530 Domain d> {
2531let neverHasSideEffects = 1 in {
2532 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2533 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2534 [(set DstRC:$dst,
2535 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2536 let mayLoad = 1 in
2537 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2538 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2539 [(set DstRC:$dst,
2540 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2541} // neverHasSideEffects = 1
2542}
2543
2544defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2545 memopv8f64, f512mem, v8f32, v8f64,
2546 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2547 EVEX_CD8<64, CD8VF>;
2548
2549defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2550 memopv4f64, f256mem, v8f64, v8f32,
2551 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2552def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2553 (VCVTPS2PDZrm addr:$src)>;
2554
2555//===----------------------------------------------------------------------===//
2556// AVX-512 Vector convert from sign integer to float/double
2557//===----------------------------------------------------------------------===//
2558
2559defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2560 memopv8i64, i512mem, v16f32, v16i32,
2561 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2562
2563defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2564 memopv4i64, i256mem, v8f64, v8i32,
2565 SSEPackedDouble>, EVEX_V512, XS,
2566 EVEX_CD8<32, CD8VH>;
2567
2568defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2569 memopv16f32, f512mem, v16i32, v16f32,
2570 SSEPackedSingle>, EVEX_V512, XS,
2571 EVEX_CD8<32, CD8VF>;
2572
2573defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2574 memopv8f64, f512mem, v8i32, v8f64,
2575 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2576 EVEX_CD8<64, CD8VF>;
2577
2578defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2579 memopv16f32, f512mem, v16i32, v16f32,
2580 SSEPackedSingle>, EVEX_V512,
2581 EVEX_CD8<32, CD8VF>;
2582
2583defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2584 memopv8f64, f512mem, v8i32, v8f64,
2585 SSEPackedDouble>, EVEX_V512, VEX_W,
2586 EVEX_CD8<64, CD8VF>;
2587
2588defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2589 memopv4i64, f256mem, v8f64, v8i32,
2590 SSEPackedDouble>, EVEX_V512, XS,
2591 EVEX_CD8<32, CD8VH>;
2592
2593defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2594 memopv16i32, f512mem, v16f32, v16i32,
2595 SSEPackedSingle>, EVEX_V512, XD,
2596 EVEX_CD8<32, CD8VF>;
2597
2598def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2599 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2600 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2601
2602
2603def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2604 (VCVTDQ2PSZrr VR512:$src)>;
2605def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2606 (VCVTDQ2PSZrm addr:$src)>;
2607
2608def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2609 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2610 [(set VR512:$dst,
2611 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2612 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2613def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2614 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2615 [(set VR512:$dst,
2616 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2617 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2618
2619
2620let Predicates = [HasAVX512] in {
2621 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2622 (VCVTPD2PSZrm addr:$src)>;
2623 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2624 (VCVTPS2PDZrm addr:$src)>;
2625}
2626
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]2627//===----------------------------------------------------------------------===//
2628// Half precision conversion instructions
2629//===----------------------------------------------------------------------===//
2630multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2631 X86MemOperand x86memop, Intrinsic Int> {
2632 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2633 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2634 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2635 let neverHasSideEffects = 1, mayLoad = 1 in
2636 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2637 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2638}
2639
2640multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2641 X86MemOperand x86memop, Intrinsic Int> {
2642 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2643 (ins srcRC:$src1, i32i8imm:$src2),
2644 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2645 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2646 let neverHasSideEffects = 1, mayStore = 1 in
2647 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2648 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2649 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2650}
2651
2652defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2653 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2654 EVEX_CD8<32, CD8VH>;
2655defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2656 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2657 EVEX_CD8<32, CD8VH>;
2658
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2659let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2660 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2661 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2662 EVEX_CD8<32, CD8VT1>;
2663 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2664 "ucomisd{z}">, TB, OpSize, EVEX,
2665 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2666 let Pattern = []<dag> in {
2667 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2668 "comiss{z}">, TB, EVEX, VEX_LIG,
2669 EVEX_CD8<32, CD8VT1>;
2670 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2671 "comisd{z}">, TB, OpSize, EVEX,
2672 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2673 }
2674 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2675 load, "ucomiss">, TB, EVEX, VEX_LIG,
2676 EVEX_CD8<32, CD8VT1>;
2677 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2678 load, "ucomisd">, TB, OpSize, EVEX,
2679 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2680
2681 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2682 load, "comiss">, TB, EVEX, VEX_LIG,
2683 EVEX_CD8<32, CD8VT1>;
2684 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2685 load, "comisd">, TB, OpSize, EVEX,
2686 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2687}
2688
2689/// avx512_unop_p - AVX-512 unops in packed form.
2690multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2691 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2692 !strconcat(OpcodeStr,
2693 "ps\t{$src, $dst|$dst, $src}"),
2694 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2695 EVEX, EVEX_V512;
2696 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2697 !strconcat(OpcodeStr,
2698 "ps\t{$src, $dst|$dst, $src}"),
2699 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2700 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2701 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2702 !strconcat(OpcodeStr,
2703 "pd\t{$src, $dst|$dst, $src}"),
2704 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2705 EVEX, EVEX_V512, VEX_W;
2706 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2707 !strconcat(OpcodeStr,
2708 "pd\t{$src, $dst|$dst, $src}"),
2709 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2710 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2711}
2712
2713/// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2714multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2715 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2716 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2717 !strconcat(OpcodeStr,
2718 "ps\t{$src, $dst|$dst, $src}"),
2719 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2720 EVEX, EVEX_V512;
2721 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2722 !strconcat(OpcodeStr,
2723 "ps\t{$src, $dst|$dst, $src}"),
2724 [(set VR512:$dst,
2725 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2726 EVEX_V512, EVEX_CD8<32, CD8VF>;
2727 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2728 !strconcat(OpcodeStr,
2729 "pd\t{$src, $dst|$dst, $src}"),
2730 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2731 EVEX, EVEX_V512, VEX_W;
2732 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2733 !strconcat(OpcodeStr,
2734 "pd\t{$src, $dst|$dst, $src}"),
2735 [(set VR512:$dst,
2736 (V8F64Int (memopv8f64 addr:$src)))]>,
2737 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2738}
2739
2740/// avx512_fp_unop_s - AVX-512 unops in scalar form.
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2741multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2742 let hasSideEffects = 0 in {
2743 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2744 (ins FR32X:$src1, FR32X:$src2),
2745 !strconcat(OpcodeStr,
2746 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2747 []>, EVEX_4V;
2748 let mayLoad = 1 in {
2749 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2750 (ins FR32X:$src1, f32mem:$src2),
2751 !strconcat(OpcodeStr,
2752 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2753 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2754 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2755 (ins VR128X:$src1, ssmem:$src2),
2756 !strconcat(OpcodeStr,
2757 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2758 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2759 }
2760 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2761 (ins FR64X:$src1, FR64X:$src2),
2762 !strconcat(OpcodeStr,
2763 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2764 EVEX_4V, VEX_W;
2765 let mayLoad = 1 in {
2766 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2767 (ins FR64X:$src1, f64mem:$src2),
2768 !strconcat(OpcodeStr,
2769 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2770 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2771 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2772 (ins VR128X:$src1, sdmem:$src2),
2773 !strconcat(OpcodeStr,
2774 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2775 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2776 }
2777}
2778}
2779
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2780defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2781 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2782 avx512_fp_unop_p_int<0x4C, "vrcp14",
2783 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2784
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2785defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2786 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2787 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2788 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2789
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2790def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2791 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2792 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2793 VR128X)>;
2794def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2795 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2796
2797def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2798 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2799 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2800 VR128X)>;
2801def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2802 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2803
2804let AddedComplexity = 20, Predicates = [HasERI] in {
2805defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2806 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2807 avx512_fp_unop_p_int<0xCA, "vrcp28",
2808 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2809
2810defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2811 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2812 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2813 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2814}
2815
2816let Predicates = [HasERI] in {
2817 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2818 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2819 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2820 VR128X)>;
2821 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2822 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2823
2824 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2825 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2826 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2827 VR128X)>;
2828 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2829 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2830}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2831multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2832 Intrinsic V16F32Int, Intrinsic V8F64Int,
2833 OpndItins itins_s, OpndItins itins_d> {
2834 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2835 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2836 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2837 EVEX, EVEX_V512;
2838
2839 let mayLoad = 1 in
2840 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2841 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2842 [(set VR512:$dst,
2843 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2844 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2845
2846 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2848 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2849 EVEX, EVEX_V512;
2850
2851 let mayLoad = 1 in
2852 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2853 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2854 [(set VR512:$dst, (OpNode
2855 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2856 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2857
2858 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2859 !strconcat(OpcodeStr,
2860 "ps\t{$src, $dst|$dst, $src}"),
2861 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2862 EVEX, EVEX_V512;
2863 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2864 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2865 [(set VR512:$dst,
2866 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2867 EVEX_V512, EVEX_CD8<32, CD8VF>;
2868 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2869 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2870 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2871 EVEX, EVEX_V512, VEX_W;
2872 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2873 !strconcat(OpcodeStr,
2874 "pd\t{$src, $dst|$dst, $src}"),
2875 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2876 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2877}
2878
2879multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2880 Intrinsic F32Int, Intrinsic F64Int,
2881 OpndItins itins_s, OpndItins itins_d> {
2882 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2883 (ins FR32X:$src1, FR32X:$src2),
2884 !strconcat(OpcodeStr,
2885 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2886 [], itins_s.rr>, XS, EVEX_4V;
2887 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2888 (ins VR128X:$src1, VR128X:$src2),
2889 !strconcat(OpcodeStr,
2890 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2891 [(set VR128X:$dst,
2892 (F32Int VR128X:$src1, VR128X:$src2))],
2893 itins_s.rr>, XS, EVEX_4V;
2894 let mayLoad = 1 in {
2895 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2896 (ins FR32X:$src1, f32mem:$src2),
2897 !strconcat(OpcodeStr,
2898 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2899 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2900 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2901 (ins VR128X:$src1, ssmem:$src2),
2902 !strconcat(OpcodeStr,
2903 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2904 [(set VR128X:$dst,
2905 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2906 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2907 }
2908 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2909 (ins FR64X:$src1, FR64X:$src2),
2910 !strconcat(OpcodeStr,
2911 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2912 XD, EVEX_4V, VEX_W;
2913 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2914 (ins VR128X:$src1, VR128X:$src2),
2915 !strconcat(OpcodeStr,
2916 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2917 [(set VR128X:$dst,
2918 (F64Int VR128X:$src1, VR128X:$src2))],
2919 itins_s.rr>, XD, EVEX_4V, VEX_W;
2920 let mayLoad = 1 in {
2921 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2922 (ins FR64X:$src1, f64mem:$src2),
2923 !strconcat(OpcodeStr,
2924 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2925 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2926 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2927 (ins VR128X:$src1, sdmem:$src2),
2928 !strconcat(OpcodeStr,
2929 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2930 [(set VR128X:$dst,
2931 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2932 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2933 }
2934}
2935
2936
2937defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2938 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2939 SSE_SQRTSS, SSE_SQRTSD>,
2940 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2941 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2942 SSE_SQRTPS, SSE_SQRTPD>;
2943
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2944let Predicates = [HasAVX512] in {
2945 def : Pat<(f32 (fsqrt FR32X:$src)),
2946 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2947 def : Pat<(f32 (fsqrt (load addr:$src))),
2948 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2949 Requires<[OptForSize]>;
2950 def : Pat<(f64 (fsqrt FR64X:$src)),
2951 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2952 def : Pat<(f64 (fsqrt (load addr:$src))),
2953 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2954 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2955
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2956 def : Pat<(f32 (X86frsqrt FR32X:$src)),
2957 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2958 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2959 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2960 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2961
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2962 def : Pat<(f32 (X86frcp FR32X:$src)),
2963 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2964 def : Pat<(f32 (X86frcp (load addr:$src))),
2965 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2966 Requires<[OptForSize]>;
2967
2968 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
2969 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
2970 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2971 VR128X)>;
2972 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2973 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2974
2975 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
2976 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
2977 (COPY_TO_REGCLASS VR128X:$src, FR64)),
2978 VR128X)>;
2979 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2980 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2981}
2982
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2983
2984multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2985 X86MemOperand x86memop, RegisterClass RC,
2986 PatFrag mem_frag32, PatFrag mem_frag64,
2987 Intrinsic V4F32Int, Intrinsic V2F64Int,
2988 CD8VForm VForm> {
2989let ExeDomain = SSEPackedSingle in {
2990 // Intrinsic operation, reg.
2991 // Vector intrinsic operation, reg
2992 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2993 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2994 !strconcat(OpcodeStr,
2995 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2996 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2997
2998 // Vector intrinsic operation, mem
2999 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3000 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3001 !strconcat(OpcodeStr,
3002 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3003 [(set RC:$dst,
3004 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3005 EVEX_CD8<32, VForm>;
3006} // ExeDomain = SSEPackedSingle
3007
3008let ExeDomain = SSEPackedDouble in {
3009 // Vector intrinsic operation, reg
3010 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3011 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3012 !strconcat(OpcodeStr,
3013 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3014 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3015
3016 // Vector intrinsic operation, mem
3017 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3018 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3019 !strconcat(OpcodeStr,
3020 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3021 [(set RC:$dst,
3022 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3023 EVEX_CD8<64, VForm>;
3024} // ExeDomain = SSEPackedDouble
3025}
3026
3027multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3028 string OpcodeStr,
3029 Intrinsic F32Int,
3030 Intrinsic F64Int> {
3031let ExeDomain = GenericDomain in {
3032 // Operation, reg.
3033 let hasSideEffects = 0 in
3034 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3035 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3036 !strconcat(OpcodeStr,
3037 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3038 []>;
3039
3040 // Intrinsic operation, reg.
3041 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3042 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3043 !strconcat(OpcodeStr,
3044 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3045 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3046
3047 // Intrinsic operation, mem.
3048 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3049 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3050 !strconcat(OpcodeStr,
3051 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3052 [(set VR128X:$dst, (F32Int VR128X:$src1,
3053 sse_load_f32:$src2, imm:$src3))]>,
3054 EVEX_CD8<32, CD8VT1>;
3055
3056 // Operation, reg.
3057 let hasSideEffects = 0 in
3058 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3059 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3060 !strconcat(OpcodeStr,
3061 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3062 []>, VEX_W;
3063
3064 // Intrinsic operation, reg.
3065 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3066 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3067 !strconcat(OpcodeStr,
3068 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3069 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3070 VEX_W;
3071
3072 // Intrinsic operation, mem.
3073 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3074 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3075 !strconcat(OpcodeStr,
3076 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3077 [(set VR128X:$dst,
3078 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3079 VEX_W, EVEX_CD8<64, CD8VT1>;
3080} // ExeDomain = GenericDomain
3081}
3082
3083let Predicates = [HasAVX512] in {
3084 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3085 int_x86_avx512_rndscale_ss,
3086 int_x86_avx512_rndscale_sd>, EVEX_4V;
3087
3088 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3089 memopv16f32, memopv8f64,
3090 int_x86_avx512_rndscale_ps_512,
3091 int_x86_avx512_rndscale_pd_512, CD8VF>,
3092 EVEX, EVEX_V512;
3093}
3094
3095def : Pat<(ffloor FR32X:$src),
3096 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3097def : Pat<(f64 (ffloor FR64X:$src)),
3098 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3099def : Pat<(f32 (fnearbyint FR32X:$src)),
3100 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3101def : Pat<(f64 (fnearbyint FR64X:$src)),
3102 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3103def : Pat<(f32 (fceil FR32X:$src)),
3104 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3105def : Pat<(f64 (fceil FR64X:$src)),
3106 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3107def : Pat<(f32 (frint FR32X:$src)),
3108 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3109def : Pat<(f64 (frint FR64X:$src)),
3110 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3111def : Pat<(f32 (ftrunc FR32X:$src)),
3112 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3113def : Pat<(f64 (ftrunc FR64X:$src)),
3114 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3115
3116def : Pat<(v16f32 (ffloor VR512:$src)),
3117 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3118def : Pat<(v16f32 (fnearbyint VR512:$src)),
3119 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3120def : Pat<(v16f32 (fceil VR512:$src)),
3121 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3122def : Pat<(v16f32 (frint VR512:$src)),
3123 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3124def : Pat<(v16f32 (ftrunc VR512:$src)),
3125 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3126
3127def : Pat<(v8f64 (ffloor VR512:$src)),
3128 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3129def : Pat<(v8f64 (fnearbyint VR512:$src)),
3130 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3131def : Pat<(v8f64 (fceil VR512:$src)),
3132 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3133def : Pat<(v8f64 (frint VR512:$src)),
3134 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3135def : Pat<(v8f64 (ftrunc VR512:$src)),
3136 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3137
3138//-------------------------------------------------
3139// Integer truncate and extend operations
3140//-------------------------------------------------
3141
3142multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3143 RegisterClass dstRC, RegisterClass srcRC,
3144 RegisterClass KRC, X86MemOperand x86memop> {
3145 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3146 (ins srcRC:$src),
3147 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3148 []>, EVEX;
3149
3150 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3151 (ins KRC:$mask, srcRC:$src),
3152 !strconcat(OpcodeStr,
3153 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3154 []>, EVEX, EVEX_KZ;
3155
3156 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3157 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3158 []>, EVEX;
3159}
3160defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3161 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3162defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3163 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3164defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3165 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3166defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3167 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3168defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3169 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3170defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3171 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3172defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3173 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3174defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3175 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3176defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3177 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3178defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3179 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3180defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3181 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3182defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3183 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3184defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3185 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3186defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3187 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3188defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3189 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3190
3191def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3192def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3193def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3194def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3195def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3196
3197def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3198 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3199def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3200 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3201def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3202 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3203def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3204 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3205
3206
3207multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3208 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3209 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3210
3211 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3212 (ins SrcRC:$src),
3213 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3214 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3215 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3216 (ins x86memop:$src),
3217 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3218 [(set DstRC:$dst,
3219 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3220 EVEX;
3221}
3222
3223defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3224 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3225 EVEX_CD8<8, CD8VQ>;
3226defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3227 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3228 EVEX_CD8<8, CD8VO>;
3229defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3230 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3231 EVEX_CD8<16, CD8VH>;
3232defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3233 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3234 EVEX_CD8<16, CD8VQ>;
3235defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3236 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3237 EVEX_CD8<32, CD8VH>;
3238
3239defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3240 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3241 EVEX_CD8<8, CD8VQ>;
3242defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3243 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3244 EVEX_CD8<8, CD8VO>;
3245defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3246 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3247 EVEX_CD8<16, CD8VH>;
3248defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3249 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3250 EVEX_CD8<16, CD8VQ>;
3251defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3252 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3253 EVEX_CD8<32, CD8VH>;
3254
3255//===----------------------------------------------------------------------===//
3256// GATHER - SCATTER Operations
3257
3258multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3259 RegisterClass RC, X86MemOperand memop> {
3260let mayLoad = 1,
3261 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3262 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3263 (ins RC:$src1, KRC:$mask, memop:$src2),
3264 !strconcat(OpcodeStr,
3265 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3266 []>, EVEX, EVEX_K;
3267}
3268defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3269 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3270defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3271 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3272
3273defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3274 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3275defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3276 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3277
3278defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3279 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3280defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3281 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3282
3283defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3284 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3285defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3286 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3287
3288multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3289 RegisterClass RC, X86MemOperand memop> {
3290let mayStore = 1, Constraints = "$mask = $mask_wb" in
3291 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3292 (ins memop:$dst, KRC:$mask, RC:$src2),
3293 !strconcat(OpcodeStr,
3294 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3295 []>, EVEX, EVEX_K;
3296}
3297
3298defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3299 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3300defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3301 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3302
3303defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3304 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3305defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3306 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3307
3308defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3309 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3310defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3311 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3312
3313defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3314 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3315defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3316 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3317
3318//===----------------------------------------------------------------------===//
3319// VSHUFPS - VSHUFPD Operations
3320
3321multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3322 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3323 Domain d> {
3324 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3325 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3326 !strconcat(OpcodeStr,
3327 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3328 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3329 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3330 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3331 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3332 (ins RC:$src1, RC:$src2, i8imm:$src3),
3333 !strconcat(OpcodeStr,
3334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3335 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3336 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3337 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3338}
3339
3340defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3341 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3342defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3343 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3344
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]3345def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3346 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3347def : Pat<(v16i32 (X86Shufp VR512:$src1,
3348 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3349 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3350
3351def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3352 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3353def : Pat<(v8i64 (X86Shufp VR512:$src1,
3354 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3355 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3356
3357multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3358 X86MemOperand x86memop> {
3359 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3360 (ins RC:$src1, RC:$src2, i8imm:$src3),
3361 !strconcat(OpcodeStr,
3362 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3363 []>, EVEX_4V;
3364 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3365 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3366 !strconcat(OpcodeStr,
3367 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3368 []>, EVEX_4V;
3369}
3370defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3371 EVEX_V512, EVEX_CD8<32, CD8VF>;
3372defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3373 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3374
3375def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3376 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3377def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3378 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3379def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3380 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3381def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3382 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3383
3384multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3385 X86MemOperand x86memop> {
3386 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3387 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3388 EVEX;
3389 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3390 (ins x86memop:$src),
3391 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3392 EVEX;
3393}
3394
3395defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3396 EVEX_CD8<32, CD8VF>;
3397defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3398 EVEX_CD8<64, CD8VF>;
3399
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame^]3400multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3401 RegisterClass RC, RegisterClass KRC, PatFrag memop_frag,
3402 X86MemOperand x86memop, PatFrag scalar_mfrag,
3403 X86MemOperand x86scalar_mop, string BrdcstStr,
3404 Intrinsic Int, Intrinsic maskInt, Intrinsic maskzInt> {
3405 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3406 (ins RC:$src),
3407 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3408 [(set RC:$dst, (Int RC:$src))]>, EVEX;
3409 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3410 (ins x86memop:$src),
3411 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3412 [(set RC:$dst, (Int (memop_frag addr:$src)))]>, EVEX;
3413 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3414 (ins x86scalar_mop:$src),
3415 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3416 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3417 []>, EVEX, EVEX_B;
3418 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3419 (ins KRC:$mask, RC:$src),
3420 !strconcat(OpcodeStr,
3421 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3422 [(set RC:$dst, (maskzInt KRC:$mask, RC:$src))]>, EVEX, EVEX_KZ;
3423 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3424 (ins KRC:$mask, x86memop:$src),
3425 !strconcat(OpcodeStr,
3426 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3427 [(set RC:$dst, (maskzInt KRC:$mask, (memop_frag addr:$src)))]>,
3428 EVEX, EVEX_KZ;
3429 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3430 (ins KRC:$mask, x86scalar_mop:$src),
3431 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3432 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3433 BrdcstStr, "}"),
3434 []>, EVEX, EVEX_KZ, EVEX_B;
3435
3436 let Constraints = "$src1 = $dst" in {
3437 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3438 (ins RC:$src1, KRC:$mask, RC:$src2),
3439 !strconcat(OpcodeStr,
3440 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3441 [(set RC:$dst, (maskInt RC:$src1, KRC:$mask, RC:$src2))]>, EVEX, EVEX_K;
3442 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3443 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3444 !strconcat(OpcodeStr,
3445 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3446 [(set RC:$dst, (maskInt RC:$src1, KRC:$mask, (memop_frag addr:$src2)))]>, EVEX, EVEX_K;
3447 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3448 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3449 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3450 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3451 []>, EVEX, EVEX_K, EVEX_B;
3452 }
3453}
3454
3455let Predicates = [HasCDI] in {
3456defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3457 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
3458 int_x86_avx512_conflict_d_512,
3459 int_x86_avx512_conflict_d_mask_512,
3460 int_x86_avx512_conflict_d_maskz_512>,
3461 EVEX_V512, EVEX_CD8<32, CD8VF>;
3462
3463defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3464 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3465 int_x86_avx512_conflict_q_512,
3466 int_x86_avx512_conflict_q_mask_512,
3467 int_x86_avx512_conflict_q_maskz_512>,
3468 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3469}