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gerrit-public.fairphone.software / toolchain / llvm-project / bb791b3dbdc009412c1a27b14b22091b15d3728b / . / llvm / test / CodeGen / PowerPC / testComparesigtsll.ll
blob: abf120c55dd08453f9e3e0bfe217fbb904850bf3 [file] [log] [blame]
Nemanja Ivanovice22ebea2017-09-26 20:42:47 +0000[diff] [blame]1; XFAIL: *
Nemanja Ivanovicf7bc9ce2017-09-25 14:05:46 +0000[diff] [blame]2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8
9@glob = common local_unnamed_addr global i64 0, align 8
10
11; Function Attrs: norecurse nounwind readnone
12define signext i32 @test_igtsll(i64 %a, i64 %b) {
13; CHECK-LABEL: test_igtsll:
14; CHECK: # BB#0: # %entry
15; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
16; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
17; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
18; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
19; CHECK-NEXT: xori r3, [[REG4]], 1
20; CHECK-NEXT: blr
21entry:
22 %cmp = icmp sgt i64 %a, %b
23 %conv = zext i1 %cmp to i32
24 ret i32 %conv
25}
26
27; Function Attrs: norecurse nounwind readnone
28define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
29; CHECK-LABEL: test_igtsll_sext:
30; CHECK: # BB#0: # %entry
31; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
32; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
33; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
34; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
35; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
36; CHECK-NEXT: neg r3, [[REG5]]
37; CHECK-NEXT: blr
38entry:
39 %cmp = icmp sgt i64 %a, %b
40 %sub = sext i1 %cmp to i32
41 ret i32 %sub
42}
43
44; FIXME
45; Function Attrs: norecurse nounwind readnone
46define signext i32 @test_igtsll_z(i64 %a) {
47; CHECK-LABEL: test_igtsll_z:
48; CHECK: # BB#0: # %entry
49; CHECK-NEXT: addi r4, r3, -1
50; CHECK-NEXT: nor r3, r4, r3
51; CHECK-NEXT: rldicl r3, r3, 1, 63
52; CHECK-NEXT: blr
53entry:
54 %cmp = icmp sgt i64 %a, 0
55 %conv = zext i1 %cmp to i32
56 ret i32 %conv
57}
58
59; Function Attrs: norecurse nounwind readnone
60define signext i32 @test_igtsll_sext_z(i64 %a) {
61; CHECK-LABEL: test_igtsll_sext_z:
62; CHECK: addi [[REG1:r[0-9]+]], r3, -1
63; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3
64; CHECK-NEXT: sradi r3, [[REG2]], 63
65entry:
66 %cmp = icmp sgt i64 %a, 0
67 %sub = sext i1 %cmp to i32
68 ret i32 %sub
69}
70
71; Function Attrs: norecurse nounwind
72define void @test_igtsll_store(i64 %a, i64 %b) {
73; CHECK-LABEL: test_igtsll_store:
74; CHECK: # BB#0: # %entry
75; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
76; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
77; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
78; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
79; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
80; CHECK-NOT: neg
81entry:
82 %cmp = icmp sgt i64 %a, %b
83 %conv1 = zext i1 %cmp to i64
84 store i64 %conv1, i64* @glob, align 8
85 ret void
86}
87
88; Function Attrs: norecurse nounwind
89define void @test_igtsll_sext_store(i64 %a, i64 %b) {
90; CHECK-LABEL: test_igtsll_sext_store:
91; CHECK: # BB#0: # %entry
92; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
93; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
94; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
95; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
96; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
97; CHECK: neg {{r[0-9]+}}, [[REG5]]
98entry:
99 %cmp = icmp sgt i64 %a, %b
100 %conv1 = sext i1 %cmp to i64
101 store i64 %conv1, i64* @glob, align 8
102 ret void
103}
104
105; FIXME
106; Function Attrs: norecurse nounwind
107define void @test_igtsll_z_store(i64 %a) {
108; CHECK-LABEL: test_igtsll_z_store:
109; CHECK: # BB#0: # %entry
110; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
111; CHECK-NEXT: addi r5, r3, -1
112; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
113; CHECK-NEXT: nor r3, r5, r3
114; CHECK-NEXT: rldicl r3, r3, 1, 63
115; CHECK-NEXT: std r3, 0(r4)
116; CHECK-NEXT: blr
117entry:
118 %cmp = icmp sgt i64 %a, 0
119 %conv1 = zext i1 %cmp to i64
120 store i64 %conv1, i64* @glob, align 8
121 ret void
122}
123
124; Function Attrs: norecurse nounwind
125define void @test_igtsll_sext_z_store(i64 %a) {
126; CHECK-LABEL: test_igtsll_sext_z_store:
127; CHECK: addi [[REG1:r[0-9]+]], r3, -1
128; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3
129; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63
130entry:
131 %cmp = icmp sgt i64 %a, 0
132 %conv1 = sext i1 %cmp to i64
133 store i64 %conv1, i64* @glob, align 8
134 ret void
135}