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gerrit-public.fairphone.software / toolchain / llvm-project / dd0794e51b733b5c2de52f9c1a20066cd61d8f09 / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 1be6660e2586ddc6f25dbf0d7a798d1c54c1d2bf [file] [log] [blame]
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1// Bitcasts between 512-bit vector types. Return the original type since
2// no instruction is needed for the conversion
3let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
17
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
48
49// Bitcasts between 256-bit vector types. Return the original type since
50// no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
81}
82
83//
84// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
85//
86
87let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
91}
92
93def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
97
98//===----------------------------------------------------------------------===//
99// AVX-512 - VECTOR INSERT
100//
101// -- 32x8 form --
102let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
107let mayLoad = 1 in
108def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
112}
113
114// -- 64x4 fp form --
115let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
120let mayLoad = 1 in
121def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
125}
126// -- 32x4 integer form --
127let neverHasSideEffects = 1 in {
128def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
132let mayLoad = 1 in
133def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
137
138}
139
140let neverHasSideEffects = 1 in {
141// -- 64x4 form --
142def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
146let mayLoad = 1 in
147def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
151}
152
153def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
165
166def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179
180def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
192
193def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206
207// vinsertps - insert f32 to XMM
208def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
212 EVEX_4V;
213def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
219
220//===----------------------------------------------------------------------===//
221// AVX-512 VECTOR EXTRACT
222//---
223let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
224// -- 32x4 form --
225def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
233
234// -- 64x4 form --
235def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
239let mayStore = 1 in
240def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
244}
245
246let neverHasSideEffects = 1 in {
247// -- 32x4 form --
248def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
256
257// -- 64x4 form --
258def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
262let mayStore = 1 in
263def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
267}
268
269def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
272
273def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
276
277def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
280
281def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
284
285
286def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
289
290def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
293
294def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
297
298def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
301
302// A 256-bit subvector extract from the first 512-bit vector position
303// is a subregister copy that needs no instruction.
304def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
312
313// zmm -> xmm
314def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
322
323
324// A 128-bit subvector insert to the first 512-bit vector position
325// is a subregister copy that needs no instruction.
326def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
329 sub_ymm)>;
330def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
333 sub_ymm)>;
334def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
337 sub_ymm)>;
338def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
341 sub_ymm)>;
342
343def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
351
352// vextractps - extract 32 bits from XMM
353def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
357 EVEX;
358
359def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
363 addr:$dst)]>, EVEX;
364
365//===---------------------------------------------------------------------===//
366// AVX-512 BROADCAST
367//---
368multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
373 []>, EVEX;
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
376}
377let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
379 VR128X, f32mem>,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
381}
382
383let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
385 VR128X, f64mem>,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
387}
388
389def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
393
394multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
395 RegisterClass SrcRC, RegisterClass KRC> {
396 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
398 []>, EVEX, EVEX_V512;
399 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
400 (ins KRC:$mask, SrcRC:$src),
401 !strconcat(OpcodeStr,
402 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
403 []>, EVEX, EVEX_V512, EVEX_KZ;
404}
405
406defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
407defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
408 VEX_W;
409
410def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
411 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
412
413def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
414 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
415
416def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
417 (VPBROADCASTDrZrr GR32:$src)>;
418def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
419 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame^]420def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
421 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]422
423multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
424 X86MemOperand x86memop, PatFrag ld_frag,
425 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
426 RegisterClass KRC> {
427 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
428 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
429 [(set DstRC:$dst,
430 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
431 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
432 VR128X:$src),
433 !strconcat(OpcodeStr,
434 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
435 [(set DstRC:$dst,
436 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
437 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame^]438 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]439 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
441 [(set DstRC:$dst,
442 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
443 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
444 x86memop:$src),
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
447 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
448 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame^]449 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]450}
451
452defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
453 loadi32, VR512, v16i32, v4i32, VK16WM>,
454 EVEX_V512, EVEX_CD8<32, CD8VT1>;
455defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
456 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
457 EVEX_CD8<64, CD8VT1>;
458
459def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
460 (VBROADCASTSSZrr VR128X:$src)>;
461def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
462 (VBROADCASTSDZrr VR128X:$src)>;
463
464// Provide fallback in case the load node that is used in the patterns above
465// is used by additional users, which prevents the pattern selection.
466def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
467 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
468def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
469 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
470
471
472let Predicates = [HasAVX512] in {
473def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
474 (EXTRACT_SUBREG
475 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
476 addr:$src)), sub_ymm)>;
477}
478//===----------------------------------------------------------------------===//
479// AVX-512 BROADCAST MASK TO VECTOR REGISTER
480//---
481
482multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
483 RegisterClass DstRC, RegisterClass KRC,
484 ValueType OpVT, ValueType SrcVT> {
485def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
486 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
487 []>, EVEX;
488}
489
490defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
491 VK16, v16i32, v16i1>, EVEX_V512;
492defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
493 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
494
495//===----------------------------------------------------------------------===//
496// AVX-512 - VPERM
497//
498// -- immediate form --
499multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
500 SDNode OpNode, PatFrag mem_frag,
501 X86MemOperand x86memop, ValueType OpVT> {
502 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
503 (ins RC:$src1, i8imm:$src2),
504 !strconcat(OpcodeStr,
505 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
506 [(set RC:$dst,
507 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
508 EVEX;
509 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
510 (ins x86memop:$src1, i8imm:$src2),
511 !strconcat(OpcodeStr,
512 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
513 [(set RC:$dst,
514 (OpVT (OpNode (mem_frag addr:$src1),
515 (i8 imm:$src2))))]>, EVEX;
516}
517
518defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
519 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
520let ExeDomain = SSEPackedDouble in
521defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
522 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
523
524// -- VPERM - register form --
525multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
526 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
527
528 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
529 (ins RC:$src1, RC:$src2),
530 !strconcat(OpcodeStr,
531 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
532 [(set RC:$dst,
533 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
534
535 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
536 (ins RC:$src1, x86memop:$src2),
537 !strconcat(OpcodeStr,
538 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
539 [(set RC:$dst,
540 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
541 EVEX_4V;
542}
543
544defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
545 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
546defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
547 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
548let ExeDomain = SSEPackedSingle in
549defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
550 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
551let ExeDomain = SSEPackedDouble in
552defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
553 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554
555// -- VPERM2I - 3 source operands form --
556multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
557 PatFrag mem_frag, X86MemOperand x86memop,
558 ValueType OpVT> {
559let Constraints = "$src1 = $dst" in {
560 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
561 (ins RC:$src1, RC:$src2, RC:$src3),
562 !strconcat(OpcodeStr,
563 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
564 [(set RC:$dst,
565 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
566 EVEX_4V;
567
568 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
569 (ins RC:$src1, RC:$src2, x86memop:$src3),
570 !strconcat(OpcodeStr,
571 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
572 [(set RC:$dst,
573 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
574 (mem_frag addr:$src3))))]>, EVEX_4V;
575 }
576}
577defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
578 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
579defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
580 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
581defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
582 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
583defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
584 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585
586//===----------------------------------------------------------------------===//
587// AVX-512 - BLEND using mask
588//
589multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
590 RegisterClass KRC, RegisterClass RC,
591 X86MemOperand x86memop, PatFrag mem_frag,
592 SDNode OpNode, ValueType vt> {
593 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
594 (ins KRC:$mask, RC:$src1, RC:$src2),
595 !strconcat(OpcodeStr,
596 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
597 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
598 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
599
600 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
601 (ins KRC:$mask, RC:$src1, x86memop:$src2),
602 !strconcat(OpcodeStr,
603 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
604 []>,
605 EVEX_4V, EVEX_K;
606}
607
608let ExeDomain = SSEPackedSingle in
609defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
610 memopv16f32, vselect, v16f32>,
611 EVEX_CD8<32, CD8VF>, EVEX_V512;
612let ExeDomain = SSEPackedDouble in
613defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
614 memopv8f64, vselect, v8f64>,
615 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
616
617defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
618 memopv8i64, vselect, v16i32>,
619 EVEX_CD8<32, CD8VF>, EVEX_V512;
620
621defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
622 memopv8i64, vselect, v8i64>, VEX_W,
623 EVEX_CD8<64, CD8VF>, EVEX_V512;
624
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]625let Predicates = [HasAVX512] in {
626def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
627 (v8f32 VR256X:$src2))),
628 (EXTRACT_SUBREG
629 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
630 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
631 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
632
633def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
634 (v8i32 VR256X:$src2))),
635 (EXTRACT_SUBREG
636 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
637 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
638 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
639}
640
641multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
642 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
643 SDNode OpNode, ValueType vt> {
644 def rr : AVX512BI<opc, MRMSrcReg,
645 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
646 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
647 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
648 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
649 def rm : AVX512BI<opc, MRMSrcMem,
650 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
651 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
652 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
653 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
654}
655
656defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
657 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
658defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
659 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
660
661defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
662 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
663defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
664 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
665
666def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
667 (COPY_TO_REGCLASS (VPCMPGTDZrr
668 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
669 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
670
671def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
672 (COPY_TO_REGCLASS (VPCMPEQDZrr
673 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
674 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
675
676multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
677 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
678 SDNode OpNode, ValueType vt, Operand CC, string asm,
679 string asm_alt> {
680 def rri : AVX512AIi8<opc, MRMSrcReg,
681 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
682 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
683 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
684 def rmi : AVX512AIi8<opc, MRMSrcMem,
685 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
686 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
687 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
688 // Accept explicit immediate argument form instead of comparison code.
689 let neverHasSideEffects = 1 in {
690 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
691 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
692 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
693 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
694 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
695 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
696 }
697}
698
699defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
700 X86cmpm, v16i32, AVXCC,
701 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
702 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
703 EVEX_V512, EVEX_CD8<32, CD8VF>;
704defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
705 X86cmpmu, v16i32, AVXCC,
706 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
707 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
708 EVEX_V512, EVEX_CD8<32, CD8VF>;
709
710defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
711 X86cmpm, v8i64, AVXCC,
712 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
713 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
714 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
715defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
716 X86cmpmu, v8i64, AVXCC,
717 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
719 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
720
721// avx512_cmp_packed - sse 1 & 2 compare packed instructions
722multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
723 X86MemOperand x86memop, Operand CC,
724 SDNode OpNode, ValueType vt, string asm,
725 string asm_alt, Domain d> {
726 def rri : AVX512PIi8<0xC2, MRMSrcReg,
727 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
728 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
729 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
730 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
731 [(set KRC:$dst,
732 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
733
734 // Accept explicit immediate argument form instead of comparison code.
735 let neverHasSideEffects = 1 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]736 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]737 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]738 asm_alt, [], d>;
739 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]740 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]741 asm_alt, [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]742 }
743}
744
745defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
746 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
747 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]748 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]749defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
750 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
751 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]752 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]753 EVEX_CD8<64, CD8VF>;
754
755def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
756 (COPY_TO_REGCLASS (VCMPPSZrri
757 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
758 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
759 imm:$cc), VK8)>;
760def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
761 (COPY_TO_REGCLASS (VPCMPDZrri
762 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
763 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
764 imm:$cc), VK8)>;
765def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
766 (COPY_TO_REGCLASS (VPCMPUDZrri
767 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
768 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
769 imm:$cc), VK8)>;
770
771// Mask register copy, including
772// - copy between mask registers
773// - load/store mask registers
774// - copy from GPR to mask register and vice versa
775//
776multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
777 string OpcodeStr, RegisterClass KRC,
778 ValueType vt, X86MemOperand x86memop> {
779 let neverHasSideEffects = 1 in {
780 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
782 let mayLoad = 1 in
783 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
784 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
785 [(set KRC:$dst, (vt (load addr:$src)))]>;
786 let mayStore = 1 in
787 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
788 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
789 }
790}
791
792multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
793 string OpcodeStr,
794 RegisterClass KRC, RegisterClass GRC> {
795 let neverHasSideEffects = 1 in {
796 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
797 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
798 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
799 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
800 }
801}
802
803let Predicates = [HasAVX512] in {
804 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
805 VEX, TB;
806 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
807 VEX, TB;
808}
809
810let Predicates = [HasAVX512] in {
811 // GR16 from/to 16-bit mask
812 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
813 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
814 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
815 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
816
817 // Store kreg in memory
818 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
819 (KMOVWmk addr:$dst, VK16:$src)>;
820
821 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
822 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
823}
824// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
825let Predicates = [HasAVX512] in {
826 // GR from/to 8-bit mask without native support
827 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
828 (COPY_TO_REGCLASS
829 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
830 VK8)>;
831 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
832 (EXTRACT_SUBREG
833 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
834 sub_8bit)>;
835}
836
837// Mask unary operation
838// - KNOT
839multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
840 RegisterClass KRC, SDPatternOperator OpNode> {
841 let Predicates = [HasAVX512] in
842 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
844 [(set KRC:$dst, (OpNode KRC:$src))]>;
845}
846
847multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
848 SDPatternOperator OpNode> {
849 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
850 VEX, TB;
851}
852
853defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
854
855def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
856def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
857 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
858
859// With AVX-512, 8-bit mask is promoted to 16-bit mask.
860def : Pat<(not VK8:$src),
861 (COPY_TO_REGCLASS
862 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
863
864// Mask binary operation
865// - KADD, KAND, KANDN, KOR, KXNOR, KXOR
866multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
867 RegisterClass KRC, SDPatternOperator OpNode> {
868 let Predicates = [HasAVX512] in
869 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
870 !strconcat(OpcodeStr,
871 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
872 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
873}
874
875multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
876 SDPatternOperator OpNode> {
877 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
878 VEX_4V, VEX_L, TB;
879}
880
881def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
882def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
883
884let isCommutable = 1 in {
885 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
886 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
887 let isCommutable = 0 in
888 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
889 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
890 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
891 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
892}
893
894multiclass avx512_mask_binop_int<string IntName, string InstName> {
895 let Predicates = [HasAVX512] in
896 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
897 VK16:$src1, VK16:$src2),
898 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
899}
900
901defm : avx512_mask_binop_int<"kadd", "KADD">;
902defm : avx512_mask_binop_int<"kand", "KAND">;
903defm : avx512_mask_binop_int<"kandn", "KANDN">;
904defm : avx512_mask_binop_int<"kor", "KOR">;
905defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
906defm : avx512_mask_binop_int<"kxor", "KXOR">;
907// With AVX-512, 8-bit mask is promoted to 16-bit mask.
908multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
909 let Predicates = [HasAVX512] in
910 def : Pat<(OpNode VK8:$src1, VK8:$src2),
911 (COPY_TO_REGCLASS
912 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
913 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
914}
915
916defm : avx512_binop_pat<and, KANDWrr>;
917defm : avx512_binop_pat<andn, KANDNWrr>;
918defm : avx512_binop_pat<or, KORWrr>;
919defm : avx512_binop_pat<xnor, KXNORWrr>;
920defm : avx512_binop_pat<xor, KXORWrr>;
921
922// Mask unpacking
923multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
924 RegisterClass KRC1, RegisterClass KRC2> {
925 let Predicates = [HasAVX512] in
926 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
927 !strconcat(OpcodeStr,
928 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
929}
930
931multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
932 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
933 VEX_4V, VEX_L, OpSize, TB;
934}
935
936defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
937
938multiclass avx512_mask_unpck_int<string IntName, string InstName> {
939 let Predicates = [HasAVX512] in
940 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
941 VK8:$src1, VK8:$src2),
942 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
943}
944
945defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
946// Mask bit testing
947multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
948 SDNode OpNode> {
949 let Predicates = [HasAVX512], Defs = [EFLAGS] in
950 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
951 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
952 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
953}
954
955multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
956 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
957 VEX, TB;
958}
959
960defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
961defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
962
963// Mask shift
964multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
965 SDNode OpNode> {
966 let Predicates = [HasAVX512] in
967 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
968 !strconcat(OpcodeStr,
969 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
970 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
971}
972
973multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
974 SDNode OpNode> {
975 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
976 VEX, OpSize, TA, VEX_W;
977}
978
979defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
980defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
981
982// Mask setting all 0s or 1s
983multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
984 let Predicates = [HasAVX512] in
985 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
986 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
987 [(set KRC:$dst, (VT Val))]>;
988}
989
990multiclass avx512_mask_setop_w<PatFrag Val> {
991 defm B : avx512_mask_setop<VK8, v8i1, Val>;
992 defm W : avx512_mask_setop<VK16, v16i1, Val>;
993}
994
995defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
996defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
997
998// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
999let Predicates = [HasAVX512] in {
1000 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1001 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1002}
1003def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1004 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1005
1006def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1007 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1008
1009def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1010 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1011
1012//===----------------------------------------------------------------------===//
1013// AVX-512 - Aligned and unaligned load and store
1014//
1015
1016multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1017 X86MemOperand x86memop, PatFrag ld_frag,
1018 string asm, Domain d> {
1019let neverHasSideEffects = 1 in
1020 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1021 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1022 EVEX;
1023let canFoldAsLoad = 1 in
1024 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1025 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1026 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1027let Constraints = "$src1 = $dst" in {
1028 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1029 (ins RC:$src1, KRC:$mask, RC:$src2),
1030 !strconcat(asm,
1031 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1032 EVEX, EVEX_K;
1033 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1034 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1035 !strconcat(asm,
1036 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1037 [], d>, EVEX, EVEX_K;
1038}
1039}
1040
1041defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1042 "vmovaps", SSEPackedSingle>,
1043 EVEX_V512, EVEX_CD8<32, CD8VF>;
1044defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1045 "vmovapd", SSEPackedDouble>,
1046 OpSize, EVEX_V512, VEX_W,
1047 EVEX_CD8<64, CD8VF>;
1048defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1049 "vmovups", SSEPackedSingle>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1050 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1051defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1052 "vmovupd", SSEPackedDouble>,
1053 OpSize, EVEX_V512, VEX_W,
1054 EVEX_CD8<64, CD8VF>;
1055def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1056 "vmovaps\t{$src, $dst|$dst, $src}",
1057 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1058 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1059def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1060 "vmovapd\t{$src, $dst|$dst, $src}",
1061 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1062 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1063 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1064def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1065 "vmovups\t{$src, $dst|$dst, $src}",
1066 [(store (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1067 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1068def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1069 "vmovupd\t{$src, $dst|$dst, $src}",
1070 [(store (v8f64 VR512:$src), addr:$dst)],
1071 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1072 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1073
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1074let neverHasSideEffects = 1 in {
1075 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1076 (ins VR512:$src),
1077 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1078 EVEX, EVEX_V512;
1079 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1080 (ins VR512:$src),
1081 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1082 EVEX, EVEX_V512, VEX_W;
1083let mayStore = 1 in {
1084 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1085 (ins i512mem:$dst, VR512:$src),
1086 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1087 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1088 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1089 (ins i512mem:$dst, VR512:$src),
1090 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1091 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1092}
1093let mayLoad = 1 in {
1094def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1095 (ins i512mem:$src),
1096 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1097 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1098def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1099 (ins i512mem:$src),
1100 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1101 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1102}
1103}
1104
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1105// 512-bit aligned load/store
1106def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1107def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1108
1109def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1110 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1111def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1112 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1113
1114multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1115 RegisterClass RC, RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1116 PatFrag ld_frag, X86MemOperand x86memop> {
1117let neverHasSideEffects = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1118 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1119 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1120let canFoldAsLoad = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1121 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1122 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1123 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1124let mayStore = 1 in
1125 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1126 (ins x86memop:$dst, VR512:$src),
1127 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1128let Constraints = "$src1 = $dst" in {
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1129 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1130 (ins RC:$src1, KRC:$mask, RC:$src2),
1131 !strconcat(asm,
1132 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1133 EVEX, EVEX_K;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1134 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1135 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1136 !strconcat(asm,
1137 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1138 []>, EVEX, EVEX_K;
1139}
1140}
1141
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1142defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1143 memopv16i32, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1144 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1145defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1146 memopv8i64, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1147 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1148
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1149// 512-bit unaligned load/store
1150def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1151def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1152
1153def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1154 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1155def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1156 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1157
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1158let AddedComplexity = 20 in {
1159def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1160 (v16f32 VR512:$src2))),
1161 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1162def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1163 (v8f64 VR512:$src2))),
1164 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1165def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1166 (v16i32 VR512:$src2))),
1167 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1168def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1169 (v8i64 VR512:$src2))),
1170 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1171}
1172// Move Int Doubleword to Packed Double Int
1173//
1174def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1175 "vmovd{z}\t{$src, $dst|$dst, $src}",
1176 [(set VR128X:$dst,
1177 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1178 EVEX, VEX_LIG;
1179def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1180 "vmovd{z}\t{$src, $dst|$dst, $src}",
1181 [(set VR128X:$dst,
1182 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1183 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1184def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1185 "vmovq{z}\t{$src, $dst|$dst, $src}",
1186 [(set VR128X:$dst,
1187 (v2i64 (scalar_to_vector GR64:$src)))],
1188 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1189let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1190def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1191 "vmovq{z}\t{$src, $dst|$dst, $src}",
1192 [(set FR64:$dst, (bitconvert GR64:$src))],
1193 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1194def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1195 "vmovq{z}\t{$src, $dst|$dst, $src}",
1196 [(set GR64:$dst, (bitconvert FR64:$src))],
1197 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1198}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1199def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1200 "vmovq{z}\t{$src, $dst|$dst, $src}",
1201 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1202 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1203 EVEX_CD8<64, CD8VT1>;
1204
1205// Move Int Doubleword to Single Scalar
1206//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1207let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1208def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1209 "vmovd{z}\t{$src, $dst|$dst, $src}",
1210 [(set FR32X:$dst, (bitconvert GR32:$src))],
1211 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1212
1213def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1214 "vmovd{z}\t{$src, $dst|$dst, $src}",
1215 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1216 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1217}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1218
1219// Move Packed Doubleword Int to Packed Double Int
1220//
1221def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1222 "vmovd{z}\t{$src, $dst|$dst, $src}",
1223 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1224 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1225 EVEX, VEX_LIG;
1226def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1227 (ins i32mem:$dst, VR128X:$src),
1228 "vmovd{z}\t{$src, $dst|$dst, $src}",
1229 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1230 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1231 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1232
1233// Move Packed Doubleword Int first element to Doubleword Int
1234//
1235def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1236 "vmovq{z}\t{$src, $dst|$dst, $src}",
1237 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1238 (iPTR 0)))],
1239 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1240 Requires<[HasAVX512, In64BitMode]>;
1241
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1242def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1243 (ins i64mem:$dst, VR128X:$src),
1244 "vmovq{z}\t{$src, $dst|$dst, $src}",
1245 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1246 addr:$dst)], IIC_SSE_MOVDQ>,
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1247 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1248 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1249
1250// Move Scalar Single to Double Int
1251//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1252let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1253def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1254 (ins FR32X:$src),
1255 "vmovd{z}\t{$src, $dst|$dst, $src}",
1256 [(set GR32:$dst, (bitconvert FR32X:$src))],
1257 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1258def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1259 (ins i32mem:$dst, FR32X:$src),
1260 "vmovd{z}\t{$src, $dst|$dst, $src}",
1261 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1262 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1263}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1264
1265// Move Quadword Int to Packed Quadword Int
1266//
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1267def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1268 (ins i64mem:$src),
1269 "vmovq{z}\t{$src, $dst|$dst, $src}",
1270 [(set VR128X:$dst,
1271 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1272 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1273
1274//===----------------------------------------------------------------------===//
1275// AVX-512 MOVSS, MOVSD
1276//===----------------------------------------------------------------------===//
1277
1278multiclass avx512_move_scalar <string asm, RegisterClass RC,
1279 SDNode OpNode, ValueType vt,
1280 X86MemOperand x86memop, PatFrag mem_pat> {
1281 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1282 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1283 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1284 (scalar_to_vector RC:$src2))))],
1285 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1286 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1287 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1288 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1289 EVEX, VEX_LIG;
1290 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1291 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1292 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1293 EVEX, VEX_LIG;
1294}
1295
1296let ExeDomain = SSEPackedSingle in
1297defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1298 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1299
1300let ExeDomain = SSEPackedDouble in
1301defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1302 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1303
1304
1305// For the disassembler
1306let isCodeGenOnly = 1 in {
1307 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1308 (ins VR128X:$src1, FR32X:$src2),
1309 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1310 IIC_SSE_MOV_S_RR>,
1311 XS, EVEX_4V, VEX_LIG;
1312 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1313 (ins VR128X:$src1, FR64X:$src2),
1314 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1315 IIC_SSE_MOV_S_RR>,
1316 XD, EVEX_4V, VEX_LIG, VEX_W;
1317}
1318
1319let Predicates = [HasAVX512] in {
1320 let AddedComplexity = 15 in {
1321 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1322 // MOVS{S,D} to the lower bits.
1323 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1324 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1325 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1326 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1327 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1328 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1329 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1330 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1331
1332 // Move low f32 and clear high bits.
1333 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1334 (SUBREG_TO_REG (i32 0),
1335 (VMOVSSZrr (v4f32 (V_SET0)),
1336 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1337 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1338 (SUBREG_TO_REG (i32 0),
1339 (VMOVSSZrr (v4i32 (V_SET0)),
1340 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1341 }
1342
1343 let AddedComplexity = 20 in {
1344 // MOVSSrm zeros the high parts of the register; represent this
1345 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1346 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1347 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1348 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1349 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1350 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1351 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1352
1353 // MOVSDrm zeros the high parts of the register; represent this
1354 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1355 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1356 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1357 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1358 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1359 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1360 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1361 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1362 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1363 def : Pat<(v2f64 (X86vzload addr:$src)),
1364 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1365
1366 // Represent the same patterns above but in the form they appear for
1367 // 256-bit types
1368 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1369 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1370 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1371 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1372 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1373 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1374 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1375 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1376 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1377 }
1378 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1379 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1380 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1381 FR32X:$src)), sub_xmm)>;
1382 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1383 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1384 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1385 FR64X:$src)), sub_xmm)>;
1386 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1387 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1388 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1389
1390 // Move low f64 and clear high bits.
1391 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1392 (SUBREG_TO_REG (i32 0),
1393 (VMOVSDZrr (v2f64 (V_SET0)),
1394 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1395
1396 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1397 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1398 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1399
1400 // Extract and store.
1401 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1402 addr:$dst),
1403 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1404 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1405 addr:$dst),
1406 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1407
1408 // Shuffle with VMOVSS
1409 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1410 (VMOVSSZrr (v4i32 VR128X:$src1),
1411 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1412 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1413 (VMOVSSZrr (v4f32 VR128X:$src1),
1414 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1415
1416 // 256-bit variants
1417 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1418 (SUBREG_TO_REG (i32 0),
1419 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1420 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1421 sub_xmm)>;
1422 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1423 (SUBREG_TO_REG (i32 0),
1424 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1425 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1426 sub_xmm)>;
1427
1428 // Shuffle with VMOVSD
1429 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1430 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1431 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1432 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1433 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1434 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1435 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1436 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1437
1438 // 256-bit variants
1439 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1440 (SUBREG_TO_REG (i32 0),
1441 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1442 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1443 sub_xmm)>;
1444 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1445 (SUBREG_TO_REG (i32 0),
1446 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1447 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1448 sub_xmm)>;
1449
1450 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1451 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1452 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1453 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1454 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1455 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1456 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1457 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1458}
1459
1460let AddedComplexity = 15 in
1461def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1462 (ins VR128X:$src),
1463 "vmovq{z}\t{$src, $dst|$dst, $src}",
1464 [(set VR128X:$dst, (v2i64 (X86vzmovl
1465 (v2i64 VR128X:$src))))],
1466 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1467
1468let AddedComplexity = 20 in
1469def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1470 (ins i128mem:$src),
1471 "vmovq{z}\t{$src, $dst|$dst, $src}",
1472 [(set VR128X:$dst, (v2i64 (X86vzmovl
1473 (loadv2i64 addr:$src))))],
1474 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1475 EVEX_CD8<8, CD8VT8>;
1476
1477let Predicates = [HasAVX512] in {
1478 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1479 let AddedComplexity = 20 in {
1480 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1481 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1482 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1483 (VMOV64toPQIZrr GR64:$src)>;
1484 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1485 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1486
1487 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1488 (VMOVDI2PDIZrm addr:$src)>;
1489 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1490 (VMOVDI2PDIZrm addr:$src)>;
1491 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1492 (VMOVZPQILo2PQIZrm addr:$src)>;
1493 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1494 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1495 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1496
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1497 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1498 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1499 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1500 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1501 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1502 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1503 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1504}
1505
1506def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1507 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1508
1509def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1510 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1511
1512def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1513 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1514
1515def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1516 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1517
1518//===----------------------------------------------------------------------===//
1519// AVX-512 - Integer arithmetic
1520//
1521multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1522 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1523 X86MemOperand x86memop, PatFrag scalar_mfrag,
1524 X86MemOperand x86scalar_mop, string BrdcstStr,
1525 OpndItins itins, bit IsCommutable = 0> {
1526 let isCommutable = IsCommutable in
1527 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1528 (ins RC:$src1, RC:$src2),
1529 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1530 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1531 itins.rr>, EVEX_4V;
1532 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1533 (ins RC:$src1, x86memop:$src2),
1534 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1535 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1536 itins.rm>, EVEX_4V;
1537 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1538 (ins RC:$src1, x86scalar_mop:$src2),
1539 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1540 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1541 [(set RC:$dst, (OpNode RC:$src1,
1542 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1543 itins.rm>, EVEX_4V, EVEX_B;
1544}
1545multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1546 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1547 PatFrag memop_frag, X86MemOperand x86memop,
1548 OpndItins itins,
1549 bit IsCommutable = 0> {
1550 let isCommutable = IsCommutable in
1551 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1552 (ins RC:$src1, RC:$src2),
1553 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1554 []>, EVEX_4V, VEX_W;
1555 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1556 (ins RC:$src1, x86memop:$src2),
1557 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1558 []>, EVEX_4V, VEX_W;
1559}
1560
1561defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1562 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1563 EVEX_V512, EVEX_CD8<32, CD8VF>;
1564
1565defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1566 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1567 EVEX_V512, EVEX_CD8<32, CD8VF>;
1568
1569defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1570 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1571 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1572
1573defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1574 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1575 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1576
1577defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1578 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1579 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1580
1581defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1582 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1583 EVEX_V512, EVEX_CD8<64, CD8VF>;
1584
1585defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1586 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1587 EVEX_CD8<64, CD8VF>;
1588
1589def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1590 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1591
1592//===----------------------------------------------------------------------===//
1593// AVX-512 - Unpack Instructions
1594//===----------------------------------------------------------------------===//
1595
1596multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1597 PatFrag mem_frag, RegisterClass RC,
1598 X86MemOperand x86memop, string asm,
1599 Domain d> {
1600 def rr : AVX512PI<opc, MRMSrcReg,
1601 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1602 asm, [(set RC:$dst,
1603 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1604 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1605 def rm : AVX512PI<opc, MRMSrcMem,
1606 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1607 asm, [(set RC:$dst,
1608 (vt (OpNode RC:$src1,
1609 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1610 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1611}
1612
1613defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1614 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1615 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1616defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1617 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1618 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1619defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1620 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1621 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1622defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1623 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1624 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1625
1626multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1627 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1628 X86MemOperand x86memop> {
1629 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1630 (ins RC:$src1, RC:$src2),
1631 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1632 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1633 IIC_SSE_UNPCK>, EVEX_4V;
1634 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1635 (ins RC:$src1, x86memop:$src2),
1636 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1637 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1638 (bitconvert (memop_frag addr:$src2)))))],
1639 IIC_SSE_UNPCK>, EVEX_4V;
1640}
1641defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1642 VR512, memopv16i32, i512mem>, EVEX_V512,
1643 EVEX_CD8<32, CD8VF>;
1644defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1645 VR512, memopv8i64, i512mem>, EVEX_V512,
1646 VEX_W, EVEX_CD8<64, CD8VF>;
1647defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1648 VR512, memopv16i32, i512mem>, EVEX_V512,
1649 EVEX_CD8<32, CD8VF>;
1650defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1651 VR512, memopv8i64, i512mem>, EVEX_V512,
1652 VEX_W, EVEX_CD8<64, CD8VF>;
1653//===----------------------------------------------------------------------===//
1654// AVX-512 - PSHUFD
1655//
1656
1657multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1658 SDNode OpNode, PatFrag mem_frag,
1659 X86MemOperand x86memop, ValueType OpVT> {
1660 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1661 (ins RC:$src1, i8imm:$src2),
1662 !strconcat(OpcodeStr,
1663 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1664 [(set RC:$dst,
1665 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1666 EVEX;
1667 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1668 (ins x86memop:$src1, i8imm:$src2),
1669 !strconcat(OpcodeStr,
1670 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1671 [(set RC:$dst,
1672 (OpVT (OpNode (mem_frag addr:$src1),
1673 (i8 imm:$src2))))]>, EVEX;
1674}
1675
1676defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1677 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1678
1679let ExeDomain = SSEPackedSingle in
1680defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1681 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1682 EVEX_CD8<32, CD8VF>;
1683let ExeDomain = SSEPackedDouble in
1684defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1685 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1686 VEX_W, EVEX_CD8<32, CD8VF>;
1687
1688def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1689 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1690def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1691 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1692
1693//===----------------------------------------------------------------------===//
1694// AVX-512 Logical Instructions
1695//===----------------------------------------------------------------------===//
1696
1697defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1698 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1699 EVEX_V512, EVEX_CD8<32, CD8VF>;
1700defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1701 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1702 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1703defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1704 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1705 EVEX_V512, EVEX_CD8<32, CD8VF>;
1706defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1707 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1708 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1709defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1710 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1711 EVEX_V512, EVEX_CD8<32, CD8VF>;
1712defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1713 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1714 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1715defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1716 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1717 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1718defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1719 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1720 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1721
1722//===----------------------------------------------------------------------===//
1723// AVX-512 FP arithmetic
1724//===----------------------------------------------------------------------===//
1725
1726multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1727 SizeItins itins> {
1728 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1729 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1730 EVEX_CD8<32, CD8VT1>;
1731 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1732 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1733 EVEX_CD8<64, CD8VT1>;
1734}
1735
1736let isCommutable = 1 in {
1737defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1738defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1739defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1740defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1741}
1742let isCommutable = 0 in {
1743defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1744defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1745}
1746
1747multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1748 RegisterClass RC, ValueType vt,
1749 X86MemOperand x86memop, PatFrag mem_frag,
1750 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1751 string BrdcstStr,
1752 Domain d, OpndItins itins, bit commutable> {
1753 let isCommutable = commutable in
1754 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1755 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1756 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1757 EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1758 let mayLoad = 1 in {
1759 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1760 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1761 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1762 itins.rm, d>, EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1763 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1764 (ins RC:$src1, x86scalar_mop:$src2),
1765 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1766 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1767 [(set RC:$dst, (OpNode RC:$src1,
1768 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1769 itins.rm, d>, EVEX_4V, EVEX_B, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1770 }
1771}
1772
1773defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1774 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1775 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1776
1777defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1778 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1779 SSE_ALU_ITINS_P.d, 1>,
1780 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1781
1782defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1783 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1784 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1785defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1786 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1787 SSE_ALU_ITINS_P.d, 1>,
1788 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1789
1790defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1791 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1792 SSE_ALU_ITINS_P.s, 1>,
1793 EVEX_V512, EVEX_CD8<32, CD8VF>;
1794defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1795 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1796 SSE_ALU_ITINS_P.s, 1>,
1797 EVEX_V512, EVEX_CD8<32, CD8VF>;
1798
1799defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1800 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1801 SSE_ALU_ITINS_P.d, 1>,
1802 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1803defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1804 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1805 SSE_ALU_ITINS_P.d, 1>,
1806 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1807
1808defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1809 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1810 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1811defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1812 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1813 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1814
1815defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1816 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1817 SSE_ALU_ITINS_P.d, 0>,
1818 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1819defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1820 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1821 SSE_ALU_ITINS_P.d, 0>,
1822 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1823
1824//===----------------------------------------------------------------------===//
1825// AVX-512 VPTESTM instructions
1826//===----------------------------------------------------------------------===//
1827
1828multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1829 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1830 SDNode OpNode, ValueType vt> {
1831 def rr : AVX5128I<opc, MRMSrcReg,
1832 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1833 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1834 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1835 def rm : AVX5128I<opc, MRMSrcMem,
1836 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1837 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1838 [(set KRC:$dst, (OpNode (vt RC:$src1),
1839 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1840}
1841
1842defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1843 memopv16i32, X86testm, v16i32>, EVEX_V512,
1844 EVEX_CD8<32, CD8VF>;
1845defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1846 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1847 EVEX_CD8<64, CD8VF>;
1848
1849//===----------------------------------------------------------------------===//
1850// AVX-512 Shift instructions
1851//===----------------------------------------------------------------------===//
1852multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1853 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1854 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1855 RegisterClass KRC> {
1856 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1857 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1858 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1859 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1860 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1861 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1862 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1863 !strconcat(OpcodeStr,
1864 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1865 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1866 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1867 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1868 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1869 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1870 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1871 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1872 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1873 !strconcat(OpcodeStr,
1874 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1875 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1876}
1877
1878multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1879 RegisterClass RC, ValueType vt, ValueType SrcVT,
1880 PatFrag bc_frag, RegisterClass KRC> {
1881 // src2 is always 128-bit
1882 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1883 (ins RC:$src1, VR128X:$src2),
1884 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1885 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1886 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1887 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1888 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1889 !strconcat(OpcodeStr,
1890 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1891 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1892 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1893 (ins RC:$src1, i128mem:$src2),
1894 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1895 [(set RC:$dst, (vt (OpNode RC:$src1,
1896 (bc_frag (memopv2i64 addr:$src2)))))],
1897 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1898 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1899 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1900 !strconcat(OpcodeStr,
1901 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1902 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1903}
1904
1905defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1906 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1907 EVEX_V512, EVEX_CD8<32, CD8VF>;
1908defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1909 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1910 EVEX_CD8<32, CD8VQ>;
1911
1912defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1913 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1914 EVEX_CD8<64, CD8VF>, VEX_W;
1915defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1916 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1917 EVEX_CD8<64, CD8VQ>, VEX_W;
1918
1919defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1920 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1921 EVEX_CD8<32, CD8VF>;
1922defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1923 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1924 EVEX_CD8<32, CD8VQ>;
1925
1926defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1927 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1928 EVEX_CD8<64, CD8VF>, VEX_W;
1929defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1930 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1931 EVEX_CD8<64, CD8VQ>, VEX_W;
1932
1933defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1934 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1935 EVEX_V512, EVEX_CD8<32, CD8VF>;
1936defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1937 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1938 EVEX_CD8<32, CD8VQ>;
1939
1940defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1941 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1942 EVEX_CD8<64, CD8VF>, VEX_W;
1943defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1944 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1945 EVEX_CD8<64, CD8VQ>, VEX_W;
1946
1947//===-------------------------------------------------------------------===//
1948// Variable Bit Shifts
1949//===-------------------------------------------------------------------===//
1950multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1951 RegisterClass RC, ValueType vt,
1952 X86MemOperand x86memop, PatFrag mem_frag> {
1953 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1954 (ins RC:$src1, RC:$src2),
1955 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1956 [(set RC:$dst,
1957 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1958 EVEX_4V;
1959 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1960 (ins RC:$src1, x86memop:$src2),
1961 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1962 [(set RC:$dst,
1963 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
1964 EVEX_4V;
1965}
1966
1967defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
1968 i512mem, memopv16i32>, EVEX_V512,
1969 EVEX_CD8<32, CD8VF>;
1970defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
1971 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1972 EVEX_CD8<64, CD8VF>;
1973defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
1974 i512mem, memopv16i32>, EVEX_V512,
1975 EVEX_CD8<32, CD8VF>;
1976defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
1977 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1978 EVEX_CD8<64, CD8VF>;
1979defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
1980 i512mem, memopv16i32>, EVEX_V512,
1981 EVEX_CD8<32, CD8VF>;
1982defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
1983 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1984 EVEX_CD8<64, CD8VF>;
1985
1986//===----------------------------------------------------------------------===//
1987// AVX-512 - MOVDDUP
1988//===----------------------------------------------------------------------===//
1989
1990multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
1991 X86MemOperand x86memop, PatFrag memop_frag> {
1992def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1993 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1994 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
1995def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1996 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1997 [(set RC:$dst,
1998 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
1999}
2000
2001defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2002 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2003def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2004 (VMOVDDUPZrm addr:$src)>;
2005
2006def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2007 (ins VR128X:$src1, VR128X:$src2),
2008 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2009 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2010 IIC_SSE_MOV_LH>, EVEX_4V;
2011def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2012 (ins VR128X:$src1, VR128X:$src2),
2013 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2014 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2015 IIC_SSE_MOV_LH>, EVEX_4V;
2016
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2017let Predicates = [HasAVX512] in {
2018 // MOVLHPS patterns
2019 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2020 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2021 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2022 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2023
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2024 // MOVHLPS patterns
2025 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2026 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2027}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2028
2029//===----------------------------------------------------------------------===//
2030// FMA - Fused Multiply Operations
2031//
2032let Constraints = "$src1 = $dst" in {
2033multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2034 RegisterClass RC, X86MemOperand x86memop,
2035 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2036 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2037 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2038 (ins RC:$src1, RC:$src2, RC:$src3),
2039 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2040 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2041
2042 let mayLoad = 1 in
2043 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2044 (ins RC:$src1, RC:$src2, x86memop:$src3),
2045 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2046 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2047 (mem_frag addr:$src3))))]>;
2048 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2049 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2050 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2051 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2052 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2053 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2054}
2055} // Constraints = "$src1 = $dst"
2056
2057let ExeDomain = SSEPackedSingle in {
2058 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2059 memopv16f32, f32mem, loadf32, "{1to16}",
2060 X86Fmadd, v16f32>, EVEX_V512,
2061 EVEX_CD8<32, CD8VF>;
2062 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2063 memopv16f32, f32mem, loadf32, "{1to16}",
2064 X86Fmsub, v16f32>, EVEX_V512,
2065 EVEX_CD8<32, CD8VF>;
2066 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2067 memopv16f32, f32mem, loadf32, "{1to16}",
2068 X86Fmaddsub, v16f32>,
2069 EVEX_V512, EVEX_CD8<32, CD8VF>;
2070 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2071 memopv16f32, f32mem, loadf32, "{1to16}",
2072 X86Fmsubadd, v16f32>,
2073 EVEX_V512, EVEX_CD8<32, CD8VF>;
2074 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2075 memopv16f32, f32mem, loadf32, "{1to16}",
2076 X86Fnmadd, v16f32>, EVEX_V512,
2077 EVEX_CD8<32, CD8VF>;
2078 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2079 memopv16f32, f32mem, loadf32, "{1to16}",
2080 X86Fnmsub, v16f32>, EVEX_V512,
2081 EVEX_CD8<32, CD8VF>;
2082}
2083let ExeDomain = SSEPackedDouble in {
2084 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2085 memopv8f64, f64mem, loadf64, "{1to8}",
2086 X86Fmadd, v8f64>, EVEX_V512,
2087 VEX_W, EVEX_CD8<64, CD8VF>;
2088 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2089 memopv8f64, f64mem, loadf64, "{1to8}",
2090 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2091 EVEX_CD8<64, CD8VF>;
2092 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2093 memopv8f64, f64mem, loadf64, "{1to8}",
2094 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2095 EVEX_CD8<64, CD8VF>;
2096 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2097 memopv8f64, f64mem, loadf64, "{1to8}",
2098 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2099 EVEX_CD8<64, CD8VF>;
2100 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2101 memopv8f64, f64mem, loadf64, "{1to8}",
2102 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2103 EVEX_CD8<64, CD8VF>;
2104 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2105 memopv8f64, f64mem, loadf64, "{1to8}",
2106 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2107 EVEX_CD8<64, CD8VF>;
2108}
2109
2110let Constraints = "$src1 = $dst" in {
2111multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2112 RegisterClass RC, X86MemOperand x86memop,
2113 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2114 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2115 let mayLoad = 1 in
2116 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2117 (ins RC:$src1, RC:$src3, x86memop:$src2),
2118 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2119 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2120 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2121 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2122 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2123 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2124 [(set RC:$dst, (OpNode RC:$src1,
2125 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2126}
2127} // Constraints = "$src1 = $dst"
2128
2129
2130let ExeDomain = SSEPackedSingle in {
2131 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2132 memopv16f32, f32mem, loadf32, "{1to16}",
2133 X86Fmadd, v16f32>, EVEX_V512,
2134 EVEX_CD8<32, CD8VF>;
2135 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2136 memopv16f32, f32mem, loadf32, "{1to16}",
2137 X86Fmsub, v16f32>, EVEX_V512,
2138 EVEX_CD8<32, CD8VF>;
2139 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2140 memopv16f32, f32mem, loadf32, "{1to16}",
2141 X86Fmaddsub, v16f32>,
2142 EVEX_V512, EVEX_CD8<32, CD8VF>;
2143 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2144 memopv16f32, f32mem, loadf32, "{1to16}",
2145 X86Fmsubadd, v16f32>,
2146 EVEX_V512, EVEX_CD8<32, CD8VF>;
2147 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2148 memopv16f32, f32mem, loadf32, "{1to16}",
2149 X86Fnmadd, v16f32>, EVEX_V512,
2150 EVEX_CD8<32, CD8VF>;
2151 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2152 memopv16f32, f32mem, loadf32, "{1to16}",
2153 X86Fnmsub, v16f32>, EVEX_V512,
2154 EVEX_CD8<32, CD8VF>;
2155}
2156let ExeDomain = SSEPackedDouble in {
2157 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2158 memopv8f64, f64mem, loadf64, "{1to8}",
2159 X86Fmadd, v8f64>, EVEX_V512,
2160 VEX_W, EVEX_CD8<64, CD8VF>;
2161 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2162 memopv8f64, f64mem, loadf64, "{1to8}",
2163 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2164 EVEX_CD8<64, CD8VF>;
2165 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2166 memopv8f64, f64mem, loadf64, "{1to8}",
2167 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2168 EVEX_CD8<64, CD8VF>;
2169 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2170 memopv8f64, f64mem, loadf64, "{1to8}",
2171 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2172 EVEX_CD8<64, CD8VF>;
2173 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2174 memopv8f64, f64mem, loadf64, "{1to8}",
2175 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2176 EVEX_CD8<64, CD8VF>;
2177 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2178 memopv8f64, f64mem, loadf64, "{1to8}",
2179 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2180 EVEX_CD8<64, CD8VF>;
2181}
2182
2183// Scalar FMA
2184let Constraints = "$src1 = $dst" in {
2185multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2186 RegisterClass RC, ValueType OpVT,
2187 X86MemOperand x86memop, Operand memop,
2188 PatFrag mem_frag> {
2189 let isCommutable = 1 in
2190 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2191 (ins RC:$src1, RC:$src2, RC:$src3),
2192 !strconcat(OpcodeStr,
2193 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2194 [(set RC:$dst,
2195 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2196 let mayLoad = 1 in
2197 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2198 (ins RC:$src1, RC:$src2, f128mem:$src3),
2199 !strconcat(OpcodeStr,
2200 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2201 [(set RC:$dst,
2202 (OpVT (OpNode RC:$src2, RC:$src1,
2203 (mem_frag addr:$src3))))]>;
2204}
2205
2206} // Constraints = "$src1 = $dst"
2207
2208defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2209 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2210defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2211 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2212defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2213 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2214defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2215 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2216defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2217 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2218defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2219 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2220defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2221 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2222defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2223 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2224
2225//===----------------------------------------------------------------------===//
2226// AVX-512 Scalar convert from sign integer to float/double
2227//===----------------------------------------------------------------------===//
2228
2229multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2230 X86MemOperand x86memop, string asm> {
2231let neverHasSideEffects = 1 in {
2232 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2233 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2234 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2235 let mayLoad = 1 in
2236 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2237 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2238 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2239 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2240} // neverHasSideEffects = 1
2241}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2242let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2243defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2244 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2245defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2246 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2247defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2248 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2249defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2250 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2251
2252def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2253 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2254def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2255 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2256def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2257 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2258def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2259 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2260
2261def : Pat<(f32 (sint_to_fp GR32:$src)),
2262 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2263def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2264 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2265def : Pat<(f64 (sint_to_fp GR32:$src)),
2266 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2267def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2268 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2269
2270defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}{z}">,
2271 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2272defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}{z}">,
2273 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2274defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}{z}">,
2275 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2276defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}{z}">,
2277 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2278
2279def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2280 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2281def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2282 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2283def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2284 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2285def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2286 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2287
2288def : Pat<(f32 (uint_to_fp GR32:$src)),
2289 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2290def : Pat<(f32 (uint_to_fp GR64:$src)),
2291 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2292def : Pat<(f64 (uint_to_fp GR32:$src)),
2293 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2294def : Pat<(f64 (uint_to_fp GR64:$src)),
2295 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2296}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2297
2298//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2299// AVX-512 Scalar convert from float/double to integer
2300//===----------------------------------------------------------------------===//
2301multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2302 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2303 string asm> {
2304let neverHasSideEffects = 1 in {
2305 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2306 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2307 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
2308 let mayLoad = 1 in
2309 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2310 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
2311} // neverHasSideEffects = 1
2312}
2313let Predicates = [HasAVX512] in {
2314// Convert float/double to signed/unsigned int 32/64
2315defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2316 ssmem, sse_load_f32, "cvtss2si{z}">,
2317 XS, EVEX_CD8<32, CD8VT1>;
2318defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2319 ssmem, sse_load_f32, "cvtss2si{z}">,
2320 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2321defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2322 ssmem, sse_load_f32, "cvtss2usi{z}">,
2323 XS, EVEX_CD8<32, CD8VT1>;
2324defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2325 int_x86_avx512_cvtss2usi64, ssmem,
2326 sse_load_f32, "cvtss2usi{z}">, XS, VEX_W,
2327 EVEX_CD8<32, CD8VT1>;
2328defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2329 sdmem, sse_load_f64, "cvtsd2si{z}">,
2330 XD, EVEX_CD8<64, CD8VT1>;
2331defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2332 sdmem, sse_load_f64, "cvtsd2si{z}">,
2333 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2334defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2335 sdmem, sse_load_f64, "cvtsd2usi{z}">,
2336 XD, EVEX_CD8<64, CD8VT1>;
2337defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2338 int_x86_avx512_cvtsd2usi64, sdmem,
2339 sse_load_f64, "cvtsd2usi{z}">, XD, VEX_W,
2340 EVEX_CD8<64, CD8VT1>;
2341
2342defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2343 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}{z}",
2344 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2345defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2346 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}{z}",
2347 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2348defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2349 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}{z}",
2350 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2351defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2352 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}{z}",
2353 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2354
2355defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2356 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}{z}",
2357 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2358defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2359 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}{z}",
2360 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2361defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2362 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}{z}",
2363 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2364defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2365 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}{z}",
2366 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2367
2368// Convert float/double to signed/unsigned int 32/64 with truncation
2369defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2370 ssmem, sse_load_f32, "cvttss2si{z}">,
2371 XS, EVEX_CD8<32, CD8VT1>;
2372defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2373 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2374 "cvttss2si{z}">, XS, VEX_W,
2375 EVEX_CD8<32, CD8VT1>;
2376defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2377 sdmem, sse_load_f64, "cvttsd2si{z}">, XD,
2378 EVEX_CD8<64, CD8VT1>;
2379defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2380 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2381 "cvttsd2si{z}">, XD, VEX_W,
2382 EVEX_CD8<64, CD8VT1>;
2383defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2384 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2385 "cvttss2si{z}">, XS, EVEX_CD8<32, CD8VT1>;
2386defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2387 int_x86_avx512_cvttss2usi64, ssmem,
2388 sse_load_f32, "cvttss2usi{z}">, XS, VEX_W,
2389 EVEX_CD8<32, CD8VT1>;
2390defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2391 int_x86_avx512_cvttsd2usi,
2392 sdmem, sse_load_f64, "cvttsd2usi{z}">, XD,
2393 EVEX_CD8<64, CD8VT1>;
2394defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2395 int_x86_avx512_cvttsd2usi64, sdmem,
2396 sse_load_f64, "cvttsd2usi{z}">, XD, VEX_W,
2397 EVEX_CD8<64, CD8VT1>;
2398}
2399
2400multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2401 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2402 string asm> {
2403 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2404 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2405 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2406 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2407 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2408 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2409}
2410
2411defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2412 loadf32, "cvttss2si{z}">, XS,
2413 EVEX_CD8<32, CD8VT1>;
2414defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2415 loadf32, "cvttss2usi{z}">, XS,
2416 EVEX_CD8<32, CD8VT1>;
2417defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2418 loadf32, "cvttss2si{z}">, XS, VEX_W,
2419 EVEX_CD8<32, CD8VT1>;
2420defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2421 loadf32, "cvttss2usi{z}">, XS, VEX_W,
2422 EVEX_CD8<32, CD8VT1>;
2423defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2424 loadf64, "cvttsd2si{z}">, XD,
2425 EVEX_CD8<64, CD8VT1>;
2426defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2427 loadf64, "cvttsd2usi{z}">, XD,
2428 EVEX_CD8<64, CD8VT1>;
2429defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2430 loadf64, "cvttsd2si{z}">, XD, VEX_W,
2431 EVEX_CD8<64, CD8VT1>;
2432defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2433 loadf64, "cvttsd2usi{z}">, XD, VEX_W,
2434 EVEX_CD8<64, CD8VT1>;
2435//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2436// AVX-512 Convert form float to double and back
2437//===----------------------------------------------------------------------===//
2438let neverHasSideEffects = 1 in {
2439def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2440 (ins FR32X:$src1, FR32X:$src2),
2441 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2442 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2443let mayLoad = 1 in
2444def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2445 (ins FR32X:$src1, f32mem:$src2),
2446 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2447 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2448 EVEX_CD8<32, CD8VT1>;
2449
2450// Convert scalar double to scalar single
2451def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2452 (ins FR64X:$src1, FR64X:$src2),
2453 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2454 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2455let mayLoad = 1 in
2456def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2457 (ins FR64X:$src1, f64mem:$src2),
2458 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2459 []>, EVEX_4V, VEX_LIG, VEX_W,
2460 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2461}
2462
2463def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2464 Requires<[HasAVX512]>;
2465def : Pat<(fextend (loadf32 addr:$src)),
2466 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2467
2468def : Pat<(extloadf32 addr:$src),
2469 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2470 Requires<[HasAVX512, OptForSize]>;
2471
2472def : Pat<(extloadf32 addr:$src),
2473 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2474 Requires<[HasAVX512, OptForSpeed]>;
2475
2476def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2477 Requires<[HasAVX512]>;
2478
2479multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2480 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2481 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2482 Domain d> {
2483let neverHasSideEffects = 1 in {
2484 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2485 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2486 [(set DstRC:$dst,
2487 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2488 let mayLoad = 1 in
2489 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2490 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2491 [(set DstRC:$dst,
2492 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2493} // neverHasSideEffects = 1
2494}
2495
2496defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2497 memopv8f64, f512mem, v8f32, v8f64,
2498 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2499 EVEX_CD8<64, CD8VF>;
2500
2501defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2502 memopv4f64, f256mem, v8f64, v8f32,
2503 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2504def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2505 (VCVTPS2PDZrm addr:$src)>;
2506
2507//===----------------------------------------------------------------------===//
2508// AVX-512 Vector convert from sign integer to float/double
2509//===----------------------------------------------------------------------===//
2510
2511defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2512 memopv8i64, i512mem, v16f32, v16i32,
2513 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2514
2515defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2516 memopv4i64, i256mem, v8f64, v8i32,
2517 SSEPackedDouble>, EVEX_V512, XS,
2518 EVEX_CD8<32, CD8VH>;
2519
2520defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2521 memopv16f32, f512mem, v16i32, v16f32,
2522 SSEPackedSingle>, EVEX_V512, XS,
2523 EVEX_CD8<32, CD8VF>;
2524
2525defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2526 memopv8f64, f512mem, v8i32, v8f64,
2527 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2528 EVEX_CD8<64, CD8VF>;
2529
2530defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2531 memopv16f32, f512mem, v16i32, v16f32,
2532 SSEPackedSingle>, EVEX_V512,
2533 EVEX_CD8<32, CD8VF>;
2534
2535defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2536 memopv8f64, f512mem, v8i32, v8f64,
2537 SSEPackedDouble>, EVEX_V512, VEX_W,
2538 EVEX_CD8<64, CD8VF>;
2539
2540defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2541 memopv4i64, f256mem, v8f64, v8i32,
2542 SSEPackedDouble>, EVEX_V512, XS,
2543 EVEX_CD8<32, CD8VH>;
2544
2545defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2546 memopv16i32, f512mem, v16f32, v16i32,
2547 SSEPackedSingle>, EVEX_V512, XD,
2548 EVEX_CD8<32, CD8VF>;
2549
2550def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2551 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2552 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2553
2554
2555def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2556 (VCVTDQ2PSZrr VR512:$src)>;
2557def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2558 (VCVTDQ2PSZrm addr:$src)>;
2559
2560def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2561 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2562 [(set VR512:$dst,
2563 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2564 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2565def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2566 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2567 [(set VR512:$dst,
2568 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2569 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2570
2571
2572let Predicates = [HasAVX512] in {
2573 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2574 (VCVTPD2PSZrm addr:$src)>;
2575 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2576 (VCVTPS2PDZrm addr:$src)>;
2577}
2578
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame^]2579//===----------------------------------------------------------------------===//
2580// Half precision conversion instructions
2581//===----------------------------------------------------------------------===//
2582multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2583 X86MemOperand x86memop, Intrinsic Int> {
2584 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2585 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2586 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2587 let neverHasSideEffects = 1, mayLoad = 1 in
2588 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2589 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2590}
2591
2592multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2593 X86MemOperand x86memop, Intrinsic Int> {
2594 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2595 (ins srcRC:$src1, i32i8imm:$src2),
2596 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2597 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2598 let neverHasSideEffects = 1, mayStore = 1 in
2599 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2600 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2601 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2602}
2603
2604defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2605 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2606 EVEX_CD8<32, CD8VH>;
2607defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2608 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2609 EVEX_CD8<32, CD8VH>;
2610
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2611let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2612 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2613 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2614 EVEX_CD8<32, CD8VT1>;
2615 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2616 "ucomisd{z}">, TB, OpSize, EVEX,
2617 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2618 let Pattern = []<dag> in {
2619 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2620 "comiss{z}">, TB, EVEX, VEX_LIG,
2621 EVEX_CD8<32, CD8VT1>;
2622 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2623 "comisd{z}">, TB, OpSize, EVEX,
2624 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2625 }
2626 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2627 load, "ucomiss">, TB, EVEX, VEX_LIG,
2628 EVEX_CD8<32, CD8VT1>;
2629 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2630 load, "ucomisd">, TB, OpSize, EVEX,
2631 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2632
2633 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2634 load, "comiss">, TB, EVEX, VEX_LIG,
2635 EVEX_CD8<32, CD8VT1>;
2636 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2637 load, "comisd">, TB, OpSize, EVEX,
2638 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2639}
2640
2641/// avx512_unop_p - AVX-512 unops in packed form.
2642multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2643 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2644 !strconcat(OpcodeStr,
2645 "ps\t{$src, $dst|$dst, $src}"),
2646 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2647 EVEX, EVEX_V512;
2648 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2649 !strconcat(OpcodeStr,
2650 "ps\t{$src, $dst|$dst, $src}"),
2651 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2652 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2653 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2654 !strconcat(OpcodeStr,
2655 "pd\t{$src, $dst|$dst, $src}"),
2656 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2657 EVEX, EVEX_V512, VEX_W;
2658 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2659 !strconcat(OpcodeStr,
2660 "pd\t{$src, $dst|$dst, $src}"),
2661 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2662 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2663}
2664
2665/// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2666multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2667 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2668 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2669 !strconcat(OpcodeStr,
2670 "ps\t{$src, $dst|$dst, $src}"),
2671 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2672 EVEX, EVEX_V512;
2673 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2674 !strconcat(OpcodeStr,
2675 "ps\t{$src, $dst|$dst, $src}"),
2676 [(set VR512:$dst,
2677 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2678 EVEX_V512, EVEX_CD8<32, CD8VF>;
2679 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2680 !strconcat(OpcodeStr,
2681 "pd\t{$src, $dst|$dst, $src}"),
2682 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2683 EVEX, EVEX_V512, VEX_W;
2684 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2685 !strconcat(OpcodeStr,
2686 "pd\t{$src, $dst|$dst, $src}"),
2687 [(set VR512:$dst,
2688 (V8F64Int (memopv8f64 addr:$src)))]>,
2689 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2690}
2691
2692/// avx512_fp_unop_s - AVX-512 unops in scalar form.
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2693multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2694 let hasSideEffects = 0 in {
2695 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2696 (ins FR32X:$src1, FR32X:$src2),
2697 !strconcat(OpcodeStr,
2698 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2699 []>, EVEX_4V;
2700 let mayLoad = 1 in {
2701 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2702 (ins FR32X:$src1, f32mem:$src2),
2703 !strconcat(OpcodeStr,
2704 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2705 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2706 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2707 (ins VR128X:$src1, ssmem:$src2),
2708 !strconcat(OpcodeStr,
2709 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2710 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2711 }
2712 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2713 (ins FR64X:$src1, FR64X:$src2),
2714 !strconcat(OpcodeStr,
2715 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2716 EVEX_4V, VEX_W;
2717 let mayLoad = 1 in {
2718 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2719 (ins FR64X:$src1, f64mem:$src2),
2720 !strconcat(OpcodeStr,
2721 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2722 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2723 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2724 (ins VR128X:$src1, sdmem:$src2),
2725 !strconcat(OpcodeStr,
2726 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2727 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2728 }
2729}
2730}
2731
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2732defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2733 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2734 avx512_fp_unop_p_int<0x4C, "vrcp14",
2735 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2736
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2737defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2738 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2739 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2740 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2741
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2742def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2743 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2744 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2745 VR128X)>;
2746def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2747 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2748
2749def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2750 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2751 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2752 VR128X)>;
2753def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2754 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2755
2756let AddedComplexity = 20, Predicates = [HasERI] in {
2757defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2758 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2759 avx512_fp_unop_p_int<0xCA, "vrcp28",
2760 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2761
2762defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2763 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2764 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2765 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2766}
2767
2768let Predicates = [HasERI] in {
2769 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2770 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2771 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2772 VR128X)>;
2773 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2774 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2775
2776 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2777 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2778 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2779 VR128X)>;
2780 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2781 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2782}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2783multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2784 Intrinsic V16F32Int, Intrinsic V8F64Int,
2785 OpndItins itins_s, OpndItins itins_d> {
2786 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2787 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2788 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2789 EVEX, EVEX_V512;
2790
2791 let mayLoad = 1 in
2792 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2793 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2794 [(set VR512:$dst,
2795 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2796 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2797
2798 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2799 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2800 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2801 EVEX, EVEX_V512;
2802
2803 let mayLoad = 1 in
2804 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2805 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2806 [(set VR512:$dst, (OpNode
2807 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2808 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2809
2810 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2811 !strconcat(OpcodeStr,
2812 "ps\t{$src, $dst|$dst, $src}"),
2813 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2814 EVEX, EVEX_V512;
2815 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2816 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2817 [(set VR512:$dst,
2818 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2819 EVEX_V512, EVEX_CD8<32, CD8VF>;
2820 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2821 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2822 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2823 EVEX, EVEX_V512, VEX_W;
2824 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2825 !strconcat(OpcodeStr,
2826 "pd\t{$src, $dst|$dst, $src}"),
2827 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2828 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2829}
2830
2831multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2832 Intrinsic F32Int, Intrinsic F64Int,
2833 OpndItins itins_s, OpndItins itins_d> {
2834 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2835 (ins FR32X:$src1, FR32X:$src2),
2836 !strconcat(OpcodeStr,
2837 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2838 [], itins_s.rr>, XS, EVEX_4V;
2839 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2840 (ins VR128X:$src1, VR128X:$src2),
2841 !strconcat(OpcodeStr,
2842 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2843 [(set VR128X:$dst,
2844 (F32Int VR128X:$src1, VR128X:$src2))],
2845 itins_s.rr>, XS, EVEX_4V;
2846 let mayLoad = 1 in {
2847 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2848 (ins FR32X:$src1, f32mem:$src2),
2849 !strconcat(OpcodeStr,
2850 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2851 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2852 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2853 (ins VR128X:$src1, ssmem:$src2),
2854 !strconcat(OpcodeStr,
2855 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2856 [(set VR128X:$dst,
2857 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2858 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2859 }
2860 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2861 (ins FR64X:$src1, FR64X:$src2),
2862 !strconcat(OpcodeStr,
2863 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2864 XD, EVEX_4V, VEX_W;
2865 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2866 (ins VR128X:$src1, VR128X:$src2),
2867 !strconcat(OpcodeStr,
2868 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2869 [(set VR128X:$dst,
2870 (F64Int VR128X:$src1, VR128X:$src2))],
2871 itins_s.rr>, XD, EVEX_4V, VEX_W;
2872 let mayLoad = 1 in {
2873 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2874 (ins FR64X:$src1, f64mem:$src2),
2875 !strconcat(OpcodeStr,
2876 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2877 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2878 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2879 (ins VR128X:$src1, sdmem:$src2),
2880 !strconcat(OpcodeStr,
2881 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2882 [(set VR128X:$dst,
2883 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2884 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2885 }
2886}
2887
2888
2889defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2890 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2891 SSE_SQRTSS, SSE_SQRTSD>,
2892 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2893 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2894 SSE_SQRTPS, SSE_SQRTPD>;
2895
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2896let Predicates = [HasAVX512] in {
2897 def : Pat<(f32 (fsqrt FR32X:$src)),
2898 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2899 def : Pat<(f32 (fsqrt (load addr:$src))),
2900 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2901 Requires<[OptForSize]>;
2902 def : Pat<(f64 (fsqrt FR64X:$src)),
2903 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2904 def : Pat<(f64 (fsqrt (load addr:$src))),
2905 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2906 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2907
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2908 def : Pat<(f32 (X86frsqrt FR32X:$src)),
2909 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2910 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2911 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2912 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2913
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2914 def : Pat<(f32 (X86frcp FR32X:$src)),
2915 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2916 def : Pat<(f32 (X86frcp (load addr:$src))),
2917 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2918 Requires<[OptForSize]>;
2919
2920 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
2921 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
2922 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2923 VR128X)>;
2924 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2925 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2926
2927 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
2928 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
2929 (COPY_TO_REGCLASS VR128X:$src, FR64)),
2930 VR128X)>;
2931 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2932 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2933}
2934
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2935
2936multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2937 X86MemOperand x86memop, RegisterClass RC,
2938 PatFrag mem_frag32, PatFrag mem_frag64,
2939 Intrinsic V4F32Int, Intrinsic V2F64Int,
2940 CD8VForm VForm> {
2941let ExeDomain = SSEPackedSingle in {
2942 // Intrinsic operation, reg.
2943 // Vector intrinsic operation, reg
2944 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2945 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2946 !strconcat(OpcodeStr,
2947 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2948 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2949
2950 // Vector intrinsic operation, mem
2951 def PSm : AVX512AIi8<opcps, MRMSrcMem,
2952 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2953 !strconcat(OpcodeStr,
2954 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2955 [(set RC:$dst,
2956 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
2957 EVEX_CD8<32, VForm>;
2958} // ExeDomain = SSEPackedSingle
2959
2960let ExeDomain = SSEPackedDouble in {
2961 // Vector intrinsic operation, reg
2962 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
2963 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2964 !strconcat(OpcodeStr,
2965 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2966 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
2967
2968 // Vector intrinsic operation, mem
2969 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
2970 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2971 !strconcat(OpcodeStr,
2972 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2973 [(set RC:$dst,
2974 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
2975 EVEX_CD8<64, VForm>;
2976} // ExeDomain = SSEPackedDouble
2977}
2978
2979multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
2980 string OpcodeStr,
2981 Intrinsic F32Int,
2982 Intrinsic F64Int> {
2983let ExeDomain = GenericDomain in {
2984 // Operation, reg.
2985 let hasSideEffects = 0 in
2986 def SSr : AVX512AIi8<opcss, MRMSrcReg,
2987 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
2988 !strconcat(OpcodeStr,
2989 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2990 []>;
2991
2992 // Intrinsic operation, reg.
2993 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
2994 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2995 !strconcat(OpcodeStr,
2996 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2997 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
2998
2999 // Intrinsic operation, mem.
3000 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3001 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3002 !strconcat(OpcodeStr,
3003 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3004 [(set VR128X:$dst, (F32Int VR128X:$src1,
3005 sse_load_f32:$src2, imm:$src3))]>,
3006 EVEX_CD8<32, CD8VT1>;
3007
3008 // Operation, reg.
3009 let hasSideEffects = 0 in
3010 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3011 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3012 !strconcat(OpcodeStr,
3013 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3014 []>, VEX_W;
3015
3016 // Intrinsic operation, reg.
3017 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3018 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3019 !strconcat(OpcodeStr,
3020 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3021 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3022 VEX_W;
3023
3024 // Intrinsic operation, mem.
3025 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3026 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3027 !strconcat(OpcodeStr,
3028 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3029 [(set VR128X:$dst,
3030 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3031 VEX_W, EVEX_CD8<64, CD8VT1>;
3032} // ExeDomain = GenericDomain
3033}
3034
3035let Predicates = [HasAVX512] in {
3036 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3037 int_x86_avx512_rndscale_ss,
3038 int_x86_avx512_rndscale_sd>, EVEX_4V;
3039
3040 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3041 memopv16f32, memopv8f64,
3042 int_x86_avx512_rndscale_ps_512,
3043 int_x86_avx512_rndscale_pd_512, CD8VF>,
3044 EVEX, EVEX_V512;
3045}
3046
3047def : Pat<(ffloor FR32X:$src),
3048 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3049def : Pat<(f64 (ffloor FR64X:$src)),
3050 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3051def : Pat<(f32 (fnearbyint FR32X:$src)),
3052 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3053def : Pat<(f64 (fnearbyint FR64X:$src)),
3054 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3055def : Pat<(f32 (fceil FR32X:$src)),
3056 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3057def : Pat<(f64 (fceil FR64X:$src)),
3058 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3059def : Pat<(f32 (frint FR32X:$src)),
3060 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3061def : Pat<(f64 (frint FR64X:$src)),
3062 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3063def : Pat<(f32 (ftrunc FR32X:$src)),
3064 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3065def : Pat<(f64 (ftrunc FR64X:$src)),
3066 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3067
3068def : Pat<(v16f32 (ffloor VR512:$src)),
3069 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3070def : Pat<(v16f32 (fnearbyint VR512:$src)),
3071 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3072def : Pat<(v16f32 (fceil VR512:$src)),
3073 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3074def : Pat<(v16f32 (frint VR512:$src)),
3075 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3076def : Pat<(v16f32 (ftrunc VR512:$src)),
3077 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3078
3079def : Pat<(v8f64 (ffloor VR512:$src)),
3080 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3081def : Pat<(v8f64 (fnearbyint VR512:$src)),
3082 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3083def : Pat<(v8f64 (fceil VR512:$src)),
3084 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3085def : Pat<(v8f64 (frint VR512:$src)),
3086 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3087def : Pat<(v8f64 (ftrunc VR512:$src)),
3088 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3089
3090//-------------------------------------------------
3091// Integer truncate and extend operations
3092//-------------------------------------------------
3093
3094multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3095 RegisterClass dstRC, RegisterClass srcRC,
3096 RegisterClass KRC, X86MemOperand x86memop> {
3097 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3098 (ins srcRC:$src),
3099 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3100 []>, EVEX;
3101
3102 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3103 (ins KRC:$mask, srcRC:$src),
3104 !strconcat(OpcodeStr,
3105 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3106 []>, EVEX, EVEX_KZ;
3107
3108 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3109 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3110 []>, EVEX;
3111}
3112defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3113 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3114defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3115 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3116defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3117 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3118defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3119 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3120defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3121 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3122defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3123 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3124defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3125 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3126defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3127 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3128defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3129 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3130defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3131 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3132defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3133 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3134defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3135 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3136defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3137 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3138defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3139 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3140defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3141 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3142
3143def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3144def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3145def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3146def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3147def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3148
3149def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3150 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3151def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3152 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3153def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3154 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3155def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3156 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3157
3158
3159multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3160 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3161 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3162
3163 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3164 (ins SrcRC:$src),
3165 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3166 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3167 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3168 (ins x86memop:$src),
3169 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3170 [(set DstRC:$dst,
3171 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3172 EVEX;
3173}
3174
3175defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3176 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3177 EVEX_CD8<8, CD8VQ>;
3178defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3179 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3180 EVEX_CD8<8, CD8VO>;
3181defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3182 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3183 EVEX_CD8<16, CD8VH>;
3184defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3185 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3186 EVEX_CD8<16, CD8VQ>;
3187defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3188 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3189 EVEX_CD8<32, CD8VH>;
3190
3191defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3192 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3193 EVEX_CD8<8, CD8VQ>;
3194defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3195 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3196 EVEX_CD8<8, CD8VO>;
3197defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3198 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3199 EVEX_CD8<16, CD8VH>;
3200defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3201 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3202 EVEX_CD8<16, CD8VQ>;
3203defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3204 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3205 EVEX_CD8<32, CD8VH>;
3206
3207//===----------------------------------------------------------------------===//
3208// GATHER - SCATTER Operations
3209
3210multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3211 RegisterClass RC, X86MemOperand memop> {
3212let mayLoad = 1,
3213 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3214 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3215 (ins RC:$src1, KRC:$mask, memop:$src2),
3216 !strconcat(OpcodeStr,
3217 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3218 []>, EVEX, EVEX_K;
3219}
3220defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3221 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3222defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3223 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3224
3225defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3226 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3227defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3228 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3229
3230defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3231 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3232defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3233 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3234
3235defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3236 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3237defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3238 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3239
3240multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3241 RegisterClass RC, X86MemOperand memop> {
3242let mayStore = 1, Constraints = "$mask = $mask_wb" in
3243 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3244 (ins memop:$dst, KRC:$mask, RC:$src2),
3245 !strconcat(OpcodeStr,
3246 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3247 []>, EVEX, EVEX_K;
3248}
3249
3250defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3251 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3252defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3253 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3254
3255defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3256 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3257defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3258 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3259
3260defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3261 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3262defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3263 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3264
3265defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3266 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3267defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3268 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3269
3270//===----------------------------------------------------------------------===//
3271// VSHUFPS - VSHUFPD Operations
3272
3273multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3274 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3275 Domain d> {
3276 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3277 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3278 !strconcat(OpcodeStr,
3279 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3280 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3281 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3282 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3283 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3284 (ins RC:$src1, RC:$src2, i8imm:$src3),
3285 !strconcat(OpcodeStr,
3286 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3287 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3288 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3289 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3290}
3291
3292defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3293 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3294defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3295 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3296
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]3297def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3298 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3299def : Pat<(v16i32 (X86Shufp VR512:$src1,
3300 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3301 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3302
3303def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3304 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3305def : Pat<(v8i64 (X86Shufp VR512:$src1,
3306 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3307 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3308
3309multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3310 X86MemOperand x86memop> {
3311 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3312 (ins RC:$src1, RC:$src2, i8imm:$src3),
3313 !strconcat(OpcodeStr,
3314 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3315 []>, EVEX_4V;
3316 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3317 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3318 !strconcat(OpcodeStr,
3319 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3320 []>, EVEX_4V;
3321}
3322defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3323 EVEX_V512, EVEX_CD8<32, CD8VF>;
3324defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3325 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3326
3327def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3328 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3329def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3330 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3331def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3332 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3333def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3334 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3335
3336multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3337 X86MemOperand x86memop> {
3338 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3339 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3340 EVEX;
3341 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3342 (ins x86memop:$src),
3343 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3344 EVEX;
3345}
3346
3347defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3348 EVEX_CD8<32, CD8VF>;
3349defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3350 EVEX_CD8<64, CD8VF>;
3351