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Alex Bradbury89718422017-10-19 21:37:38 +00001//===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that RISCV uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
17
18#include "RISCV.h"
19#include "llvm/CodeGen/SelectionDAG.h"
David Blaikieb3bde2e2017-11-17 01:07:10 +000020#include "llvm/CodeGen/TargetLowering.h"
Alex Bradbury89718422017-10-19 21:37:38 +000021
22namespace llvm {
23class RISCVSubtarget;
24namespace RISCVISD {
25enum NodeType : unsigned {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Alex Bradburya3376752017-11-08 13:41:21 +000027 RET_FLAG,
Alex Bradbury65385162017-11-21 07:51:32 +000028 CALL,
Alex Bradbury0b4175f2018-04-12 05:34:25 +000029 SELECT_CC,
30 BuildPairF64,
31 SplitF64
Alex Bradbury89718422017-10-19 21:37:38 +000032};
33}
34
35class RISCVTargetLowering : public TargetLowering {
36 const RISCVSubtarget &Subtarget;
37
38public:
39 explicit RISCVTargetLowering(const TargetMachine &TM,
40 const RISCVSubtarget &STI);
41
Alex Bradbury09926292018-04-26 12:13:48 +000042 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
43 unsigned AS,
44 Instruction *I = nullptr) const override;
Alex Bradburydcbff632018-04-26 13:15:17 +000045 bool isLegalICmpImmediate(int64_t Imm) const override;
Alex Bradbury5c41ece2018-04-26 13:00:37 +000046 bool isLegalAddImmediate(int64_t Imm) const override;
Alex Bradbury130b8b32018-04-26 13:37:00 +000047 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
48 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
Alex Bradbury15e894b2018-04-26 14:04:18 +000049 bool isZExtFree(SDValue Val, EVT VT2) const override;
Alex Bradbury09926292018-04-26 12:13:48 +000050
Alex Bradbury89718422017-10-19 21:37:38 +000051 // Provide custom lowering hooks for some operations.
52 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
53
54 // This method returns the name of a target specific DAG node.
55 const char *getTargetNodeName(unsigned Opcode) const override;
56
Alex Bradbury9330e642018-01-10 20:05:09 +000057 std::pair<unsigned, const TargetRegisterClass *>
58 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
59 StringRef Constraint, MVT VT) const override;
60
Alex Bradbury65385162017-11-21 07:51:32 +000061 MachineBasicBlock *
62 EmitInstrWithCustomInserter(MachineInstr &MI,
63 MachineBasicBlock *BB) const override;
64
Shiva Chenbbf4c5c2018-02-02 02:43:18 +000065 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
66 EVT VT) const override;
67
Alex Bradbury89718422017-10-19 21:37:38 +000068private:
Alex Bradburydc31c612017-12-11 12:49:02 +000069 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
70 const SmallVectorImpl<ISD::InputArg> &Ins,
71 bool IsRet) const;
72 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
73 const SmallVectorImpl<ISD::OutputArg> &Outs,
Alex Bradburyc85be0d2018-01-10 19:41:03 +000074 bool IsRet, CallLoweringInfo *CLI) const;
Alex Bradbury89718422017-10-19 21:37:38 +000075 // Lower incoming arguments, copy physregs into vregs
76 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
77 bool IsVarArg,
78 const SmallVectorImpl<ISD::InputArg> &Ins,
79 const SDLoc &DL, SelectionDAG &DAG,
80 SmallVectorImpl<SDValue> &InVals) const override;
Alex Bradburydc31c612017-12-11 12:49:02 +000081 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
82 bool IsVarArg,
83 const SmallVectorImpl<ISD::OutputArg> &Outs,
84 LLVMContext &Context) const override;
Alex Bradbury89718422017-10-19 21:37:38 +000085 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
86 const SmallVectorImpl<ISD::OutputArg> &Outs,
87 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
88 SelectionDAG &DAG) const override;
Alex Bradburya3376752017-11-08 13:41:21 +000089 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
90 SmallVectorImpl<SDValue> &InVals) const override;
Alex Bradbury89718422017-10-19 21:37:38 +000091 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
92 Type *Ty) const override {
93 return true;
94 }
Alex Bradburyec8aa912017-11-08 13:24:21 +000095 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
Alex Bradburyffc435e2017-11-21 08:11:03 +000096 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
Alex Bradbury80c8eb72018-03-20 13:26:12 +000097 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
Alex Bradburyffc435e2017-11-21 08:11:03 +000098 SDValue lowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
Alex Bradbury65385162017-11-21 07:51:32 +000099 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000100 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
Alex Bradbury70f137b2018-01-10 20:12:00 +0000101 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Alex Bradbury89718422017-10-19 21:37:38 +0000103};
104}
105
106#endif